1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 241904360SSuravee Suthikulpanit/* 341904360SSuravee Suthikulpanit * DTS file for AMD Seattle SoC 441904360SSuravee Suthikulpanit * 541904360SSuravee Suthikulpanit * Copyright (C) 2014 Advanced Micro Devices, Inc. 641904360SSuravee Suthikulpanit */ 741904360SSuravee Suthikulpanit 841904360SSuravee Suthikulpanit/ { 941904360SSuravee Suthikulpanit compatible = "amd,seattle"; 1041904360SSuravee Suthikulpanit interrupt-parent = <&gic0>; 1141904360SSuravee Suthikulpanit #address-cells = <2>; 1241904360SSuravee Suthikulpanit #size-cells = <2>; 1341904360SSuravee Suthikulpanit 1441904360SSuravee Suthikulpanit gic0: interrupt-controller@e1101000 { 1541904360SSuravee Suthikulpanit compatible = "arm,gic-400", "arm,cortex-a15-gic"; 1641904360SSuravee Suthikulpanit interrupt-controller; 1741904360SSuravee Suthikulpanit #interrupt-cells = <3>; 1841904360SSuravee Suthikulpanit #address-cells = <2>; 1941904360SSuravee Suthikulpanit #size-cells = <2>; 2041904360SSuravee Suthikulpanit reg = <0x0 0xe1110000 0 0x1000>, 2141904360SSuravee Suthikulpanit <0x0 0xe112f000 0 0x2000>, 2248527738SBrijesh Singh <0x0 0xe1140000 0 0x2000>, 2348527738SBrijesh Singh <0x0 0xe1160000 0 0x2000>; 2441904360SSuravee Suthikulpanit interrupts = <1 9 0xf04>; 2541904360SSuravee Suthikulpanit ranges = <0 0 0 0xe1100000 0 0x100000>; 2641904360SSuravee Suthikulpanit v2m0: v2m@e0080000 { 2741904360SSuravee Suthikulpanit compatible = "arm,gic-v2m-frame"; 2841904360SSuravee Suthikulpanit msi-controller; 2941904360SSuravee Suthikulpanit reg = <0x0 0x00080000 0 0x1000>; 3041904360SSuravee Suthikulpanit }; 3141904360SSuravee Suthikulpanit }; 3241904360SSuravee Suthikulpanit 3341904360SSuravee Suthikulpanit timer { 3441904360SSuravee Suthikulpanit compatible = "arm,armv8-timer"; 3541904360SSuravee Suthikulpanit interrupts = <1 13 0xff04>, 3641904360SSuravee Suthikulpanit <1 14 0xff04>, 3741904360SSuravee Suthikulpanit <1 11 0xff04>, 3841904360SSuravee Suthikulpanit <1 10 0xff04>; 3941904360SSuravee Suthikulpanit }; 4041904360SSuravee Suthikulpanit 4141904360SSuravee Suthikulpanit smb0: smb { 4241904360SSuravee Suthikulpanit compatible = "simple-bus"; 4341904360SSuravee Suthikulpanit #address-cells = <2>; 4441904360SSuravee Suthikulpanit #size-cells = <2>; 4541904360SSuravee Suthikulpanit ranges; 4641904360SSuravee Suthikulpanit 47c91cb912SSuravee Suthikulpanit /* 48c91cb912SSuravee Suthikulpanit * dma-ranges is 40-bit address space containing: 49c91cb912SSuravee Suthikulpanit * - GICv2m MSI register is at 0xe0080000 50c91cb912SSuravee Suthikulpanit * - DRAM range [0x8000000000 to 0xffffffffff] 51c91cb912SSuravee Suthikulpanit */ 52c91cb912SSuravee Suthikulpanit dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 5341904360SSuravee Suthikulpanit 5441904360SSuravee Suthikulpanit /include/ "amd-seattle-clks.dtsi" 5541904360SSuravee Suthikulpanit 5641904360SSuravee Suthikulpanit sata0: sata@e0300000 { 5741904360SSuravee Suthikulpanit compatible = "snps,dwc-ahci"; 587973a3fbSSuravee Suthikulpanit reg = <0 0xe0300000 0 0xf0000>; 5941904360SSuravee Suthikulpanit interrupts = <0 355 4>; 6041904360SSuravee Suthikulpanit clocks = <&sataclk_333mhz>; 61*429863e7SArd Biesheuvel iommus = <&sata0_smmu 0x0 0x1f>; 6241904360SSuravee Suthikulpanit dma-coherent; 6341904360SSuravee Suthikulpanit }; 6441904360SSuravee Suthikulpanit 657973a3fbSSuravee Suthikulpanit /* This is for Rev B only */ 667973a3fbSSuravee Suthikulpanit sata1: sata@e0d00000 { 677973a3fbSSuravee Suthikulpanit status = "disabled"; 687973a3fbSSuravee Suthikulpanit compatible = "snps,dwc-ahci"; 697973a3fbSSuravee Suthikulpanit reg = <0 0xe0d00000 0 0xf0000>; 707973a3fbSSuravee Suthikulpanit interrupts = <0 354 4>; 717973a3fbSSuravee Suthikulpanit clocks = <&sataclk_333mhz>; 72*429863e7SArd Biesheuvel iommus = <&sata1_smmu 0x0e>, 73*429863e7SArd Biesheuvel <&sata1_smmu 0x0f>, 74*429863e7SArd Biesheuvel <&sata1_smmu 0x1e>; 75*429863e7SArd Biesheuvel dma-coherent; 76*429863e7SArd Biesheuvel }; 77*429863e7SArd Biesheuvel 78*429863e7SArd Biesheuvel sata0_smmu: iommu@e0200000 { 79*429863e7SArd Biesheuvel compatible = "arm,mmu-401"; 80*429863e7SArd Biesheuvel reg = <0 0xe0200000 0 0x10000>; 81*429863e7SArd Biesheuvel #global-interrupts = <1>; 82*429863e7SArd Biesheuvel interrupts = <0 332 4>, <0 332 4>; 83*429863e7SArd Biesheuvel #iommu-cells = <2>; 84*429863e7SArd Biesheuvel dma-coherent; 85*429863e7SArd Biesheuvel }; 86*429863e7SArd Biesheuvel 87*429863e7SArd Biesheuvel sata1_smmu: iommu@e0c00000 { 88*429863e7SArd Biesheuvel compatible = "arm,mmu-401"; 89*429863e7SArd Biesheuvel reg = <0 0xe0c00000 0 0x10000>; 90*429863e7SArd Biesheuvel #global-interrupts = <1>; 91*429863e7SArd Biesheuvel interrupts = <0 331 4>, <0 331 4>; 92*429863e7SArd Biesheuvel #iommu-cells = <1>; 937973a3fbSSuravee Suthikulpanit dma-coherent; 947973a3fbSSuravee Suthikulpanit }; 957973a3fbSSuravee Suthikulpanit 9641904360SSuravee Suthikulpanit i2c0: i2c@e1000000 { 9741904360SSuravee Suthikulpanit status = "disabled"; 9841904360SSuravee Suthikulpanit compatible = "snps,designware-i2c"; 9941904360SSuravee Suthikulpanit reg = <0 0xe1000000 0 0x1000>; 10041904360SSuravee Suthikulpanit interrupts = <0 357 4>; 1011584fd13SSuravee Suthikulpanit clocks = <&miscclk_250mhz>; 1021584fd13SSuravee Suthikulpanit }; 1031584fd13SSuravee Suthikulpanit 1041584fd13SSuravee Suthikulpanit i2c1: i2c@e0050000 { 1051584fd13SSuravee Suthikulpanit status = "disabled"; 1061584fd13SSuravee Suthikulpanit compatible = "snps,designware-i2c"; 1071584fd13SSuravee Suthikulpanit reg = <0 0xe0050000 0 0x1000>; 1081584fd13SSuravee Suthikulpanit interrupts = <0 340 4>; 1091584fd13SSuravee Suthikulpanit clocks = <&miscclk_250mhz>; 11041904360SSuravee Suthikulpanit }; 11141904360SSuravee Suthikulpanit 11241904360SSuravee Suthikulpanit serial0: serial@e1010000 { 11341904360SSuravee Suthikulpanit compatible = "arm,pl011", "arm,primecell"; 11441904360SSuravee Suthikulpanit reg = <0 0xe1010000 0 0x1000>; 11541904360SSuravee Suthikulpanit interrupts = <0 328 4>; 11641904360SSuravee Suthikulpanit clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; 11741904360SSuravee Suthikulpanit clock-names = "uartclk", "apb_pclk"; 11841904360SSuravee Suthikulpanit }; 11941904360SSuravee Suthikulpanit 120e9f0878cSRob Herring spi0: spi@e1020000 { 12141904360SSuravee Suthikulpanit status = "disabled"; 12241904360SSuravee Suthikulpanit compatible = "arm,pl022", "arm,primecell"; 12341904360SSuravee Suthikulpanit reg = <0 0xe1020000 0 0x1000>; 12441904360SSuravee Suthikulpanit spi-controller; 12541904360SSuravee Suthikulpanit interrupts = <0 330 4>; 12641904360SSuravee Suthikulpanit clocks = <&uartspiclk_100mhz>; 12741904360SSuravee Suthikulpanit clock-names = "apb_pclk"; 12841904360SSuravee Suthikulpanit }; 12941904360SSuravee Suthikulpanit 130e9f0878cSRob Herring spi1: spi@e1030000 { 13141904360SSuravee Suthikulpanit status = "disabled"; 13241904360SSuravee Suthikulpanit compatible = "arm,pl022", "arm,primecell"; 13341904360SSuravee Suthikulpanit reg = <0 0xe1030000 0 0x1000>; 13441904360SSuravee Suthikulpanit spi-controller; 13541904360SSuravee Suthikulpanit interrupts = <0 329 4>; 13641904360SSuravee Suthikulpanit clocks = <&uartspiclk_100mhz>; 13741904360SSuravee Suthikulpanit clock-names = "apb_pclk"; 13841904360SSuravee Suthikulpanit num-cs = <1>; 13941904360SSuravee Suthikulpanit #address-cells = <1>; 14041904360SSuravee Suthikulpanit #size-cells = <0>; 14141904360SSuravee Suthikulpanit }; 14241904360SSuravee Suthikulpanit 143ce00c22fSSuravee Suthikulpanit gpio0: gpio@e1040000 { /* Not available to OS for B0 */ 14441904360SSuravee Suthikulpanit status = "disabled"; 14541904360SSuravee Suthikulpanit compatible = "arm,pl061", "arm,primecell"; 14641904360SSuravee Suthikulpanit #gpio-cells = <2>; 14741904360SSuravee Suthikulpanit reg = <0 0xe1040000 0 0x1000>; 14841904360SSuravee Suthikulpanit gpio-controller; 14941904360SSuravee Suthikulpanit interrupts = <0 359 4>; 15041904360SSuravee Suthikulpanit interrupt-controller; 15141904360SSuravee Suthikulpanit #interrupt-cells = <2>; 152ce00c22fSSuravee Suthikulpanit clocks = <&miscclk_250mhz>; 15341904360SSuravee Suthikulpanit clock-names = "apb_pclk"; 15441904360SSuravee Suthikulpanit }; 15541904360SSuravee Suthikulpanit 156ce00c22fSSuravee Suthikulpanit gpio1: gpio@e1050000 { /* [0:7] */ 15741904360SSuravee Suthikulpanit status = "disabled"; 15841904360SSuravee Suthikulpanit compatible = "arm,pl061", "arm,primecell"; 15941904360SSuravee Suthikulpanit #gpio-cells = <2>; 16041904360SSuravee Suthikulpanit reg = <0 0xe1050000 0 0x1000>; 16141904360SSuravee Suthikulpanit gpio-controller; 162ce00c22fSSuravee Suthikulpanit interrupt-controller; 163ce00c22fSSuravee Suthikulpanit #interrupt-cells = <2>; 16441904360SSuravee Suthikulpanit interrupts = <0 358 4>; 165ce00c22fSSuravee Suthikulpanit clocks = <&miscclk_250mhz>; 166ce00c22fSSuravee Suthikulpanit clock-names = "apb_pclk"; 167ce00c22fSSuravee Suthikulpanit }; 168ce00c22fSSuravee Suthikulpanit 169ce00c22fSSuravee Suthikulpanit gpio2: gpio@e0020000 { /* [8:15] */ 170ce00c22fSSuravee Suthikulpanit status = "disabled"; 171ce00c22fSSuravee Suthikulpanit compatible = "arm,pl061", "arm,primecell"; 172ce00c22fSSuravee Suthikulpanit #gpio-cells = <2>; 173ce00c22fSSuravee Suthikulpanit reg = <0 0xe0020000 0 0x1000>; 174ce00c22fSSuravee Suthikulpanit gpio-controller; 175ce00c22fSSuravee Suthikulpanit interrupt-controller; 176ce00c22fSSuravee Suthikulpanit #interrupt-cells = <2>; 177ce00c22fSSuravee Suthikulpanit interrupts = <0 366 4>; 178ce00c22fSSuravee Suthikulpanit clocks = <&miscclk_250mhz>; 179ce00c22fSSuravee Suthikulpanit clock-names = "apb_pclk"; 180ce00c22fSSuravee Suthikulpanit }; 181ce00c22fSSuravee Suthikulpanit 182ce00c22fSSuravee Suthikulpanit gpio3: gpio@e0030000 { /* [16:23] */ 183ce00c22fSSuravee Suthikulpanit status = "disabled"; 184ce00c22fSSuravee Suthikulpanit compatible = "arm,pl061", "arm,primecell"; 185ce00c22fSSuravee Suthikulpanit #gpio-cells = <2>; 186ce00c22fSSuravee Suthikulpanit reg = <0 0xe0030000 0 0x1000>; 187ce00c22fSSuravee Suthikulpanit gpio-controller; 188ce00c22fSSuravee Suthikulpanit interrupt-controller; 189ce00c22fSSuravee Suthikulpanit #interrupt-cells = <2>; 190ce00c22fSSuravee Suthikulpanit interrupts = <0 365 4>; 191ce00c22fSSuravee Suthikulpanit clocks = <&miscclk_250mhz>; 192ce00c22fSSuravee Suthikulpanit clock-names = "apb_pclk"; 193ce00c22fSSuravee Suthikulpanit }; 194ce00c22fSSuravee Suthikulpanit 195ce00c22fSSuravee Suthikulpanit gpio4: gpio@e0080000 { /* [24] */ 196ce00c22fSSuravee Suthikulpanit status = "disabled"; 197ce00c22fSSuravee Suthikulpanit compatible = "arm,pl061", "arm,primecell"; 198ce00c22fSSuravee Suthikulpanit #gpio-cells = <2>; 199ce00c22fSSuravee Suthikulpanit reg = <0 0xe0080000 0 0x1000>; 200ce00c22fSSuravee Suthikulpanit gpio-controller; 201ce00c22fSSuravee Suthikulpanit interrupt-controller; 202ce00c22fSSuravee Suthikulpanit #interrupt-cells = <2>; 203ce00c22fSSuravee Suthikulpanit interrupts = <0 361 4>; 204ce00c22fSSuravee Suthikulpanit clocks = <&miscclk_250mhz>; 20541904360SSuravee Suthikulpanit clock-names = "apb_pclk"; 20641904360SSuravee Suthikulpanit }; 20741904360SSuravee Suthikulpanit 20841904360SSuravee Suthikulpanit ccp0: ccp@e0100000 { 20941904360SSuravee Suthikulpanit status = "disabled"; 21041904360SSuravee Suthikulpanit compatible = "amd,ccp-seattle-v1a"; 21141904360SSuravee Suthikulpanit reg = <0 0xe0100000 0 0x10000>; 21241904360SSuravee Suthikulpanit interrupts = <0 3 4>; 21341904360SSuravee Suthikulpanit dma-coherent; 214*429863e7SArd Biesheuvel iommus = <&sata1_smmu 0x00>, 215*429863e7SArd Biesheuvel <&sata1_smmu 0x02>, 216*429863e7SArd Biesheuvel <&sata1_smmu 0x40>, 217*429863e7SArd Biesheuvel <&sata1_smmu 0x42>; 21841904360SSuravee Suthikulpanit }; 21941904360SSuravee Suthikulpanit 22041904360SSuravee Suthikulpanit pcie0: pcie@f0000000 { 22141904360SSuravee Suthikulpanit compatible = "pci-host-ecam-generic"; 22241904360SSuravee Suthikulpanit #address-cells = <3>; 22341904360SSuravee Suthikulpanit #size-cells = <2>; 22441904360SSuravee Suthikulpanit #interrupt-cells = <1>; 22541904360SSuravee Suthikulpanit device_type = "pci"; 22670bcc9baSSuravee Suthikulpanit bus-range = <0 0x7f>; 22741904360SSuravee Suthikulpanit msi-parent = <&v2m0>; 22841904360SSuravee Suthikulpanit reg = <0 0xf0000000 0 0x10000000>; 22941904360SSuravee Suthikulpanit 230acd9208eSArd Biesheuvel interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 23141904360SSuravee Suthikulpanit interrupt-map = 232acd9208eSArd Biesheuvel <0x1100 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>, 233acd9208eSArd Biesheuvel <0x1100 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>, 234acd9208eSArd Biesheuvel <0x1100 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>, 235acd9208eSArd Biesheuvel <0x1100 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>, 236acd9208eSArd Biesheuvel 237acd9208eSArd Biesheuvel <0x1200 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x124 0x1>, 238acd9208eSArd Biesheuvel <0x1200 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x125 0x1>, 239acd9208eSArd Biesheuvel <0x1200 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x126 0x1>, 240acd9208eSArd Biesheuvel <0x1200 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x127 0x1>, 241acd9208eSArd Biesheuvel 242acd9208eSArd Biesheuvel <0x1300 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x128 0x1>, 243acd9208eSArd Biesheuvel <0x1300 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x129 0x1>, 244acd9208eSArd Biesheuvel <0x1300 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x12a 0x1>, 245acd9208eSArd Biesheuvel <0x1300 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x12b 0x1>; 24641904360SSuravee Suthikulpanit 24741904360SSuravee Suthikulpanit dma-coherent; 248c91cb912SSuravee Suthikulpanit dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; 24941904360SSuravee Suthikulpanit ranges = 25041904360SSuravee Suthikulpanit /* I/O Memory (size=64K) */ 25141904360SSuravee Suthikulpanit <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, 25241904360SSuravee Suthikulpanit /* 32-bit MMIO (size=2G) */ 25341904360SSuravee Suthikulpanit <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>, 254acd9208eSArd Biesheuvel /* 64-bit MMIO (size= 508G) */ 25541904360SSuravee Suthikulpanit <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; 256dd5c1606SArd Biesheuvel iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; 257dd5c1606SArd Biesheuvel }; 258dd5c1606SArd Biesheuvel 259dd5c1606SArd Biesheuvel pcie_smmu: iommu@e0a00000 { 260dd5c1606SArd Biesheuvel compatible = "arm,mmu-401"; 261dd5c1606SArd Biesheuvel reg = <0 0xe0a00000 0 0x10000>; 262dd5c1606SArd Biesheuvel #global-interrupts = <1>; 263dd5c1606SArd Biesheuvel interrupts = <0 333 4>, <0 333 4>; 264dd5c1606SArd Biesheuvel #iommu-cells = <1>; 265dd5c1606SArd Biesheuvel dma-coherent; 26641904360SSuravee Suthikulpanit }; 267fb8d5e09SSuravee Suthikulpanit 268fb8d5e09SSuravee Suthikulpanit /* Perf CCN504 PMU */ 26918f94513SSuravee Suthikulpanit ccn: ccn@e8000000 { 270fb8d5e09SSuravee Suthikulpanit compatible = "arm,ccn-504"; 271fb8d5e09SSuravee Suthikulpanit reg = <0x0 0xe8000000 0 0x1000000>; 272fb8d5e09SSuravee Suthikulpanit interrupts = <0 380 4>; 273fb8d5e09SSuravee Suthikulpanit }; 27471edbebbSBrijesh Singh 27571edbebbSBrijesh Singh ipmi_kcs: kcs@e0010000 { 27671edbebbSBrijesh Singh status = "disabled"; 27771edbebbSBrijesh Singh compatible = "ipmi-kcs"; 27871edbebbSBrijesh Singh device_type = "ipmi"; 27971edbebbSBrijesh Singh reg = <0x0 0xe0010000 0 0x8>; 28071edbebbSBrijesh Singh interrupts = <0 389 4>; 28171edbebbSBrijesh Singh reg-size = <1>; 28271edbebbSBrijesh Singh reg-spacing = <4>; 28371edbebbSBrijesh Singh }; 28441904360SSuravee Suthikulpanit }; 28541904360SSuravee Suthikulpanit}; 286