1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 252f69f81SVladimir Zapolskiy /* 352f69f81SVladimir Zapolskiy * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 452f69f81SVladimir Zapolskiy */ 552f69f81SVladimir Zapolskiy 652f69f81SVladimir Zapolskiy #ifndef _LPC32XX_CPU_H 752f69f81SVladimir Zapolskiy #define _LPC32XX_CPU_H 852f69f81SVladimir Zapolskiy 952f69f81SVladimir Zapolskiy /* LPC32XX Memory map */ 1052f69f81SVladimir Zapolskiy 1152f69f81SVladimir Zapolskiy /* AHB physical base addresses */ 1252f69f81SVladimir Zapolskiy #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ 1352f69f81SVladimir Zapolskiy #define SSP0_BASE 0x20084000 /* SSP0 registers base */ 1452f69f81SVladimir Zapolskiy #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ 1552f69f81SVladimir Zapolskiy #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ 1652f69f81SVladimir Zapolskiy #define DMA_BASE 0x31000000 /* DMA controller registers base */ 1752f69f81SVladimir Zapolskiy #define USB_BASE 0x31020000 /* USB registers base */ 1852f69f81SVladimir Zapolskiy #define LCD_BASE 0x31040000 /* LCD registers base */ 1952f69f81SVladimir Zapolskiy #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ 2052f69f81SVladimir Zapolskiy #define EMC_BASE 0x31080000 /* EMC configuration registers base */ 2152f69f81SVladimir Zapolskiy 2252f69f81SVladimir Zapolskiy /* FAB peripherals base addresses */ 2352f69f81SVladimir Zapolskiy #define CLK_PM_BASE 0x40004000 /* System control registers base */ 2452f69f81SVladimir Zapolskiy #define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ 2552f69f81SVladimir Zapolskiy #define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ 2652f69f81SVladimir Zapolskiy #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ 2752f69f81SVladimir Zapolskiy #define RTC_BASE 0x40024000 /* RTC registers base */ 2852f69f81SVladimir Zapolskiy #define GPIO_BASE 0x40028000 /* GPIO registers base */ 29d75b532aSSylvain Lemieux #define MUX_BASE 0x40028000 /* MUX registers base */ 3052f69f81SVladimir Zapolskiy #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ 3152f69f81SVladimir Zapolskiy #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ 3252f69f81SVladimir Zapolskiy #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ 3352f69f81SVladimir Zapolskiy #define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ 3452f69f81SVladimir Zapolskiy 3552f69f81SVladimir Zapolskiy /* APB peripherals base addresses */ 3652f69f81SVladimir Zapolskiy #define UART3_BASE 0x40080000 /* UART 3 registers base */ 3752f69f81SVladimir Zapolskiy #define UART4_BASE 0x40088000 /* UART 4 registers base */ 3852f69f81SVladimir Zapolskiy #define UART5_BASE 0x40090000 /* UART 5 registers base */ 3952f69f81SVladimir Zapolskiy #define UART6_BASE 0x40098000 /* UART 6 registers base */ 405e862b95SAlbert ARIBAUD \(3ADEV\) #define I2C1_BASE 0x400A0000 /* I2C 1 registers base */ 415e862b95SAlbert ARIBAUD \(3ADEV\) #define I2C2_BASE 0x400A8000 /* I2C 2 registers base */ 4252f69f81SVladimir Zapolskiy 4352f69f81SVladimir Zapolskiy /* External SDRAM Memory Bank base addresses */ 4452f69f81SVladimir Zapolskiy #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ 4552f69f81SVladimir Zapolskiy #define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ 4652f69f81SVladimir Zapolskiy 4752f69f81SVladimir Zapolskiy /* External Static Memory Bank base addresses */ 4852f69f81SVladimir Zapolskiy #define EMC_CS0_BASE 0xE0000000 4952f69f81SVladimir Zapolskiy #define EMC_CS1_BASE 0xE1000000 5052f69f81SVladimir Zapolskiy #define EMC_CS2_BASE 0xE2000000 5152f69f81SVladimir Zapolskiy #define EMC_CS3_BASE 0xE3000000 5252f69f81SVladimir Zapolskiy 5352f69f81SVladimir Zapolskiy #endif /* _LPC32XX_CPU_H */ 54