1d3532910SArnd Bergmann /* SPDX-License-Identifier: GPL-2.0-or-later */ 2d3532910SArnd Bergmann /* 3d3532910SArnd Bergmann * arch/arm/mach-lpc32xx/include/mach/platform.h 4d3532910SArnd Bergmann * 5d3532910SArnd Bergmann * Author: Kevin Wells <kevin.wells@nxp.com> 6d3532910SArnd Bergmann * 7d3532910SArnd Bergmann * Copyright (C) 2010 NXP Semiconductors 8d3532910SArnd Bergmann */ 9d3532910SArnd Bergmann 10d3532910SArnd Bergmann #ifndef __ARM_LPC32XX_H 11d3532910SArnd Bergmann #define __ARM_LPC32XX_H 12d3532910SArnd Bergmann 13d3532910SArnd Bergmann #define _SBF(f, v) ((v) << (f)) 14d3532910SArnd Bergmann #define _BIT(n) _SBF(n, 1) 15d3532910SArnd Bergmann 16d3532910SArnd Bergmann /* 17d3532910SArnd Bergmann * AHB 0 physical base addresses 18d3532910SArnd Bergmann */ 19d3532910SArnd Bergmann #define LPC32XX_SLC_BASE 0x20020000 20d3532910SArnd Bergmann #define LPC32XX_SSP0_BASE 0x20084000 21d3532910SArnd Bergmann #define LPC32XX_SPI1_BASE 0x20088000 22d3532910SArnd Bergmann #define LPC32XX_SSP1_BASE 0x2008C000 23d3532910SArnd Bergmann #define LPC32XX_SPI2_BASE 0x20090000 24d3532910SArnd Bergmann #define LPC32XX_I2S0_BASE 0x20094000 25d3532910SArnd Bergmann #define LPC32XX_SD_BASE 0x20098000 26d3532910SArnd Bergmann #define LPC32XX_I2S1_BASE 0x2009C000 27d3532910SArnd Bergmann #define LPC32XX_MLC_BASE 0x200A8000 28d3532910SArnd Bergmann #define LPC32XX_AHB0_START LPC32XX_SLC_BASE 29d3532910SArnd Bergmann #define LPC32XX_AHB0_SIZE 0x00089000 30d3532910SArnd Bergmann 31d3532910SArnd Bergmann /* 32d3532910SArnd Bergmann * AHB 1 physical base addresses 33d3532910SArnd Bergmann */ 34d3532910SArnd Bergmann #define LPC32XX_DMA_BASE 0x31000000 35d3532910SArnd Bergmann #define LPC32XX_USB_BASE 0x31020000 36d3532910SArnd Bergmann #define LPC32XX_USBH_BASE 0x31020000 37d3532910SArnd Bergmann #define LPC32XX_USB_OTG_BASE 0x31020000 38d3532910SArnd Bergmann #define LPC32XX_OTG_I2C_BASE 0x31020300 39d3532910SArnd Bergmann #define LPC32XX_LCD_BASE 0x31040000 40d3532910SArnd Bergmann #define LPC32XX_ETHERNET_BASE 0x31060000 41d3532910SArnd Bergmann #define LPC32XX_EMC_BASE 0x31080000 42d3532910SArnd Bergmann #define LPC32XX_ETB_CFG_BASE 0x310C0000 43d3532910SArnd Bergmann #define LPC32XX_ETB_DATA_BASE 0x310E0000 44d3532910SArnd Bergmann #define LPC32XX_AHB1_START LPC32XX_DMA_BASE 45d3532910SArnd Bergmann #define LPC32XX_AHB1_SIZE 0x000E1000 46d3532910SArnd Bergmann 47d3532910SArnd Bergmann /* 48d3532910SArnd Bergmann * FAB physical base addresses 49d3532910SArnd Bergmann */ 50d3532910SArnd Bergmann #define LPC32XX_CLK_PM_BASE 0x40004000 51d3532910SArnd Bergmann #define LPC32XX_MIC_BASE 0x40008000 52d3532910SArnd Bergmann #define LPC32XX_SIC1_BASE 0x4000C000 53d3532910SArnd Bergmann #define LPC32XX_SIC2_BASE 0x40010000 54d3532910SArnd Bergmann #define LPC32XX_HS_UART1_BASE 0x40014000 55d3532910SArnd Bergmann #define LPC32XX_HS_UART2_BASE 0x40018000 56d3532910SArnd Bergmann #define LPC32XX_HS_UART7_BASE 0x4001C000 57d3532910SArnd Bergmann #define LPC32XX_RTC_BASE 0x40024000 58d3532910SArnd Bergmann #define LPC32XX_RTC_RAM_BASE 0x40024080 59d3532910SArnd Bergmann #define LPC32XX_GPIO_BASE 0x40028000 60d3532910SArnd Bergmann #define LPC32XX_PWM3_BASE 0x4002C000 61d3532910SArnd Bergmann #define LPC32XX_PWM4_BASE 0x40030000 62d3532910SArnd Bergmann #define LPC32XX_MSTIM_BASE 0x40034000 63d3532910SArnd Bergmann #define LPC32XX_HSTIM_BASE 0x40038000 64d3532910SArnd Bergmann #define LPC32XX_WDTIM_BASE 0x4003C000 65d3532910SArnd Bergmann #define LPC32XX_DEBUG_CTRL_BASE 0x40040000 66d3532910SArnd Bergmann #define LPC32XX_TIMER0_BASE 0x40044000 67d3532910SArnd Bergmann #define LPC32XX_ADC_BASE 0x40048000 68d3532910SArnd Bergmann #define LPC32XX_TIMER1_BASE 0x4004C000 69d3532910SArnd Bergmann #define LPC32XX_KSCAN_BASE 0x40050000 70d3532910SArnd Bergmann #define LPC32XX_UART_CTRL_BASE 0x40054000 71d3532910SArnd Bergmann #define LPC32XX_TIMER2_BASE 0x40058000 72d3532910SArnd Bergmann #define LPC32XX_PWM1_BASE 0x4005C000 73d3532910SArnd Bergmann #define LPC32XX_PWM2_BASE 0x4005C004 74d3532910SArnd Bergmann #define LPC32XX_TIMER3_BASE 0x40060000 75d3532910SArnd Bergmann 76d3532910SArnd Bergmann /* 77d3532910SArnd Bergmann * APB physical base addresses 78d3532910SArnd Bergmann */ 79d3532910SArnd Bergmann #define LPC32XX_UART3_BASE 0x40080000 80d3532910SArnd Bergmann #define LPC32XX_UART4_BASE 0x40088000 81d3532910SArnd Bergmann #define LPC32XX_UART5_BASE 0x40090000 82d3532910SArnd Bergmann #define LPC32XX_UART6_BASE 0x40098000 83d3532910SArnd Bergmann #define LPC32XX_I2C1_BASE 0x400A0000 84d3532910SArnd Bergmann #define LPC32XX_I2C2_BASE 0x400A8000 85d3532910SArnd Bergmann 86d3532910SArnd Bergmann /* 87d3532910SArnd Bergmann * FAB and APB base and sizing 88d3532910SArnd Bergmann */ 89d3532910SArnd Bergmann #define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE 90d3532910SArnd Bergmann #define LPC32XX_FABAPB_SIZE 0x000A5000 91d3532910SArnd Bergmann 92d3532910SArnd Bergmann /* 93d3532910SArnd Bergmann * Internal memory bases and sizes 94d3532910SArnd Bergmann */ 95d3532910SArnd Bergmann #define LPC32XX_IRAM_BASE 0x08000000 96d3532910SArnd Bergmann #define LPC32XX_IROM_BASE 0x0C000000 97d3532910SArnd Bergmann 98d3532910SArnd Bergmann /* 99d3532910SArnd Bergmann * External Static Memory Bank Address Space Bases 100d3532910SArnd Bergmann */ 101d3532910SArnd Bergmann #define LPC32XX_EMC_CS0_BASE 0xE0000000 102d3532910SArnd Bergmann #define LPC32XX_EMC_CS1_BASE 0xE1000000 103d3532910SArnd Bergmann #define LPC32XX_EMC_CS2_BASE 0xE2000000 104d3532910SArnd Bergmann #define LPC32XX_EMC_CS3_BASE 0xE3000000 105d3532910SArnd Bergmann 106d3532910SArnd Bergmann /* 107d3532910SArnd Bergmann * External SDRAM Memory Bank Address Space Bases 108d3532910SArnd Bergmann */ 109d3532910SArnd Bergmann #define LPC32XX_EMC_DYCS0_BASE 0x80000000 110d3532910SArnd Bergmann #define LPC32XX_EMC_DYCS1_BASE 0xA0000000 111d3532910SArnd Bergmann 112d3532910SArnd Bergmann /* 113d3532910SArnd Bergmann * Clock and crystal information 114d3532910SArnd Bergmann */ 115d3532910SArnd Bergmann #define LPC32XX_MAIN_OSC_FREQ 13000000 116d3532910SArnd Bergmann #define LPC32XX_CLOCK_OSC_FREQ 32768 117d3532910SArnd Bergmann 118d3532910SArnd Bergmann /* 119d3532910SArnd Bergmann * Clock and Power control register offsets 120d3532910SArnd Bergmann */ 121d3532910SArnd Bergmann #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ 122d3532910SArnd Bergmann (x)) 123d3532910SArnd Bergmann #define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000) 124d3532910SArnd Bergmann #define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014) 125d3532910SArnd Bergmann #define LPC32XX_CLKPWR_P01_ER _PMREG(0x018) 126d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C) 127d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INT_ER _PMREG(0x020) 128d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INT_RS _PMREG(0x024) 129d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INT_SR _PMREG(0x028) 130d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C) 131d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030) 132d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034) 133d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038) 134d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C) 135d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040) 136d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044) 137d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048) 138d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C) 139d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050) 140d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054) 141d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058) 142d3532910SArnd Bergmann #define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060) 143d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064) 144d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068) 145d3532910SArnd Bergmann #define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C) 146d3532910SArnd Bergmann #define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070) 147d3532910SArnd Bergmann #define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074) 148d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078) 149d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C) 150d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080) 151d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090) 152d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4) 153d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8) 154d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC) 155d3532910SArnd Bergmann #define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0) 156d3532910SArnd Bergmann #define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4) 157d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8) 158d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC) 159d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0) 160d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4) 161d3532910SArnd Bergmann #define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8) 162d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0) 163d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4) 164d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8) 165d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC) 166d3532910SArnd Bergmann #define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0) 167d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4) 168d3532910SArnd Bergmann #define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8) 169d3532910SArnd Bergmann #define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC) 170d3532910SArnd Bergmann #define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x)) 171d3532910SArnd Bergmann 172d3532910SArnd Bergmann /* 173d3532910SArnd Bergmann * clkpwr_debug_ctrl register definitions 174d3532910SArnd Bergmann */ 175d3532910SArnd Bergmann #define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4) 176d3532910SArnd Bergmann 177d3532910SArnd Bergmann /* 178d3532910SArnd Bergmann * clkpwr_bootmap register definitions 179d3532910SArnd Bergmann */ 180d3532910SArnd Bergmann #define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1) 181d3532910SArnd Bergmann 182d3532910SArnd Bergmann /* 183d3532910SArnd Bergmann * clkpwr_start_gpio register bit definitions 184d3532910SArnd Bergmann */ 185d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31) 186d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30) 187d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29) 188d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28) 189d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27) 190d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26) 191d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25) 192d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24) 193d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23) 194d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22) 195d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21) 196d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20) 197d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19) 198d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18) 199d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17) 200d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16) 201d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15) 202d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14) 203d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13) 204d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12) 205d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11) 206d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10) 207d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9) 208d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8) 209d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7) 210d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6) 211d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5) 212d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4) 213d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3) 214d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2) 215d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1) 216d3532910SArnd Bergmann #define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0) 217d3532910SArnd Bergmann 218d3532910SArnd Bergmann /* 219d3532910SArnd Bergmann * clkpwr_usbclk_pdiv register definitions 220d3532910SArnd Bergmann */ 221d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF 222d3532910SArnd Bergmann 223d3532910SArnd Bergmann /* 224d3532910SArnd Bergmann * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int, 225d3532910SArnd Bergmann * clkpwr_start_pol_int, register bit definitions 226d3532910SArnd Bergmann */ 227d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31) 228d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30) 229d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29) 230d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26) 231d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25) 232d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24) 233d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23) 234d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22) 235d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21) 236d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20) 237d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19) 238d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16) 239d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7) 240d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6) 241d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5) 242d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4) 243d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3) 244d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2) 245d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1) 246d3532910SArnd Bergmann #define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0) 247d3532910SArnd Bergmann 248d3532910SArnd Bergmann /* 249d3532910SArnd Bergmann * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin, 250d3532910SArnd Bergmann * clkpwr_start_pol_pin register bit definitions 251d3532910SArnd Bergmann */ 252d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31) 253d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30) 254d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28) 255d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26) 256d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25) 257d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24) 258d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23) 259d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22) 260d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21) 261d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18) 262d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17) 263d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16) 264d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15) 265d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14) 266d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13) 267d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12) 268d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11) 269d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10) 270d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9) 271d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8) 272d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7) 273d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6) 274d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5) 275d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4) 276d3532910SArnd Bergmann #define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3) 277d3532910SArnd Bergmann 278d3532910SArnd Bergmann /* 279d3532910SArnd Bergmann * clkpwr_hclk_div register definitions 280d3532910SArnd Bergmann */ 281d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7) 282d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7) 283d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7) 284d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2) 285d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3) 286d3532910SArnd Bergmann 287d3532910SArnd Bergmann /* 288d3532910SArnd Bergmann * clkpwr_pwr_ctrl register definitions 289d3532910SArnd Bergmann */ 290d3532910SArnd Bergmann #define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10) 291d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9) 292d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8) 293d3532910SArnd Bergmann #define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7) 294d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5) 295d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4) 296d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3) 297d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2) 298d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1) 299d3532910SArnd Bergmann #define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0) 300d3532910SArnd Bergmann 301d3532910SArnd Bergmann /* 302d3532910SArnd Bergmann * clkpwr_pll397_ctrl register definitions 303d3532910SArnd Bergmann */ 304d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10) 305d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9) 306d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000 307d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040 308d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080 309d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0 310d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100 311d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140 312d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180 313d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0 314d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0 315d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1) 316d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0) 317d3532910SArnd Bergmann 318d3532910SArnd Bergmann /* 319d3532910SArnd Bergmann * clkpwr_main_osc_ctrl register definitions 320d3532910SArnd Bergmann */ 321d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2) 322d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2) 323d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TEST_MODE _BIT(1) 324d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0) 325d3532910SArnd Bergmann 326d3532910SArnd Bergmann /* 327d3532910SArnd Bergmann * clkpwr_sysclk_ctrl register definitions 328d3532910SArnd Bergmann */ 329d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2) 330d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2) 331d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1) 332d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0) 333d3532910SArnd Bergmann 334d3532910SArnd Bergmann /* 335d3532910SArnd Bergmann * clkpwr_lcdclk_ctrl register definitions 336d3532910SArnd Bergmann */ 337d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000 338d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040 339d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080 340d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0 341d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100 342d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140 343d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180 344d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0 345d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0 346d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020 347d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F) 348d3532910SArnd Bergmann #define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F 349d3532910SArnd Bergmann 350d3532910SArnd Bergmann /* 351d3532910SArnd Bergmann * clkpwr_hclkpll_ctrl register definitions 352d3532910SArnd Bergmann */ 353d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16) 354d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15) 355d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14) 356d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13) 357d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11) 358d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) 359d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1) 360d3532910SArnd Bergmann #define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0) 361d3532910SArnd Bergmann 362d3532910SArnd Bergmann /* 363d3532910SArnd Bergmann * clkpwr_adc_clk_ctrl_1 register definitions 364d3532910SArnd Bergmann */ 365d3532910SArnd Bergmann #define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0) 366d3532910SArnd Bergmann #define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8) 367d3532910SArnd Bergmann 368d3532910SArnd Bergmann /* 369d3532910SArnd Bergmann * clkpwr_usb_ctrl register definitions 370d3532910SArnd Bergmann */ 371d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24) 372d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23) 373d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22) 374d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21) 375d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19) 376d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19) 377d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19) 378d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18) 379d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17) 380d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16) 381d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15) 382d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14) 383d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13) 384d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) 385d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) 386d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) 387d3532910SArnd Bergmann #define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0) 388d3532910SArnd Bergmann 389d3532910SArnd Bergmann /* 390d3532910SArnd Bergmann * clkpwr_sdramclk_ctrl register definitions 391d3532910SArnd Bergmann */ 392d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22) 393d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21) 394d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20) 395d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19) 396d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14) 397d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13) 398d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10) 399d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9) 400d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8) 401d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7) 402d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2) 403d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1) 404d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0) 405d3532910SArnd Bergmann 406d3532910SArnd Bergmann /* 407d3532910SArnd Bergmann * clkpwr_ssp_blk_ctrl register definitions 408d3532910SArnd Bergmann */ 409d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5) 410d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4) 411d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3) 412d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2) 413d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1) 414d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0) 415d3532910SArnd Bergmann 416d3532910SArnd Bergmann /* 417d3532910SArnd Bergmann * clkpwr_i2s_clk_ctrl register definitions 418d3532910SArnd Bergmann */ 419d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6) 420d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5) 421d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4) 422d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3) 423d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2) 424d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1) 425d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0) 426d3532910SArnd Bergmann 427d3532910SArnd Bergmann /* 428d3532910SArnd Bergmann * clkpwr_ms_ctrl register definitions 429d3532910SArnd Bergmann */ 430d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10) 431d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9) 432d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8) 433d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7) 434d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6) 435d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5) 436d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF) 437d3532910SArnd Bergmann 438d3532910SArnd Bergmann /* 439d3532910SArnd Bergmann * clkpwr_macclk_ctrl register definitions 440d3532910SArnd Bergmann */ 441d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00 442d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08 443d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18 444d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18 445d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2) 446d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1) 447d3532910SArnd Bergmann #define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0) 448d3532910SArnd Bergmann 449d3532910SArnd Bergmann /* 450d3532910SArnd Bergmann * clkpwr_test_clk_sel register definitions 451d3532910SArnd Bergmann */ 452d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5) 453d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5) 454d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5) 455d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5) 456d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4) 457d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1) 458d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1) 459d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1) 460d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1) 461d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1) 462d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1) 463d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0) 464d3532910SArnd Bergmann 465d3532910SArnd Bergmann /* 466d3532910SArnd Bergmann * clkpwr_sw_int register definitions 467d3532910SArnd Bergmann */ 468d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1)) 469d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1) 470d3532910SArnd Bergmann 471d3532910SArnd Bergmann /* 472d3532910SArnd Bergmann * clkpwr_i2c_clk_ctrl register definitions 473d3532910SArnd Bergmann */ 474d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4) 475d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3) 476d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2) 477d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1) 478d3532910SArnd Bergmann #define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0) 479d3532910SArnd Bergmann 480d3532910SArnd Bergmann /* 481d3532910SArnd Bergmann * clkpwr_key_clk_ctrl register definitions 482d3532910SArnd Bergmann */ 483d3532910SArnd Bergmann #define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1 484d3532910SArnd Bergmann 485d3532910SArnd Bergmann /* 486d3532910SArnd Bergmann * clkpwr_adc_clk_ctrl register definitions 487d3532910SArnd Bergmann */ 488d3532910SArnd Bergmann #define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1 489d3532910SArnd Bergmann 490d3532910SArnd Bergmann /* 491d3532910SArnd Bergmann * clkpwr_pwm_clk_ctrl register definitions 492d3532910SArnd Bergmann */ 493d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8) 494d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4) 495d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8 496d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4 497d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2 498d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1 499d3532910SArnd Bergmann 500d3532910SArnd Bergmann /* 501d3532910SArnd Bergmann * clkpwr_timer_clk_ctrl register definitions 502d3532910SArnd Bergmann */ 503d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2 504d3532910SArnd Bergmann #define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1 505d3532910SArnd Bergmann 506d3532910SArnd Bergmann /* 507d3532910SArnd Bergmann * clkpwr_timers_pwms_clk_ctrl_1 register definitions 508d3532910SArnd Bergmann */ 509d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40 510d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 511d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 512d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 513d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04 514d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02 515d3532910SArnd Bergmann #define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01 516d3532910SArnd Bergmann 517d3532910SArnd Bergmann /* 518d3532910SArnd Bergmann * clkpwr_spi_clk_ctrl register definitions 519d3532910SArnd Bergmann */ 520d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80 521d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40 522d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20 523d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10 524d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08 525d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04 526d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02 527d3532910SArnd Bergmann #define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01 528d3532910SArnd Bergmann 529d3532910SArnd Bergmann /* 530d3532910SArnd Bergmann * clkpwr_nand_clk_ctrl register definitions 531d3532910SArnd Bergmann */ 532d3532910SArnd Bergmann #define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20 533d3532910SArnd Bergmann #define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10 534d3532910SArnd Bergmann #define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08 535d3532910SArnd Bergmann #define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04 536d3532910SArnd Bergmann #define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02 537d3532910SArnd Bergmann #define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01 538d3532910SArnd Bergmann 539d3532910SArnd Bergmann /* 540d3532910SArnd Bergmann * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl 541d3532910SArnd Bergmann * and clkpwr_uart6_clk_ctrl register definitions 542d3532910SArnd Bergmann */ 543d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF) 544d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8) 545d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16) 546d3532910SArnd Bergmann 547d3532910SArnd Bergmann /* 548d3532910SArnd Bergmann * clkpwr_irda_clk_ctrl register definitions 549d3532910SArnd Bergmann */ 550d3532910SArnd Bergmann #define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF) 551d3532910SArnd Bergmann #define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8) 552d3532910SArnd Bergmann 553d3532910SArnd Bergmann /* 554d3532910SArnd Bergmann * clkpwr_uart_clk_ctrl register definitions 555d3532910SArnd Bergmann */ 556d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3) 557d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2) 558d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1) 559d3532910SArnd Bergmann #define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0) 560d3532910SArnd Bergmann 561d3532910SArnd Bergmann /* 562d3532910SArnd Bergmann * clkpwr_dmaclk_ctrl register definitions 563d3532910SArnd Bergmann */ 564d3532910SArnd Bergmann #define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1 565d3532910SArnd Bergmann 566d3532910SArnd Bergmann /* 567d3532910SArnd Bergmann * clkpwr_autoclock register definitions 568d3532910SArnd Bergmann */ 569d3532910SArnd Bergmann #define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40 570d3532910SArnd Bergmann #define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02 571d3532910SArnd Bergmann #define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01 572d3532910SArnd Bergmann 573d3532910SArnd Bergmann /* 574d3532910SArnd Bergmann * Interrupt controller register offsets 575d3532910SArnd Bergmann */ 576d3532910SArnd Bergmann #define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00) 577d3532910SArnd Bergmann #define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04) 578d3532910SArnd Bergmann #define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08) 579d3532910SArnd Bergmann #define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C) 580d3532910SArnd Bergmann #define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10) 581d3532910SArnd Bergmann #define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14) 582d3532910SArnd Bergmann 583d3532910SArnd Bergmann /* 584d3532910SArnd Bergmann * Timer/counter register offsets 585d3532910SArnd Bergmann */ 586d3532910SArnd Bergmann #define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) 587d3532910SArnd Bergmann #define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) 588d3532910SArnd Bergmann #define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) 589d3532910SArnd Bergmann #define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) 590d3532910SArnd Bergmann #define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) 591d3532910SArnd Bergmann #define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) 592d3532910SArnd Bergmann #define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) 593d3532910SArnd Bergmann #define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) 594d3532910SArnd Bergmann #define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) 595d3532910SArnd Bergmann #define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) 596d3532910SArnd Bergmann #define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) 597d3532910SArnd Bergmann #define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) 598d3532910SArnd Bergmann #define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) 599d3532910SArnd Bergmann #define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) 600d3532910SArnd Bergmann #define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) 601d3532910SArnd Bergmann #define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) 602d3532910SArnd Bergmann #define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) 603d3532910SArnd Bergmann 604d3532910SArnd Bergmann /* 605d3532910SArnd Bergmann * ir register definitions 606d3532910SArnd Bergmann */ 607d3532910SArnd Bergmann #define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) 608d3532910SArnd Bergmann #define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) 609d3532910SArnd Bergmann 610d3532910SArnd Bergmann /* 611d3532910SArnd Bergmann * tcr register definitions 612d3532910SArnd Bergmann */ 613d3532910SArnd Bergmann #define LPC32XX_TIMER_CNTR_TCR_EN 0x1 614d3532910SArnd Bergmann #define LPC32XX_TIMER_CNTR_TCR_RESET 0x2 615d3532910SArnd Bergmann 616d3532910SArnd Bergmann /* 617d3532910SArnd Bergmann * mcr register definitions 618d3532910SArnd Bergmann */ 619d3532910SArnd Bergmann #define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) 620d3532910SArnd Bergmann #define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) 621d3532910SArnd Bergmann #define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) 622d3532910SArnd Bergmann 623d3532910SArnd Bergmann /* 624d3532910SArnd Bergmann * Standard UART register offsets 625d3532910SArnd Bergmann */ 626d3532910SArnd Bergmann #define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00) 627d3532910SArnd Bergmann #define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04) 628d3532910SArnd Bergmann #define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08) 629d3532910SArnd Bergmann #define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C) 630d3532910SArnd Bergmann #define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10) 631d3532910SArnd Bergmann #define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14) 632d3532910SArnd Bergmann #define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18) 633d3532910SArnd Bergmann #define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C) 634d3532910SArnd Bergmann 635d3532910SArnd Bergmann /* 636d3532910SArnd Bergmann * UART control structure offsets 637d3532910SArnd Bergmann */ 638d3532910SArnd Bergmann #define _UCREG(x) io_p2v(\ 639d3532910SArnd Bergmann LPC32XX_UART_CTRL_BASE + (x)) 640d3532910SArnd Bergmann #define LPC32XX_UARTCTL_CTRL _UCREG(0x00) 641d3532910SArnd Bergmann #define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04) 642d3532910SArnd Bergmann #define LPC32XX_UARTCTL_CLOOP _UCREG(0x08) 643d3532910SArnd Bergmann 644d3532910SArnd Bergmann /* 645d3532910SArnd Bergmann * ctrl register definitions 646d3532910SArnd Bergmann */ 647d3532910SArnd Bergmann #define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11) 648d3532910SArnd Bergmann #define LPC32XX_UART_IRRX6_INV_EN _BIT(10) 649d3532910SArnd Bergmann #define LPC32XX_UART_HDPX_EN _BIT(9) 650d3532910SArnd Bergmann #define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5) 651d3532910SArnd Bergmann #define LPC32XX_RT_IRTX6_INV_EN _BIT(4) 652d3532910SArnd Bergmann #define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3) 653d3532910SArnd Bergmann #define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2) 654d3532910SArnd Bergmann #define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1) 655d3532910SArnd Bergmann #define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0) 656d3532910SArnd Bergmann 657d3532910SArnd Bergmann /* 658d3532910SArnd Bergmann * clkmode register definitions 659d3532910SArnd Bergmann */ 660d3532910SArnd Bergmann #define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F) 661d3532910SArnd Bergmann #define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1) 662d3532910SArnd Bergmann #define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14) 663d3532910SArnd Bergmann #define LPC32XX_UART_CLKMODE_OFF 0x0 664d3532910SArnd Bergmann #define LPC32XX_UART_CLKMODE_ON 0x1 665d3532910SArnd Bergmann #define LPC32XX_UART_CLKMODE_AUTO 0x2 666d3532910SArnd Bergmann #define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4)) 667d3532910SArnd Bergmann #define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4)) 668d3532910SArnd Bergmann 669d3532910SArnd Bergmann /* 670d3532910SArnd Bergmann * GPIO Module Register offsets 671d3532910SArnd Bergmann */ 672d3532910SArnd Bergmann #define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x)) 673d3532910SArnd Bergmann #define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100) 674d3532910SArnd Bergmann #define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104) 675d3532910SArnd Bergmann #define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108) 676d3532910SArnd Bergmann #define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110) 677d3532910SArnd Bergmann #define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114) 678d3532910SArnd Bergmann #define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118) 679d3532910SArnd Bergmann #define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120) 680d3532910SArnd Bergmann #define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124) 681d3532910SArnd Bergmann #define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128) 682d3532910SArnd Bergmann #define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) 683d3532910SArnd Bergmann #define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) 684d3532910SArnd Bergmann #define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) 685d3532910SArnd Bergmann #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) 686d3532910SArnd Bergmann #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) 687d3532910SArnd Bergmann #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) 688d3532910SArnd Bergmann 689d3532910SArnd Bergmann /* 690d3532910SArnd Bergmann * USB Otg Registers 691d3532910SArnd Bergmann */ 692d3532910SArnd Bergmann #define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) 693d3532910SArnd Bergmann #define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) 694d3532910SArnd Bergmann #define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) 695d3532910SArnd Bergmann 696d3532910SArnd Bergmann /* USB OTG CLK CTRL bit defines */ 697d3532910SArnd Bergmann #define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) 698d3532910SArnd Bergmann #define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) 699d3532910SArnd Bergmann #define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) 700d3532910SArnd Bergmann #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) 701d3532910SArnd Bergmann #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) 702d3532910SArnd Bergmann 703d3532910SArnd Bergmann /* 704d3532910SArnd Bergmann * Start of virtual addresses for IO devices 705d3532910SArnd Bergmann */ 706d3532910SArnd Bergmann #define IO_BASE 0xF0000000 707d3532910SArnd Bergmann 708d3532910SArnd Bergmann /* 709d3532910SArnd Bergmann * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 710d3532910SArnd Bergmann */ 711d3532910SArnd Bergmann #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ 712d3532910SArnd Bergmann IO_BASE) 713d3532910SArnd Bergmann 714d3532910SArnd Bergmann #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) 715d3532910SArnd Bergmann #define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) 716d3532910SArnd Bergmann 717d3532910SArnd Bergmann #endif 718