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/openbmc/linux/arch/powerpc/include/asm/
H A Ddisassemble.h21 return (inst >> 1) & 0x3ff; in get_xop()
26 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_sprn()
31 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_dcrn()
36 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_tmrn()
41 return (inst >> 21) & 0x1f; in get_rt()
46 return (inst >> 21) & 0x1f; in get_rs()
51 return (inst >> 16) & 0x1f; in get_ra()
56 return (inst >> 11) & 0x1f; in get_rb()
61 return inst & 0x1; in get_rc()
66 return (inst >> 11) & 0x1f; in get_ws()
[all …]
/openbmc/qemu/include/hw/intc/
H A Dloongarch_pch_pic.h14 #define PCH_PIC_INT_ID_VAL 0x7000000UL
15 #define PCH_PIC_INT_ID_VER 0x1UL
17 #define PCH_PIC_INT_ID_LO 0x00
18 #define PCH_PIC_INT_ID_HI 0x04
19 #define PCH_PIC_INT_MASK_LO 0x20
20 #define PCH_PIC_INT_MASK_HI 0x24
21 #define PCH_PIC_HTMSI_EN_LO 0x40
22 #define PCH_PIC_HTMSI_EN_HI 0x44
23 #define PCH_PIC_INT_EDGE_LO 0x60
24 #define PCH_PIC_INT_EDGE_HI 0x64
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dintr_queue.h7 #define INTRQ_CPU_MONDO_HEAD 0x3c0 /* CPU mondo head */
8 #define INTRQ_CPU_MONDO_TAIL 0x3c8 /* CPU mondo tail */
9 #define INTRQ_DEVICE_MONDO_HEAD 0x3d0 /* Device mondo head */
10 #define INTRQ_DEVICE_MONDO_TAIL 0x3d8 /* Device mondo tail */
11 #define INTRQ_RESUM_MONDO_HEAD 0x3e0 /* Resumable error mondo head */
12 #define INTRQ_RESUM_MONDO_TAIL 0x3e8 /* Resumable error mondo tail */
13 #define INTRQ_NONRESUM_MONDO_HEAD 0x3f0 /* Non-resumable error mondo head */
14 #define INTRQ_NONRESUM_MONDO_TAIL 0x3f8 /* Non-resumable error mondo head */
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dpins-imx8mq.h24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/openbmc/qemu/include/hw/display/
H A Dbochs-vbe.h12 #define VBE_DISPI_INDEX_ID 0x0
13 #define VBE_DISPI_INDEX_XRES 0x1
14 #define VBE_DISPI_INDEX_YRES 0x2
15 #define VBE_DISPI_INDEX_BPP 0x3
16 #define VBE_DISPI_INDEX_ENABLE 0x4
17 #define VBE_DISPI_INDEX_BANK 0x5
18 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
19 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
20 #define VBE_DISPI_INDEX_X_OFFSET 0x8
21 #define VBE_DISPI_INDEX_Y_OFFSET 0x9
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_mme_ctrl_lo_masks.h24 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0
25 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F
27 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20
29 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40
31 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180
33 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00
35 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000
37 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000
39 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000
41 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000
[all …]
/openbmc/linux/arch/alpha/include/asm/
H A Dvga.h57 (((a) >= 0x3b0) && ((a) < 0x3e0) && \
58 ((a) != 0x3b3) && ((a) != 0x3d3))
61 (((a) >= 0xa0000) && ((a) <= 0xc0000))
66 } while(0)
71 } while(0)
74 # define pci_vga_hose 0
75 # define __is_port_vga(a) 0
76 # define __is_mem_vga(a) 0
/openbmc/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dcache.json46 "EventCode": "0x49",
52 "EventCode": "0x59",
58 "EventCode": "0x200",
64 "EventCode": "0x202",
70 "EventCode": "0x208",
76 "EventCode": "0x209",
82 "EventCode": "0x300",
88 "EventCode": "0x302",
94 "EventCode": "0x308",
100 "EventCode": "0x309",
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
/openbmc/linux/include/linux/
H A Dtc.h29 #define TC_OLDCARD 0x3c0000
30 #define TC_NEWCARD 0x000000
32 #define TC_ROM_WIDTH 0x3e0
33 #define TC_ROM_STRIDE 0x3e4
34 #define TC_ROM_SIZE 0x3e8
35 #define TC_SLOT_SIZE 0x3ec
36 #define TC_PATTERN0 0x3f0
37 #define TC_PATTERN1 0x3f4
38 #define TC_PATTERN2 0x3f8
39 #define TC_PATTERN3 0x3fc
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra114/
H A Dpinmux.h34 PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
36 PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
39 PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
110 PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
135 PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
170 PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
176 PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
200 PMUX_DRVGRP_DAP1 = (0x28 / 4),
205 PMUX_DRVGRP_SDIO3 = (0x48 / 4),
211 PMUX_DRVGRP_SDIO1 = (0x84 / 4),
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dpinmux.h34 PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
36 PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
39 PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
110 PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
149 PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
174 PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
180 PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
183 PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
185 PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
200 PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
[all …]
/openbmc/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6q-pinfunc.h17 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
19 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
20 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
21 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
22 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
24 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
25 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
26 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-digctl.h15 mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
16 mxs_reg_32(hw_digctl_status) /* 0x010 */
17 mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
18 mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
19 mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
20 mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
21 uint32_t hw_digctl_writeonce; /* 0x060 */
23 mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */
24 mxs_reg_32(hw_digctl_bist_status) /* 0x080 */
25 uint32_t hw_digctl_entropy; /* 0x090 */
[all …]
/openbmc/qemu/hw/timer/
H A Dexynos4210_pwm.c40 ## __VA_ARGS__); } while (0)
42 #define DPRINTF(fmt, ...) do {} while (0)
46 #define EXYNOS4210_PWM_REG_MEM_SIZE 0x50
48 #define TCFG0 0x0000
49 #define TCFG1 0x0004
50 #define TCON 0x0008
51 #define TCNTB0 0x000C
52 #define TCMPB0 0x0010
53 #define TCNTO0 0x0014
54 #define TCNTB1 0x0018
[all …]
/openbmc/linux/drivers/media/pci/tw68/
H A Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
[all …]
/openbmc/linux/drivers/usb/host/
H A Dxhci-caps.h4 /* bits 7:0 - how long is the Capabilities register */
7 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
10 /* bits 0:7, Max Device Slots */
11 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
12 #define HCS_SLOTS_MASK 0xff
14 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
15 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
16 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
19 /* bits 0:3, frames or uframes that SW needs to queue transactions
21 #define HCS_IST(p) (((p) >> 0) & 0xf)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra30-pinmux.yaml147 reg = <0x70000868 0x0d0>, /* Pad control registers */
148 <0x70003000 0x3e0>; /* Mux registers */
155 nvidia,pull = <0>;
156 nvidia,tristate = <0>;
170 nvidia,tristate = <0>;
/openbmc/qemu/target/ppc/
H A Dmisc_helper.c111 raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr); in raise_fu_exception()
186 error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR", in helper_store_ptcr()
192 error_report("Invalid Partition Table size 0x" TARGET_FMT_lx in helper_store_ptcr()
244 target_ulong dpdes = 0; in helper_load_dpdes()
263 dpdes |= (0x1 << thread_id); in helper_load_dpdes()
281 ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1); in helper_store_dpdes()
291 ppc_set_irq(ccpu, PPC_INTERRUPT_DOORBELL, val & (0x1 << thread_id)); in helper_store_dpdes()
306 if (val & ~0x3f8ULL) { in helper_store_sprc()
324 switch (sprc & 0x3e0) { in helper_load_sprd()
325 case 0: /* SCRATCH0-3 */ in helper_load_sprd()
[all …]
/openbmc/linux/sound/isa/msnd/
H A Dmsnd_pinnacle.c94 snd_msnd_DAPQ(chip, 0); in snd_msnd_eval_dsp_msg()
99 chip->playDMAPos = 0; in snd_msnd_eval_dsp_msg()
110 chip->captureDMAPos = 0; in snd_msnd_eval_dsp_msg()
137 ": DSP message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
149 snd_printd(KERN_WARNING LOGNAME ": HIMT message %d 0x%02x\n", in snd_msnd_eval_dsp_msg()
173 head = 0; in snd_msnd_interrupt()
195 while (timeout-- > 0) { in snd_msnd_reset_dsp()
197 return 0; in snd_msnd_reset_dsp()
220 if (snd_msnd_reset_dsp(chip->io, &info) < 0) { in snd_msnd_probe()
229 "I/O 0x%lx-0x%lx, IRQ %d, memory mapped to 0x%lX-0x%lX\n", in snd_msnd_probe()
[all …]

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