1*5497b23eSShunsuke Nakamura[
2*5497b23eSShunsuke Nakamura  {
3*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L1I_CACHE_REFILL"
4*5497b23eSShunsuke Nakamura  },
5*5497b23eSShunsuke Nakamura  {
6*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L1I_TLB_REFILL"
7*5497b23eSShunsuke Nakamura  },
8*5497b23eSShunsuke Nakamura  {
9*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L1D_CACHE_REFILL"
10*5497b23eSShunsuke Nakamura  },
11*5497b23eSShunsuke Nakamura  {
12*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L1D_CACHE"
13*5497b23eSShunsuke Nakamura  },
14*5497b23eSShunsuke Nakamura  {
15*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L1D_TLB_REFILL"
16*5497b23eSShunsuke Nakamura  },
17*5497b23eSShunsuke Nakamura  {
18*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L1I_CACHE"
19*5497b23eSShunsuke Nakamura  },
20*5497b23eSShunsuke Nakamura  {
21*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L1D_CACHE_WB"
22*5497b23eSShunsuke Nakamura  },
23*5497b23eSShunsuke Nakamura  {
24*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L2D_CACHE"
25*5497b23eSShunsuke Nakamura  },
26*5497b23eSShunsuke Nakamura  {
27*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L2D_CACHE_REFILL"
28*5497b23eSShunsuke Nakamura  },
29*5497b23eSShunsuke Nakamura  {
30*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L2D_CACHE_WB"
31*5497b23eSShunsuke Nakamura  },
32*5497b23eSShunsuke Nakamura  {
33*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L2D_TLB_REFILL"
34*5497b23eSShunsuke Nakamura  },
35*5497b23eSShunsuke Nakamura  {
36*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L2I_TLB_REFILL"
37*5497b23eSShunsuke Nakamura  },
38*5497b23eSShunsuke Nakamura  {
39*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L2D_TLB"
40*5497b23eSShunsuke Nakamura  },
41*5497b23eSShunsuke Nakamura  {
42*5497b23eSShunsuke Nakamura    "ArchStdEvent": "L2I_TLB"
43*5497b23eSShunsuke Nakamura  },
44*5497b23eSShunsuke Nakamura  {
45*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.",
46*5497b23eSShunsuke Nakamura    "EventCode": "0x49",
47*5497b23eSShunsuke Nakamura    "EventName": "L1D_CACHE_REFILL_PRF",
48*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch."
49*5497b23eSShunsuke Nakamura  },
50*5497b23eSShunsuke Nakamura  {
51*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.",
52*5497b23eSShunsuke Nakamura    "EventCode": "0x59",
53*5497b23eSShunsuke Nakamura    "EventName": "L2D_CACHE_REFILL_PRF",
54*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch."
55*5497b23eSShunsuke Nakamura  },
56*5497b23eSShunsuke Nakamura  {
57*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.",
58*5497b23eSShunsuke Nakamura    "EventCode": "0x200",
59*5497b23eSShunsuke Nakamura    "EventName": "L1D_CACHE_REFILL_DM",
60*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access."
61*5497b23eSShunsuke Nakamura  },
62*5497b23eSShunsuke Nakamura  {
63*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.",
64*5497b23eSShunsuke Nakamura    "EventCode": "0x202",
65*5497b23eSShunsuke Nakamura    "EventName": "L1D_CACHE_REFILL_HWPRF",
66*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch."
67*5497b23eSShunsuke Nakamura  },
68*5497b23eSShunsuke Nakamura  {
69*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.",
70*5497b23eSShunsuke Nakamura    "EventCode": "0x208",
71*5497b23eSShunsuke Nakamura    "EventName": "L1_MISS_WAIT",
72*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle."
73*5497b23eSShunsuke Nakamura  },
74*5497b23eSShunsuke Nakamura  {
75*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.",
76*5497b23eSShunsuke Nakamura    "EventCode": "0x209",
77*5497b23eSShunsuke Nakamura    "EventName": "L1I_MISS_WAIT",
78*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle."
79*5497b23eSShunsuke Nakamura  },
80*5497b23eSShunsuke Nakamura  {
81*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts L2D_CACHE_REFILL caused by demand access.",
82*5497b23eSShunsuke Nakamura    "EventCode": "0x300",
83*5497b23eSShunsuke Nakamura    "EventName": "L2D_CACHE_REFILL_DM",
84*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access."
85*5497b23eSShunsuke Nakamura  },
86*5497b23eSShunsuke Nakamura  {
87*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch.",
88*5497b23eSShunsuke Nakamura    "EventCode": "0x302",
89*5497b23eSShunsuke Nakamura    "EventName": "L2D_CACHE_REFILL_HWPRF",
90*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts L2D_CACHE_REFILL caused by hardware prefetch."
91*5497b23eSShunsuke Nakamura  },
92*5497b23eSShunsuke Nakamura  {
93*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.",
94*5497b23eSShunsuke Nakamura    "EventCode": "0x308",
95*5497b23eSShunsuke Nakamura    "EventName": "L2_MISS_WAIT",
96*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle."
97*5497b23eSShunsuke Nakamura  },
98*5497b23eSShunsuke Nakamura  {
99*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts the number of times of L2 cache miss.",
100*5497b23eSShunsuke Nakamura    "EventCode": "0x309",
101*5497b23eSShunsuke Nakamura    "EventName": "L2_MISS_COUNT",
102*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts the number of times of L2 cache miss."
103*5497b23eSShunsuke Nakamura  },
104*5497b23eSShunsuke Nakamura  {
105*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.",
106*5497b23eSShunsuke Nakamura    "EventCode": "0x325",
107*5497b23eSShunsuke Nakamura    "EventName": "L2D_SWAP_DM",
108*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch."
109*5497b23eSShunsuke Nakamura  },
110*5497b23eSShunsuke Nakamura  {
111*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.",
112*5497b23eSShunsuke Nakamura    "EventCode": "0x326",
113*5497b23eSShunsuke Nakamura    "EventName": "L2D_CACHE_MIBMCH_PRF",
114*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access."
115*5497b23eSShunsuke Nakamura  },
116*5497b23eSShunsuke Nakamura  {
117*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch.",
118*5497b23eSShunsuke Nakamura    "EventCode": "0x396",
119*5497b23eSShunsuke Nakamura    "EventName": "L2D_CACHE_SWAP_LOCAL",
120*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts operations where demand access hits an L2 cache refill buffer allocated by software or hardware prefetch."
121*5497b23eSShunsuke Nakamura  },
122*5497b23eSShunsuke Nakamura  {
123*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts energy consumption per cycle of L2 cache.",
124*5497b23eSShunsuke Nakamura    "EventCode": "0x3E0",
125*5497b23eSShunsuke Nakamura    "EventName": "EA_L2",
126*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts energy consumption per cycle of L2 cache."
127*5497b23eSShunsuke Nakamura  }
128*5497b23eSShunsuke Nakamura]
129