Lines Matching +full:0 +full:x3e0
15 mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
16 mxs_reg_32(hw_digctl_status) /* 0x010 */
17 mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
18 mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
19 mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
20 mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
21 uint32_t hw_digctl_writeonce; /* 0x060 */
23 mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */
24 mxs_reg_32(hw_digctl_bist_status) /* 0x080 */
25 uint32_t hw_digctl_entropy; /* 0x090 */
27 uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
32 mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */
33 uint32_t hw_digctl_dbgrd; /* 0x0d0 */
35 uint32_t hw_digctl_dbg; /* 0x0e0 */
40 mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */
41 mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */
42 mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */
43 mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */
44 mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */
45 mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */
46 mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */
47 mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */
48 mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */
49 mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */
50 mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
51 mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
52 mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
53 mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
54 mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
58 uint32_t hw_digctl_scratch0; /* 0x280 */
60 uint32_t hw_digctl_scratch1; /* 0x290 */
62 uint32_t hw_digctl_armcache; /* 0x2a0 */
64 mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
65 uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */
67 uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */
69 uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */
71 uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */
73 uint32_t hw_digctl_fsl; /* 0x300 */
75 uint32_t hw_digctl_chipid; /* 0x310 */
80 uint32_t hw_digctl_ahb_stats_select; /* 0x330 */
85 uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */
87 uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */
89 uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */
91 uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */
93 uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */
95 uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */
97 uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */
99 uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */
101 uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */
106 uint32_t hw_digctl_mpte0_loc; /* 0x500 */
108 uint32_t hw_digctl_mpte1_loc; /* 0x510 */
110 uint32_t hw_digctl_mpte2_loc; /* 0x520 */
112 uint32_t hw_digctl_mpte3_loc; /* 0x530 */
114 uint32_t hw_digctl_mpte4_loc; /* 0x540 */
116 uint32_t hw_digctl_mpte5_loc; /* 0x550 */
118 uint32_t hw_digctl_mpte6_loc; /* 0x560 */
120 uint32_t hw_digctl_mpte7_loc; /* 0x570 */
122 uint32_t hw_digctl_mpte8_loc; /* 0x580 */
124 uint32_t hw_digctl_mpte9_loc; /* 0x590 */
126 uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */
128 uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */
130 uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */
132 uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */
134 uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */
136 uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */
142 #define HW_DIGCTL_CHIPID_MASK (0xffff << 16)
143 #define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16)
144 #define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16)