Lines Matching +full:0 +full:x3e0

34 	PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
36 	PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
39 	PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
110 	PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
149 	PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
174 	PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
180 	PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
183 	PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
185 	PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
200 	PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
214 	PMUX_DRVGRP_DAP1 = (0x28 / 4),
219 	PMUX_DRVGRP_SDIO3 = (0x48 / 4),
225 	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
226 	PMUX_DRVGRP_DDC = (0x94 / 4),
228 	PMUX_DRVGRP_GME = (0xa8 / 4),
236 	PMUX_DRVGRP_CEC = (0xd0 / 4),
237 	PMUX_DRVGRP_AT6 = (0x12c / 4),
240 	PMUX_DRVGRP_AO3 = (0x140 / 4),
241 	PMUX_DRVGRP_AO0 = (0x148 / 4),
243 	PMUX_DRVGRP_SDIO4 = (0x15c / 4),
344 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
345 #define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820