Lines Matching +full:0 +full:x3e0

4 /* bits 7:0 - how long is the Capabilities register */
7 #define HC_VERSION(p)		(((p) >> 16) & 0xffff)
10 /* bits 0:7, Max Device Slots */
11 #define HCS_MAX_SLOTS(p)	(((p) >> 0) & 0xff)
12 #define HCS_SLOTS_MASK		0xff
14 #define HCS_MAX_INTRS(p)	(((p) >> 8) & 0x7ff)
15 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
16 #define HCS_MAX_PORTS(p)	(((p) >> 24) & 0x7f)
19 /* bits 0:3, frames or uframes that SW needs to queue transactions
21 #define HCS_IST(p)		(((p) >> 0) & 0xf)
23 #define HCS_ERST_MAX(p)		(((p) >> 4) & 0xf)
27 #define HCS_MAX_SCRATCHPAD(p)   ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
30 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
31 #define HCS_U1_LATENCY(p)	(((p) >> 0) & 0xff)
33 #define HCS_U2_LATENCY(p)	(((p) >> 16) & 0xffff)
37 #define HCC_64BIT_ADDR(p)	((p) & (1 << 0))
59 #define HCC_MAX_PSA(p)		(1 << ((((p) >> 12) & 0xf) + 1))
65 /* db_off bitmask - bits 0:1 reserved */
66 #define	DBOFF_MASK	(~0x3)
68 /* run_regs_off bitmask - bits 0:4 reserved */
69 #define	RTSOFF_MASK	(~0x1f)
73 #define	HCC2_U3C(p)		((p) & (1 << 0))