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/openbmc/linux/include/linux/mfd/wm8350/
H A Dpmic.h19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/loongson/
H A Dloongson,ls2k-pmc.yaml65 reg = <0x1fe27000 0x58>;
68 loongson,suspend-address = <0x0 0x1c000500>;
72 offset = <0x30>;
73 mask = <0x1>;
79 offset = <0x14>;
80 mask = <0x3c00>;
81 value = <0x3c00>;
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-stm32/
H A Dstm32f.h10 #define STM32_PERIPH_BASE 0x40000000UL
12 #define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
13 #define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
15 #define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800)
16 #define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00)
/openbmc/u-boot/board/toradex/apalis-tk1/
H A Das3722_init.h8 #define AS3722_I2C_ADDR 0x80
10 #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
11 #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
12 #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
13 #define AS3722_SDCONTROL_REG 0x4D
15 #define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
16 #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
17 #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
18 #define AS3722_LDCONTROL_REG 0x4E
20 #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
/openbmc/u-boot/board/nvidia/venice2/
H A Das3722_init.h9 #define AS3722_I2C_ADDR 0x80
11 #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
12 #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
13 #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
14 #define AS3722_SDCONTROL_REG 0x4D
16 #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
17 #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
18 #define AS3722_LDCONTROL_REG 0x4E
21 #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
23 #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
[all …]
/openbmc/linux/drivers/net/dsa/
H A Dlantiq_pce.h11 OUT_MAC0 = 0,
55 #define INSTR 0
61 FLAG_ITAG = 0,
89 MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
90 MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
91 MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
92 MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
93 MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
94 MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
95 MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dqspi.h14 u16 mr; /* 0x00 Mode */
16 u16 dlyr; /* 0x04 Delay */
18 u16 wr; /* 0x08 Wrap */
20 u16 ir; /* 0x0C Interrupt */
22 u16 ar; /* 0x10 Address */
24 u16 dr; /* 0x14 Data */
29 #define QSPI_QMR_MSTR (0x8000)
30 #define QSPI_QMR_DOHIE (0x4000)
31 #define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
32 #define QSPI_QMR_BITS_MASK (0xC3FF)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dspi.h24 u32 sscr0; /* SSP Control Register 0 - 0x000 */
25 u32 sscr1; /* SSP Control Register 1 - 0x004 */
26 u32 sssr; /* SSP Status Register - 0x008 */
27 u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
28 u32 ssdr; /* SSP Data Register - 0x010 */
30 u32 ssto; /* SSP Timeout Register - 0x028 */
31 u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
32 u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
33 u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
34 u32 sstss; /* SSP Timeslot Status Register - 0x038 */
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
H A Drt715.h30 #define RT715_AUDIO_FUNCTION_GROUP 0x01
31 #define RT715_MIC_ADC 0x07
32 #define RT715_LINE_ADC 0x08
33 #define RT715_MIX_ADC 0x09
34 #define RT715_DMIC1 0x12
35 #define RT715_DMIC2 0x13
36 #define RT715_MIC1 0x18
37 #define RT715_MIC2 0x19
38 #define RT715_LINE1 0x1a
39 #define RT715_LINE2 0x1b
[all …]
/openbmc/qemu/tests/tcg/arm/
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
/openbmc/u-boot/fs/ext4/
H A Dcrc16.c13 /** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
15 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
16 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
17 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
18 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
19 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
20 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
21 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
22 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
23 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/lib/
H A Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/fs/ubifs/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/include/configs/
H A Dls1088ardb.h12 #define CONFIG_SYS_MMC_ENV_DEV 0
14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15 #define CONFIG_ENV_OFFSET 0x500000
18 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
22 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #define CONFIG_SYS_MMC_ENV_DEV 0
26 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dls2080ardb.h19 #define I2C_MUX_CH_VOL_MONITOR 0xa
20 #define I2C_VOL_MONITOR_ADDR 0x38
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1 0x51
48 #define SPD_EEPROM_ADDRESS2 0x52
49 #define SPD_EEPROM_ADDRESS3 0x53
50 #define SPD_EEPROM_ADDRESS4 0x54
51 #define SPD_EEPROM_ADDRESS5 0x55
52 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
54 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/openbmc/linux/arch/sh/boards/
H A Dboard-magicpanelr2.c33 #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
43 for (i = 0; i < 10; ++i) { in ethernet_reset_finished()
49 return 0; in ethernet_reset_finished()
55 CLRBITS_OUTB(0x10, PORT_PMDR); in reset_ethernet()
60 SETBITS_OUTB(0x10, PORT_PMDR); in reset_ethernet()
65 /* CS2: LAN (0x08000000 - 0x0bffffff) */ in setup_chip_select()
67 __raw_writel(0x36db0400, CS2BCR); in setup_chip_select()
69 __raw_writel(0x000003c0, CS2WCR); in setup_chip_select()
71 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ in setup_chip_select()
73 __raw_writel(0x00000200, CS4BCR); in setup_chip_select()
[all …]
/openbmc/linux/drivers/w1/masters/
H A Dmatrox_w1.c32 #define MATROX_BASE 0x3C00
33 #define MATROX_STATUS 0x1e14
35 #define MATROX_PORT_INDEX_OFFSET 0x00
36 #define MATROX_PORT_DATA_OFFSET 0x0A
38 #define MATROX_GET_CONTROL 0x2A
39 #define MATROX_GET_DATA 0x2B
40 #define MATROX_CURSOR_CTL 0x06
90 bit = 0; in matrox_w1_write_ddc_bit()
96 matrox_w1_write_reg(dev, MATROX_GET_DATA, 0x00); in matrox_w1_write_ddc_bit()
111 matrox_w1_write_reg(dev, MATROX_GET_DATA, 0xFF); in matrox_w1_hw_init()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc866ads.dts19 #size-cells = <0>;
21 PowerPC,866@0 {
23 reg = <0x0>;
26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x800000>;
45 reg = <0xff000100 0x40>;
[all …]

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