Lines Matching +full:0 +full:x3c00

24 	u32 sscr0;	/* SSP Control Register 0 - 0x000 */
25 	u32 sscr1;	/* SSP Control Register 1 - 0x004 */
26 	u32 sssr;	/* SSP Status Register - 0x008 */
27 	u32 ssitr;	/* SSP Interrupt Test Register - 0x00C */
28 	u32 ssdr;	/* SSP Data Register - 0x010 */
30 	u32 ssto;	/* SSP Timeout Register - 0x028 */
31 	u32 sspsp;	/* SSP Programmable Serial Protocol Register - 0x02C */
32 	u32 sstsa;	/* SSP TX Timeslot Active Register - 0x030 */
33 	u32 ssrsa;	/* SSP RX Timeslot Active Register - 0x034 */
34 	u32 sstss;	/* SSP Timeslot Status Register - 0x038 */
38 #define SSP_FLUSH_NUM		0x2000
43 #define SSCR1_RIE	(1 << 0)	/* Receive FIFO Interrupt Enable */
50 #define SSCR1_TFT	0x03c0		/* Transmit FIFO Threshold (mask) */
51 #define SSCR1_RFT	0x3c00		/* Receive FIFO Threshold (mask) */
58 #define SSCR0_DSS		0x0f		/* Data Size Select (mask) */
60 #define SSCR0_FRF		0x30		/* FRame Format (mask) */
61 #define SSCR0_MOTO		(0x0 << 4)	/* Motorola's Serial
63 #define SSCR0_TI		(0x1 << 4)	/* TI's Synchronous
65 #define SSCR0_NATIONAL		(0x2 << 4)	/* National Microwire */