1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2f38f5f4bSMarcel Ziswiler /*
3f38f5f4bSMarcel Ziswiler  * Copyright (c) 2012-2016 Toradex, Inc.
4f38f5f4bSMarcel Ziswiler  */
5f38f5f4bSMarcel Ziswiler 
6f38f5f4bSMarcel Ziswiler /* AS3722-PMIC-specific early init regs */
7f38f5f4bSMarcel Ziswiler 
8f38f5f4bSMarcel Ziswiler #define AS3722_I2C_ADDR		0x80
9f38f5f4bSMarcel Ziswiler 
10f38f5f4bSMarcel Ziswiler #define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
11f38f5f4bSMarcel Ziswiler #define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
12f38f5f4bSMarcel Ziswiler #define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
13f38f5f4bSMarcel Ziswiler #define AS3722_SDCONTROL_REG	0x4D
14f38f5f4bSMarcel Ziswiler 
15f38f5f4bSMarcel Ziswiler #define AS3722_LDO1VOLTAGE_REG	0x11	/* VDD_SDMMC1 */
16f38f5f4bSMarcel Ziswiler #define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
17f38f5f4bSMarcel Ziswiler #define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC3 */
18f38f5f4bSMarcel Ziswiler #define AS3722_LDCONTROL_REG	0x4E
19f38f5f4bSMarcel Ziswiler 
20f38f5f4bSMarcel Ziswiler #define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
21f38f5f4bSMarcel Ziswiler #define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
22f38f5f4bSMarcel Ziswiler 
23f38f5f4bSMarcel Ziswiler #define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
24f38f5f4bSMarcel Ziswiler #define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
25f38f5f4bSMarcel Ziswiler 
26f38f5f4bSMarcel Ziswiler #define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
27f38f5f4bSMarcel Ziswiler #define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
28f38f5f4bSMarcel Ziswiler 
29f38f5f4bSMarcel Ziswiler #define AS3722_LDO1CONTROL_DATA	(0x0200 | AS3722_LDCONTROL_REG)
30f38f5f4bSMarcel Ziswiler #define AS3722_LDO1VOLTAGE_DATA	(0x7F00 | AS3722_LDO1VOLTAGE_REG)
31f38f5f4bSMarcel Ziswiler 
32f38f5f4bSMarcel Ziswiler #define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
33f38f5f4bSMarcel Ziswiler #define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
34f38f5f4bSMarcel Ziswiler 
35f38f5f4bSMarcel Ziswiler #define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
36f38f5f4bSMarcel Ziswiler #define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
37f38f5f4bSMarcel Ziswiler 
38f38f5f4bSMarcel Ziswiler #define I2C_SEND_2_BYTES	0x0A02
39f38f5f4bSMarcel Ziswiler 
40f38f5f4bSMarcel Ziswiler void pmic_enable_cpu_vdd(void);
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