Lines Matching +full:0 +full:x3c00

8 #define AS3722_I2C_ADDR		0x80
10 #define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
11 #define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
12 #define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
13 #define AS3722_SDCONTROL_REG	0x4D
15 #define AS3722_LDO1VOLTAGE_REG	0x11	/* VDD_SDMMC1 */
16 #define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
17 #define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC3 */
18 #define AS3722_LDCONTROL_REG	0x4E
20 #define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
21 #define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
23 #define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
24 #define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
26 #define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
27 #define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
29 #define AS3722_LDO1CONTROL_DATA	(0x0200 | AS3722_LDCONTROL_REG)
30 #define AS3722_LDO1VOLTAGE_DATA	(0x7F00 | AS3722_LDO1VOLTAGE_REG)
32 #define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
33 #define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
35 #define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
36 #define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
38 #define I2C_SEND_2_BYTES	0x0A02