1a8ec9e04SChunfeng Yun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2a8ec9e04SChunfeng Yun# Copyright (c) 2020 MediaTek 3a8ec9e04SChunfeng Yun%YAML 1.2 4a8ec9e04SChunfeng Yun--- 5a8ec9e04SChunfeng Yun$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml# 6a8ec9e04SChunfeng Yun$schema: http://devicetree.org/meta-schemas/core.yaml# 7a8ec9e04SChunfeng Yun 8*dd3cb467SAndrew Lunntitle: MediaTek XS-PHY Controller 9a8ec9e04SChunfeng Yun 10a8ec9e04SChunfeng Yunmaintainers: 11a8ec9e04SChunfeng Yun - Chunfeng Yun <chunfeng.yun@mediatek.com> 12a8ec9e04SChunfeng Yun 13a8ec9e04SChunfeng Yundescription: | 14a8ec9e04SChunfeng Yun The XS-PHY controller supports physical layer functionality for USB3.1 15a8ec9e04SChunfeng Yun GEN2 controller on MediaTek SoCs. 16a8ec9e04SChunfeng Yun 17a8ec9e04SChunfeng Yun Banks layout of xsphy 18a8ec9e04SChunfeng Yun ---------------------------------- 19a8ec9e04SChunfeng Yun port offset bank 20a8ec9e04SChunfeng Yun u2 port0 0x0000 MISC 21a8ec9e04SChunfeng Yun 0x0100 FMREG 22a8ec9e04SChunfeng Yun 0x0300 U2PHY_COM 23a8ec9e04SChunfeng Yun u2 port1 0x1000 MISC 24a8ec9e04SChunfeng Yun 0x1100 FMREG 25a8ec9e04SChunfeng Yun 0x1300 U2PHY_COM 26a8ec9e04SChunfeng Yun u2 port2 0x2000 MISC 27a8ec9e04SChunfeng Yun ... 28a8ec9e04SChunfeng Yun u31 common 0x3000 DIG_GLB 29a8ec9e04SChunfeng Yun 0x3100 PHYA_GLB 30a8ec9e04SChunfeng Yun u31 port0 0x3400 DIG_LN_TOP 31a8ec9e04SChunfeng Yun 0x3500 DIG_LN_TX0 32a8ec9e04SChunfeng Yun 0x3600 DIG_LN_RX0 33a8ec9e04SChunfeng Yun 0x3700 DIG_LN_DAIF 34a8ec9e04SChunfeng Yun 0x3800 PHYA_LN 35a8ec9e04SChunfeng Yun u31 port1 0x3a00 DIG_LN_TOP 36a8ec9e04SChunfeng Yun 0x3b00 DIG_LN_TX0 37a8ec9e04SChunfeng Yun 0x3c00 DIG_LN_RX0 38a8ec9e04SChunfeng Yun 0x3d00 DIG_LN_DAIF 39a8ec9e04SChunfeng Yun 0x3e00 PHYA_LN 40a8ec9e04SChunfeng Yun ... 41a8ec9e04SChunfeng Yun DIG_GLB & PHYA_GLB are shared by U31 ports. 42a8ec9e04SChunfeng Yun 43a8ec9e04SChunfeng Yunproperties: 44a8ec9e04SChunfeng Yun $nodename: 45a8ec9e04SChunfeng Yun pattern: "^xs-phy@[0-9a-f]+$" 46a8ec9e04SChunfeng Yun 47a8ec9e04SChunfeng Yun compatible: 48a8ec9e04SChunfeng Yun items: 49a8ec9e04SChunfeng Yun - enum: 50a8ec9e04SChunfeng Yun - mediatek,mt3611-xsphy 51a8ec9e04SChunfeng Yun - mediatek,mt3612-xsphy 52a8ec9e04SChunfeng Yun - const: mediatek,xsphy 53a8ec9e04SChunfeng Yun 54a8ec9e04SChunfeng Yun reg: 55a8ec9e04SChunfeng Yun description: 56a8ec9e04SChunfeng Yun Register shared by multiple U3 ports, exclude port's private register, 57a8ec9e04SChunfeng Yun if only U2 ports provided, shouldn't use the property. 58a8ec9e04SChunfeng Yun maxItems: 1 59a8ec9e04SChunfeng Yun 60a8ec9e04SChunfeng Yun "#address-cells": 61a8ec9e04SChunfeng Yun enum: [1, 2] 62a8ec9e04SChunfeng Yun 63a8ec9e04SChunfeng Yun "#size-cells": 64a8ec9e04SChunfeng Yun enum: [1, 2] 65a8ec9e04SChunfeng Yun 66a8ec9e04SChunfeng Yun ranges: true 67a8ec9e04SChunfeng Yun 68a8ec9e04SChunfeng Yun mediatek,src-ref-clk-mhz: 69a8ec9e04SChunfeng Yun description: 70a8ec9e04SChunfeng Yun Frequency of reference clock for slew rate calibrate 71a8ec9e04SChunfeng Yun default: 26 72a8ec9e04SChunfeng Yun 73a8ec9e04SChunfeng Yun mediatek,src-coef: 74a8ec9e04SChunfeng Yun description: 75a8ec9e04SChunfeng Yun Coefficient for slew rate calibrate, depends on SoC process 76a8ec9e04SChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 77a8ec9e04SChunfeng Yun default: 17 78a8ec9e04SChunfeng Yun 79a8ec9e04SChunfeng Yun# Required child node: 80a8ec9e04SChunfeng YunpatternProperties: 81a8ec9e04SChunfeng Yun "^usb-phy@[0-9a-f]+$": 82a8ec9e04SChunfeng Yun type: object 83a8ec9e04SChunfeng Yun description: 84a8ec9e04SChunfeng Yun A sub-node is required for each port the controller provides. 85a8ec9e04SChunfeng Yun Address range information including the usual 'reg' property 86a8ec9e04SChunfeng Yun is used inside these nodes to describe the controller's topology. 87a8ec9e04SChunfeng Yun 88a8ec9e04SChunfeng Yun properties: 89a8ec9e04SChunfeng Yun reg: 90a8ec9e04SChunfeng Yun maxItems: 1 91a8ec9e04SChunfeng Yun 92a8ec9e04SChunfeng Yun clocks: 93a8ec9e04SChunfeng Yun items: 94a8ec9e04SChunfeng Yun - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 95a8ec9e04SChunfeng Yun 96a8ec9e04SChunfeng Yun clock-names: 97a8ec9e04SChunfeng Yun items: 98a8ec9e04SChunfeng Yun - const: ref 99a8ec9e04SChunfeng Yun 100a8ec9e04SChunfeng Yun "#phy-cells": 101a8ec9e04SChunfeng Yun const: 1 102a8ec9e04SChunfeng Yun description: | 103a8ec9e04SChunfeng Yun The cells contain the following arguments. 104a8ec9e04SChunfeng Yun 105a8ec9e04SChunfeng Yun - description: The PHY type 106a8ec9e04SChunfeng Yun enum: 107a8ec9e04SChunfeng Yun - PHY_TYPE_USB2 108a8ec9e04SChunfeng Yun - PHY_TYPE_USB3 109a8ec9e04SChunfeng Yun 110a8ec9e04SChunfeng Yun # The following optional vendor properties are only for debug or HQA test 111a8ec9e04SChunfeng Yun mediatek,eye-src: 112a8ec9e04SChunfeng Yun description: 113a8ec9e04SChunfeng Yun The value of slew rate calibrate (U2 phy) 114a8ec9e04SChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 115a8ec9e04SChunfeng Yun minimum: 1 116a8ec9e04SChunfeng Yun maximum: 7 117a8ec9e04SChunfeng Yun 118a8ec9e04SChunfeng Yun mediatek,eye-vrt: 119a8ec9e04SChunfeng Yun description: 120a8ec9e04SChunfeng Yun The selection of VRT reference voltage (U2 phy) 121a8ec9e04SChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 122a8ec9e04SChunfeng Yun minimum: 1 123a8ec9e04SChunfeng Yun maximum: 7 124a8ec9e04SChunfeng Yun 125a8ec9e04SChunfeng Yun mediatek,eye-term: 126a8ec9e04SChunfeng Yun description: 127a8ec9e04SChunfeng Yun The selection of HS_TX TERM reference voltage (U2 phy) 128a8ec9e04SChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 129a8ec9e04SChunfeng Yun minimum: 1 130a8ec9e04SChunfeng Yun maximum: 7 131a8ec9e04SChunfeng Yun 132a8ec9e04SChunfeng Yun mediatek,efuse-intr: 133a8ec9e04SChunfeng Yun description: 134a8ec9e04SChunfeng Yun The selection of Internal Resistor (U2/U3 phy) 135a8ec9e04SChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 136a8ec9e04SChunfeng Yun minimum: 1 137a8ec9e04SChunfeng Yun maximum: 63 138a8ec9e04SChunfeng Yun 139a8ec9e04SChunfeng Yun mediatek,efuse-tx-imp: 140a8ec9e04SChunfeng Yun description: 141a8ec9e04SChunfeng Yun The selection of TX Impedance (U3 phy) 142a8ec9e04SChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 143a8ec9e04SChunfeng Yun minimum: 1 144a8ec9e04SChunfeng Yun maximum: 31 145a8ec9e04SChunfeng Yun 146a8ec9e04SChunfeng Yun mediatek,efuse-rx-imp: 147a8ec9e04SChunfeng Yun description: 148a8ec9e04SChunfeng Yun The selection of RX Impedance (U3 phy) 149a8ec9e04SChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 150a8ec9e04SChunfeng Yun minimum: 1 151a8ec9e04SChunfeng Yun maximum: 31 152a8ec9e04SChunfeng Yun 153a8ec9e04SChunfeng Yun required: 154a8ec9e04SChunfeng Yun - reg 155a8ec9e04SChunfeng Yun - clocks 156a8ec9e04SChunfeng Yun - clock-names 157a8ec9e04SChunfeng Yun - "#phy-cells" 158a8ec9e04SChunfeng Yun 159a8ec9e04SChunfeng Yun additionalProperties: false 160a8ec9e04SChunfeng Yun 161a8ec9e04SChunfeng Yunrequired: 162a8ec9e04SChunfeng Yun - compatible 163a8ec9e04SChunfeng Yun - "#address-cells" 164a8ec9e04SChunfeng Yun - "#size-cells" 165a8ec9e04SChunfeng Yun - ranges 166a8ec9e04SChunfeng Yun 167a8ec9e04SChunfeng YunadditionalProperties: false 168a8ec9e04SChunfeng Yun 169a8ec9e04SChunfeng Yunexamples: 170a8ec9e04SChunfeng Yun - | 171a8ec9e04SChunfeng Yun #include <dt-bindings/phy/phy.h> 172a8ec9e04SChunfeng Yun 173a8ec9e04SChunfeng Yun u3phy: xs-phy@11c40000 { 174a8ec9e04SChunfeng Yun compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy"; 175a8ec9e04SChunfeng Yun reg = <0x11c43000 0x0200>; 176a8ec9e04SChunfeng Yun mediatek,src-ref-clk-mhz = <26>; 177a8ec9e04SChunfeng Yun mediatek,src-coef = <17>; 178a8ec9e04SChunfeng Yun #address-cells = <1>; 179a8ec9e04SChunfeng Yun #size-cells = <1>; 180a8ec9e04SChunfeng Yun ranges; 181a8ec9e04SChunfeng Yun 182a8ec9e04SChunfeng Yun u2port0: usb-phy@11c40000 { 183a8ec9e04SChunfeng Yun reg = <0x11c40000 0x0400>; 184a8ec9e04SChunfeng Yun clocks = <&clk48m>; 185a8ec9e04SChunfeng Yun clock-names = "ref"; 186a8ec9e04SChunfeng Yun mediatek,eye-src = <4>; 187a8ec9e04SChunfeng Yun #phy-cells = <1>; 188a8ec9e04SChunfeng Yun }; 189a8ec9e04SChunfeng Yun 190a8ec9e04SChunfeng Yun u3port0: usb-phy@11c43000 { 191a8ec9e04SChunfeng Yun reg = <0x11c43400 0x0500>; 192a8ec9e04SChunfeng Yun clocks = <&clk26m>; 193a8ec9e04SChunfeng Yun clock-names = "ref"; 194a8ec9e04SChunfeng Yun mediatek,efuse-intr = <28>; 195a8ec9e04SChunfeng Yun #phy-cells = <1>; 196a8ec9e04SChunfeng Yun }; 197a8ec9e04SChunfeng Yun }; 198a8ec9e04SChunfeng Yun 199a8ec9e04SChunfeng Yun... 200