Lines Matching +full:0 +full:x3c00
19 #define I2C_MUX_CH_VOL_MONITOR 0xa
20 #define I2C_VOL_MONITOR_ADDR 0x38
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1 0x51
48 #define SPD_EEPROM_ADDRESS2 0x52
49 #define SPD_EEPROM_ADDRESS3 0x53
50 #define SPD_EEPROM_ADDRESS4 0x54
51 #define SPD_EEPROM_ADDRESS5 0x55
52 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
54 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
72 #define CONFIG_SYS_MMC_ENV_DEV 0
74 #define CONFIG_ENV_SIZE 0x2000
75 #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
78 #define CONFIG_ENV_SECT_SIZE 0x40000
83 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
98 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
99 FTIM0_NOR_TEADC(0x5) | \
100 FTIM0_NOR_TEAHC(0x5))
101 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
102 FTIM1_NOR_TRAD_NOR(0x1a) |\
103 FTIM1_NOR_TSEQRAD_NOR(0x13))
104 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
105 FTIM2_NOR_TCH(0x4) | \
106 FTIM2_NOR_TWPH(0x0E) | \
107 FTIM2_NOR_TWP(0x1c))
108 #define CONFIG_SYS_NOR_FTIM3 0x04000000
109 #define CONFIG_SYS_IFC_CCR 0x01000000
122 CONFIG_SYS_FLASH_BASE + 0x40000000}
129 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
147 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
148 FTIM0_NAND_TWP(0x30) | \
149 FTIM0_NAND_TWCHT(0x0e) | \
150 FTIM0_NAND_TWH(0x14))
151 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
152 FTIM1_NAND_TWBE(0xab) | \
153 FTIM1_NAND_TRR(0x1c) | \
154 FTIM1_NAND_TRP(0x30))
155 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
156 FTIM2_NAND_TREH(0x14) | \
157 FTIM2_NAND_TWHRE(0x3c))
158 #define CONFIG_SYS_NAND_FTIM3 0x0
166 #define QIXIS_LBMAP_SWITCH 0x06
167 #define QIXIS_LBMAP_MASK 0x0f
168 #define QIXIS_LBMAP_SHIFT 0
169 #define QIXIS_LBMAP_DFLTBANK 0x00
170 #define QIXIS_LBMAP_ALTBANK 0x04
171 #define QIXIS_LBMAP_NAND 0x09
172 #define QIXIS_RST_CTL_RESET 0x31
173 #define QIXIS_RST_CTL_RESET_EN 0x30
174 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
175 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
176 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
177 #define QIXIS_RCW_SRC_NAND 0x119
178 #define QIXIS_RST_FORCE_MEM 0x01
180 #define CONFIG_SYS_CSPR3_EXT (0x0)
193 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
194 FTIM0_GPCM_TEADC(0x0e) | \
195 FTIM0_GPCM_TEAHC(0x0e))
196 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
197 FTIM1_GPCM_TRAD(0x3f))
198 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
199 FTIM2_GPCM_TCH(0xf) | \
200 FTIM2_GPCM_TWP(0x3E))
201 #define CONFIG_SYS_CS3_FTIM3 0x0
224 #define CONFIG_ENV_SECT_SIZE 0x20000
225 #define CONFIG_ENV_SIZE 0x2000
227 #define CONFIG_SPL_PAD_TO 0x80000
250 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
251 #define CONFIG_ENV_SECT_SIZE 0x20000
252 #define CONFIG_ENV_SIZE 0x2000
258 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
264 #define QIXIS_QMAP_MASK 0x07
266 #define QIXIS_LBMAP_DFLTBANK 0x00
267 #define QIXIS_LBMAP_QSPI 0x00
268 #define QIXIS_RCW_SRC_QSPI 0x62
269 #define QIXIS_LBMAP_ALTBANK 0x20
270 #define QIXIS_RST_CTL_RESET 0x31
271 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
272 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
273 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
274 #define QIXIS_LBMAP_MASK 0x0f
275 #define QIXIS_RST_CTL_RESET_EN 0x30
282 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
284 #define I2C_MUX_PCA_ADDR 0x75
285 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
288 #define I2C_MUX_CH_DEFAULT 0x8
305 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
308 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
314 #define CONFIG_SYS_EEPROM_BUS_NUM 0
315 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
332 func(USB, usb, 0) \
333 func(MMC, mmc, 0) \
334 func(SCSI, scsi, 0) \
341 "esbc_validate 0x20700000 && " \
342 "esbc_validate 0x20740000;" \
343 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
345 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
346 "mmc read 0x80100000 0x7000 0x800;" \
348 "mmc read 0x80700000 0x3800 0x10 && " \
349 "mmc read 0x80740000 0x3A00 0x10 && " \
350 "esbc_validate 0x80700000 && " \
351 "esbc_validate 0x80740000 ;" \
352 "fsl_mc start mc 0x80000000 0x80100000\0"
355 "esbc_validate 0x580700000 && " \
356 "esbc_validate 0x580740000; " \
357 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
362 "esbc_validate 0x20700000 && " \
363 "esbc_validate 0x20740000;" \
364 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
367 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
368 "mmc read 0x80100000 0x7000 0x800;" \
370 "mmc read 0x80700000 0x3800 0x10 && " \
371 "mmc read 0x80740000 0x3A00 0x10 && " \
372 "esbc_validate 0x80700000 && " \
373 "esbc_validate 0x80740000 ;" \
374 "fsl_mc start mc 0x80000000 0x80100000\0" \
375 "mcmemsize=0x70000000\0"
379 "esbc_validate 0x580700000 && " \
380 "esbc_validate 0x580740000; " \
381 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
389 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
390 "ramdisk_addr=0x800000\0" \
391 "ramdisk_size=0x2000000\0" \
392 "fdt_high=0xa0000000\0" \
393 "initrd_high=0xffffffffffffffff\0" \
394 "fdt_addr=0x64f00000\0" \
395 "kernel_addr=0x581000000\0" \
396 "kernel_start=0x1000000\0" \
397 "kernelheader_start=0x800000\0" \
398 "scriptaddr=0x80000000\0" \
399 "scripthdraddr=0x80080000\0" \
400 "fdtheader_addr_r=0x80100000\0" \
401 "kernelheader_addr_r=0x80200000\0" \
402 "kernelheader_addr=0x580800000\0" \
403 "kernel_addr_r=0x81000000\0" \
404 "kernelheader_size=0x40000\0" \
405 "fdt_addr_r=0x90000000\0" \
406 "load_addr=0xa0000000\0" \
407 "kernel_size=0x2800000\0" \
408 "kernel_addr_sd=0x8000\0" \
409 "kernel_size_sd=0x14000\0" \
410 "console=ttyAMA0,38400n8\0" \
411 "mcmemsize=0x70000000\0" \
415 "bootm $load_addr#$board\0" \
418 "boot_scripts=ls2088ardb_boot.scr\0" \
419 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
429 "done\0" \
437 "source ${scriptaddr}\0" \
443 " bootm $load_addr#$board\0" \
449 "bootm $load_addr#$board\0"
452 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
453 "ramdisk_addr=0x800000\0" \
454 "ramdisk_size=0x2000000\0" \
455 "fdt_high=0xa0000000\0" \
456 "initrd_high=0xffffffffffffffff\0" \
457 "fdt_addr=0x64f00000\0" \
458 "kernel_addr=0x581000000\0" \
459 "kernel_start=0x1000000\0" \
460 "kernelheader_start=0x800000\0" \
461 "scriptaddr=0x80000000\0" \
462 "scripthdraddr=0x80080000\0" \
463 "fdtheader_addr_r=0x80100000\0" \
464 "kernelheader_addr_r=0x80200000\0" \
465 "kernelheader_addr=0x580800000\0" \
466 "kernel_addr_r=0x81000000\0" \
467 "kernelheader_size=0x40000\0" \
468 "fdt_addr_r=0x90000000\0" \
469 "load_addr=0xa0000000\0" \
470 "kernel_size=0x2800000\0" \
471 "kernel_addr_sd=0x8000\0" \
472 "kernel_size_sd=0x14000\0" \
473 "console=ttyAMA0,38400n8\0" \
474 "mcmemsize=0x70000000\0" \
478 "bootm $load_addr#$board\0" \
481 "boot_scripts=ls2088ardb_boot.scr\0" \
482 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
492 "done\0" \
500 "source ${scriptaddr}\0" \
506 " bootm $load_addr#$board\0" \
512 "bootm $load_addr#$board\0"
518 "&& esbc_validate 0x20780000; " \
520 "fsl_mc lazyapply dpl 0x20d00000; " \
527 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
530 "&& mmc read 0x88000000 0x6800 0x800 " \
531 "&& fsl_mc lazyapply dpl 0x88000000; " \
538 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
539 "&& fsl_mc lazyapply dpl 0x580d00000;" \
548 "&& esbc_validate 0x20780000; " \
550 "fsl_mc lazyapply dpl 0x20d00000; " \
557 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
560 "&& mmc read 0x88000000 0x6800 0x800 " \
561 "&& fsl_mc lazyapply dpl 0x88000000; " \
568 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
569 "&& fsl_mc lazyapply dpl 0x580d00000;" \
580 #define CONFIG_CORTINA_FW_ADDR 0x20980000
582 #define CONFIG_CORTINA_FW_ADDR 0x580980000
584 #define CONFIG_CORTINA_FW_LENGTH 0x40000
586 #define CORTINA_PHY_ADDR1 0x10
587 #define CORTINA_PHY_ADDR2 0x11
588 #define CORTINA_PHY_ADDR3 0x12
589 #define CORTINA_PHY_ADDR4 0x13
590 #define AQ_PHY_ADDR1 0x00
591 #define AQ_PHY_ADDR2 0x01
592 #define AQ_PHY_ADDR3 0x02
593 #define AQ_PHY_ADDR4 0x03
594 #define AQR405_IRQ_MASK 0x36