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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-karo-tx25.dts17 reg_fec_phy: regulator-0 {
22 gpio = <&gpio4 9 0>;
28 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
35 MX25_PAD_UART1_TXD__UART1_TXD 0x00000020
36 MX25_PAD_UART1_RXD__UART1_RXD 0x000000a0
37 MX25_PAD_UART1_CTS__UART1_CTS 0x00000060
38 MX25_PAD_UART1_RTS__UART1_RTS 0x000000e0
44 MX25_PAD_D11__GPIO_4_9 0x00000021 /* FEC PHY power on pin */
45 MX25_PAD_D13__GPIO_4_7 0x000000a1 /* FEC reset */
46 MX25_PAD_FEC_MDC__FEC_MDC 0x00000060
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8dxl-evk.dts27 reg = <0x00000000 0x80000000 0 0x40000000>;
39 * reg = <0 0x96000000 0 0x2000000>;
48 size = <0 0x14000000>;
49 alloc-ranges = <0 0x98000000 0 0x14000000>;
54 mux3_en: regulator-0 {
78 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
119 pinctrl-0 = <&pinctrl_eqos>;
129 #size-cells = <0>;
131 ethphy0: ethernet-phy@0 {
133 reg = <0>;
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dstb0899_reg.h14 #define STB0899_DEV_ID 0xf000
15 #define STB0899_CHIP_ID (0x0f << 4)
18 #define STB0899_CHIP_REL (0x0f << 0)
19 #define STB0899_OFFST_CHIP_REL 0
22 #define STB0899_DEMOD 0xf40e
23 #define STB0899_MODECOEFF (0x01 << 0)
24 #define STB0899_OFFST_MODECOEFF 0
27 #define STB0899_RCOMPC 0xf410
28 #define STB0899_AGC1CN 0xf412
29 #define STB0899_AGC1REF 0xf413
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dhsw_clear_kernel.c9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x00000160,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
H A Divb_clear_kernel.c9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x0000002c,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_matrix.h12 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
14 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
16 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
18 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
63 u32 mrcr; /* 0x100 Master Remap Control */
66 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
67 u32 womr; /* 0x1E4 Write Protect Mode */
68 u32 wpsr; /* 0x1E8 Write Protect Status */
88 #define AT91_MATRIX_CSA_DBPUC 0x00000100
89 #define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl176e.h5 #define NV176E_SET_OBJECT (0x00000000)
6 #define NV176E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060)
7 #define NV176E_SEMAPHORE_OFFSET (0x00000064)
8 #define NV176E_SEMAPHORE_ACQUIRE (0x00000068)
9 #define NV176E_SEMAPHORE_RELEASE (0x0000006c)
H A Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
H A Dcl826f.h26 #define NV826F_SEMAPHOREA (0x00000010)
27 #define NV826F_SEMAPHOREA_OFFSET_UPPER 7:0
28 #define NV826F_SEMAPHOREB (0x00000014)
30 #define NV826F_SEMAPHOREC (0x00000018)
31 #define NV826F_SEMAPHOREC_PAYLOAD 31:0
32 #define NV826F_SEMAPHORED (0x0000001C)
33 #define NV826F_SEMAPHORED_OPERATION 2:0
34 #define NV826F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001
35 #define NV826F_SEMAPHORED_OPERATION_RELEASE 0x00000002
36 #define NV826F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004
[all …]
/openbmc/linux/drivers/net/ethernet/pasemi/
H A Dpasemi_mac.h110 PAS_MAC_CFG_PCFG = 0x80,
111 PAS_MAC_CFG_MACCFG = 0x84,
112 PAS_MAC_CFG_ADR0 = 0x8c,
113 PAS_MAC_CFG_ADR1 = 0x90,
114 PAS_MAC_CFG_TXP = 0x98,
115 PAS_MAC_CFG_RMON = 0x100,
116 PAS_MAC_IPC_CHNL = 0x208,
120 #define PAS_MAC_CFG_PCFG_PE 0x80000000
121 #define PAS_MAC_CFG_PCFG_CE 0x40000000
122 #define PAS_MAC_CFG_PCFG_BU 0x20000000
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm54xxacr.h12 #define CACR_DEC 0x80000000 /* Enable data cache */
13 #define CACR_DWP 0x40000000 /* Data write protection */
14 #define CACR_DESB 0x20000000 /* Enable data store buffer */
15 #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
16 #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
18 #define CACR_DDCM_CP 0x02000000 /* Copyback cache */
19 #define CACR_DDCM_P 0x04000000 /* No cache, precise */
20 #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
21 #define CACR_DCINVA 0x01000000 /* Invalidate data cache */
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/openbmc/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.xml.h57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
/openbmc/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mtl.h12 #define SXGBE_MTL_OPMODE_ESTMASK 0x3
13 #define SXGBE_MTL_OPMODE_RAAMASK 0x1
14 #define SXGBE_MTL_FCMASK 0x7
20 #define SXGBE_MTL_ENABLE_FC 0x80
22 #define ETS_WRR 0xFFFFFF9F
23 #define ETS_RST 0xFFFFFF9F
24 #define ETS_WFQ 0x00000020
25 #define ETS_DWRR 0x00000040
26 #define RAA_SP 0xFFFFFFFB
27 #define RAA_WSP 0x00000004
[all …]
/openbmc/u-boot/include/
H A Dlcdvideo.h11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
/openbmc/linux/sound/pci/vx222/
H A Dvx222.h32 #define VX2_AKM_LEVEL_MAX 0x93
38 #define VX_RESET_DMA_REGISTER_OFFSET 0x00000008
41 #define VX_INTCSR_VALUE 0x00000001
42 #define VX_PCI_INTERRUPT_MASK 0x00000040
44 /* Constants used to access the CDSP register (0x20). */
45 #define VX_CDSP_TEST1_MASK 0x00000080
46 #define VX_CDSP_TOR1_MASK 0x00000040
47 #define VX_CDSP_TOR2_MASK 0x00000020
48 #define VX_CDSP_RESERVED0_0_MASK 0x00000010
49 #define VX_CDSP_CODEC_RESET_MASK 0x00000008
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dfsl_lbc.h22 #define BR_BA 0xFFFF8000
24 #define BR_PS 0x00001800
26 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
27 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
28 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
29 #define BR_DECC 0x00000600
31 #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
32 #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
33 #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
34 #define BR_WP 0x00000100
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_lbc.h18 #define BR0 0x5000 /* Register offset to immr */
19 #define BR1 0x5008
20 #define BR2 0x5010
21 #define BR3 0x5018
22 #define BR4 0x5020
23 #define BR5 0x5028
24 #define BR6 0x5030
25 #define BR7 0x5038
27 #define BR_BA 0xFFFF8000
29 #define BR_XBA 0x00006000
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-regs.h13 #define UMC_CPURST 0x00000700
14 #define UMC_IDSRST 0x0000070C
15 #define UMC_IXMRST 0x00000714
16 #define UMC_HDMRST 0x00000718
17 #define UMC_MDMRST 0x0000071C
18 #define UMC_HDDRST 0x00000720
19 #define UMC_MDDRST 0x00000724
20 #define UMC_SIORST 0x00000728
21 #define UMC_GIORST 0x0000072C
22 #define UMC_HD2RST 0x00000734
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/openbmc/linux/arch/arm/nwfpe/
H A Dfpsr.h32 #define MASK_SYSID 0xff000000
33 #define BIT_HARDWARE 0x80000000
34 #define FP_EMULATOR 0x01000000 /* System ID for emulator */
35 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
40 #define MASK_TRAP_ENABLE 0x00ff0000
41 #define MASK_TRAP_ENABLE_STRICT 0x001f0000
42 #define BIT_IXE 0x00100000 /* inexact exception enable */
43 #define BIT_UFE 0x00080000 /* underflow exception enable */
44 #define BIT_OFE 0x00040000 /* overflow exception enable */
45 #define BIT_DZE 0x00020000 /* divide by zero exception enable */
[all …]
/openbmc/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/thm/
H A Dthm_10_0_default.h26 #define mmTHM_TCON_CUR_TMP_DEFAULT 0x00000000
27 #define mmTHM_TCON_HTC_DEFAULT 0x00004000
28 #define mmTHM_TCON_THERM_TRIP_DEFAULT 0x00000001
29 #define mmTHM_CTF_DELAY_DEFAULT 0x00000000
30 #define mmTHM_GPIO_PROCHOT_CTRL_DEFAULT 0x000000f9
31 #define mmTHM_THERMAL_INT_ENA_DEFAULT 0x00000000
32 #define mmTHM_THERMAL_INT_CTRL_DEFAULT 0x0fff0078
33 #define mmTHM_THERMAL_INT_STATUS_DEFAULT 0x00000000
34 #define mmTHM_TMON0_RDIL0_DATA_DEFAULT 0x00000000
35 #define mmTHM_TMON0_RDIL1_DATA_DEFAULT 0x00000000
[all …]
/openbmc/u-boot/include/linux/mtd/
H A Dst_smi.h10 /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */
11 /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */
21 #define BANK0 0
35 #define BANK_EN 0x0000000F /* enables all banks */
36 #define DSEL_TIME 0x00000060 /* Deselect time */
37 #define PRESCAL5 0x00000500 /* AHB_CK prescaling value */
38 #define PRESCALA 0x00000A00 /* AHB_CK prescaling value */
39 #define PRESCAL3 0x00000300 /* AHB_CK prescaling value */
40 #define PRESCAL4 0x00000400 /* AHB_CK prescaling value */
41 #define SW_MODE 0x10000000 /* enables SW Mode */
[all …]

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