Lines Matching +full:0 +full:x00000060
57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
88 #define HDMI_ACR_PKT_CTRL_CONT 0x00000001
89 #define HDMI_ACR_PKT_CTRL_SEND 0x00000002
90 #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030
96 #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100
97 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000
103 #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000
105 #define REG_HDMI_VBI_PKT_CTRL 0x00000028
106 #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010
107 #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020
108 #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100
109 #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200
110 #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000
111 #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000
113 #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c
114 #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001
115 #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002
116 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010
117 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020
118 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
119 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
121 #define REG_HDMI_INFOFRAME_CTRL1 0x00000030
122 #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
123 #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
128 #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
134 #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
140 #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
147 #define REG_HDMI_GEN_PKT_CTRL 0x00000034
148 #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
149 #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
150 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c
156 #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010
157 #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020
158 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000
164 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000
171 #define REG_HDMI_GC 0x00000040
172 #define HDMI_GC_MUTE 0x00000001
174 #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044
175 #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001
176 #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002
178 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } in REG_HDMI_AVI_INFO()
180 #define REG_HDMI_GENERIC0_HDR 0x00000084
182 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } in REG_HDMI_GENERIC0()
184 #define REG_HDMI_GENERIC1_HDR 0x000000a4
186 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } in REG_HDMI_GENERIC1()
188 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR()
190 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR_0()
191 #define HDMI_ACR_0_CTS__MASK 0xfffff000
198 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } in REG_HDMI_ACR_1()
199 #define HDMI_ACR_1_N__MASK 0xffffffff
200 #define HDMI_ACR_1_N__SHIFT 0
206 #define REG_HDMI_AUDIO_INFO0 0x000000e4
207 #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff
208 #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0
213 #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700
220 #define REG_HDMI_AUDIO_INFO1 0x000000e8
221 #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff
222 #define HDMI_AUDIO_INFO1_CA__SHIFT 0
227 #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800
233 #define HDMI_AUDIO_INFO1_DM_INH 0x00008000
235 #define REG_HDMI_HDCP_CTRL 0x00000110
236 #define HDMI_HDCP_CTRL_ENABLE 0x00000001
237 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100
239 #define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114
240 #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004
242 #define REG_HDMI_HDCP_INT_CTRL 0x00000118
243 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001
244 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002
245 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004
246 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010
247 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020
248 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040
249 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080
250 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100
251 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200
252 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400
253 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000
254 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000
255 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000
257 #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c
258 #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100
259 #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200
260 #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000
261 #define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000
262 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000
269 #define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120
270 #define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001
272 #define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124
273 #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001
275 #define REG_HDMI_HDCP_DDC_STATUS 0x00000128
276 #define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010
277 #define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400
278 #define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000
279 #define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000
280 #define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000
281 #define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000
282 #define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000
284 #define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c
286 #define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c
288 #define REG_HDMI_HDCP_RESET 0x00000130
289 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
291 #define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134
293 #define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138
295 #define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c
297 #define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140
299 #define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144
301 #define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148
303 #define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c
305 #define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150
307 #define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154
309 #define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158
311 #define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c
313 #define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160
315 #define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164
317 #define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168
319 #define REG_HDMI_VENSPEC_INFO0 0x0000016c
321 #define REG_HDMI_VENSPEC_INFO1 0x00000170
323 #define REG_HDMI_VENSPEC_INFO2 0x00000174
325 #define REG_HDMI_VENSPEC_INFO3 0x00000178
327 #define REG_HDMI_VENSPEC_INFO4 0x0000017c
329 #define REG_HDMI_VENSPEC_INFO5 0x00000180
331 #define REG_HDMI_VENSPEC_INFO6 0x00000184
333 #define REG_HDMI_AUDIO_CFG 0x000001d0
334 #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
335 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
342 #define REG_HDMI_USEC_REFTIMER 0x00000208
344 #define REG_HDMI_DDC_CTRL 0x0000020c
345 #define HDMI_DDC_CTRL_GO 0x00000001
346 #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002
347 #define HDMI_DDC_CTRL_SEND_RESET 0x00000004
348 #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008
349 #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000
356 #define REG_HDMI_DDC_ARBITRATION 0x00000210
357 #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
359 #define REG_HDMI_DDC_INT_CTRL 0x00000214
360 #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
361 #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
362 #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004
364 #define REG_HDMI_DDC_SW_STATUS 0x00000218
365 #define HDMI_DDC_SW_STATUS_NACK0 0x00001000
366 #define HDMI_DDC_SW_STATUS_NACK1 0x00002000
367 #define HDMI_DDC_SW_STATUS_NACK2 0x00004000
368 #define HDMI_DDC_SW_STATUS_NACK3 0x00008000
370 #define REG_HDMI_DDC_HW_STATUS 0x0000021c
371 #define HDMI_DDC_HW_STATUS_DONE 0x00000008
373 #define REG_HDMI_DDC_SPEED 0x00000220
374 #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003
375 #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0
380 #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000
387 #define REG_HDMI_DDC_SETUP 0x00000224
388 #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000
395 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION()
397 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION_REG()
398 #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001
399 #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0
404 #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100
405 #define HDMI_I2C_TRANSACTION_REG_START 0x00001000
406 #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000
407 #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000
414 #define REG_HDMI_DDC_DATA 0x00000238
415 #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001
416 #define HDMI_DDC_DATA_DATA_RW__SHIFT 0
421 #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00
427 #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000
433 #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000
435 #define REG_HDMI_HDCP_SHA_CTRL 0x0000023c
437 #define REG_HDMI_HDCP_SHA_STATUS 0x00000240
438 #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001
439 #define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010
441 #define REG_HDMI_HDCP_SHA_DATA 0x00000244
442 #define HDMI_HDCP_SHA_DATA_DONE 0x00000001
444 #define REG_HDMI_HPD_INT_STATUS 0x00000250
445 #define HDMI_HPD_INT_STATUS_INT 0x00000001
446 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002
448 #define REG_HDMI_HPD_INT_CTRL 0x00000254
449 #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001
450 #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002
451 #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004
452 #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010
453 #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020
454 #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200
456 #define REG_HDMI_HPD_CTRL 0x00000258
457 #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff
458 #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0
463 #define HDMI_HPD_CTRL_ENABLE 0x10000000
465 #define REG_HDMI_DDC_REF 0x0000027c
466 #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000
467 #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff
468 #define HDMI_DDC_REF_REFTIMER__SHIFT 0
474 #define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284
476 #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288
478 #define REG_HDMI_CEC_CTRL 0x0000028c
480 #define REG_HDMI_CEC_WR_DATA 0x00000290
482 #define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294
484 #define REG_HDMI_CEC_STATUS 0x00000298
486 #define REG_HDMI_CEC_INT 0x0000029c
488 #define REG_HDMI_CEC_ADDR 0x000002a0
490 #define REG_HDMI_CEC_TIME 0x000002a4
492 #define REG_HDMI_CEC_REFTIMER 0x000002a8
494 #define REG_HDMI_CEC_RD_DATA 0x000002ac
496 #define REG_HDMI_CEC_RD_FILTER 0x000002b0
498 #define REG_HDMI_ACTIVE_HSYNC 0x000002b4
499 #define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
500 #define HDMI_ACTIVE_HSYNC_START__SHIFT 0
505 #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000
512 #define REG_HDMI_ACTIVE_VSYNC 0x000002b8
513 #define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
514 #define HDMI_ACTIVE_VSYNC_START__SHIFT 0
519 #define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
526 #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
527 #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
528 #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
533 #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
540 #define REG_HDMI_TOTAL 0x000002c0
541 #define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
542 #define HDMI_TOTAL_H_TOTAL__SHIFT 0
547 #define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
554 #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
555 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
556 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
562 #define REG_HDMI_FRAME_CTRL 0x000002c8
563 #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000
564 #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000
565 #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
566 #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
568 #define REG_HDMI_AUD_INT 0x000002cc
569 #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
570 #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
571 #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
572 #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
574 #define REG_HDMI_PHY_CTRL 0x000002d4
575 #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
576 #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
577 #define HDMI_PHY_CTRL_SW_RESET 0x00000004
578 #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
580 #define REG_HDMI_CEC_WR_RANGE 0x000002dc
582 #define REG_HDMI_CEC_RD_RANGE 0x000002e0
584 #define REG_HDMI_VERSION 0x000002e4
586 #define REG_HDMI_CEC_COMPL_CTL 0x00000360
588 #define REG_HDMI_CEC_RD_START_RANGE 0x00000364
590 #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
592 #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
594 #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
596 #define REG_HDMI_8x60_PHY_REG0 0x00000000
597 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
604 #define REG_HDMI_8x60_PHY_REG1 0x00000004
605 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0
611 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f
612 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0
618 #define REG_HDMI_8x60_PHY_REG2 0x00000008
619 #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001
620 #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002
621 #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
622 #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008
623 #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010
624 #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020
625 #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040
626 #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080
628 #define REG_HDMI_8x60_PHY_REG3 0x0000000c
629 #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001
631 #define REG_HDMI_8x60_PHY_REG4 0x00000010
633 #define REG_HDMI_8x60_PHY_REG5 0x00000014
635 #define REG_HDMI_8x60_PHY_REG6 0x00000018
637 #define REG_HDMI_8x60_PHY_REG7 0x0000001c
639 #define REG_HDMI_8x60_PHY_REG8 0x00000020
641 #define REG_HDMI_8x60_PHY_REG9 0x00000024
643 #define REG_HDMI_8x60_PHY_REG10 0x00000028
645 #define REG_HDMI_8x60_PHY_REG11 0x0000002c
647 #define REG_HDMI_8x60_PHY_REG12 0x00000030
648 #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001
649 #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002
650 #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010
652 #define REG_HDMI_8960_PHY_REG0 0x00000000
654 #define REG_HDMI_8960_PHY_REG1 0x00000004
656 #define REG_HDMI_8960_PHY_REG2 0x00000008
658 #define REG_HDMI_8960_PHY_REG3 0x0000000c
660 #define REG_HDMI_8960_PHY_REG4 0x00000010
662 #define REG_HDMI_8960_PHY_REG5 0x00000014
664 #define REG_HDMI_8960_PHY_REG6 0x00000018
666 #define REG_HDMI_8960_PHY_REG7 0x0000001c
668 #define REG_HDMI_8960_PHY_REG8 0x00000020
670 #define REG_HDMI_8960_PHY_REG9 0x00000024
672 #define REG_HDMI_8960_PHY_REG10 0x00000028
674 #define REG_HDMI_8960_PHY_REG11 0x0000002c
676 #define REG_HDMI_8960_PHY_REG12 0x00000030
677 #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
678 #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
680 #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034
682 #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038
684 #define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c
686 #define REG_HDMI_8960_PHY_REG13 0x00000040
688 #define REG_HDMI_8960_PHY_REG14 0x00000044
690 #define REG_HDMI_8960_PHY_REG15 0x00000048
692 #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000
694 #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004
696 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008
698 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c
700 #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010
702 #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014
704 #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018
705 #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
706 #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
708 #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c
710 #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020
712 #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024
714 #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028
716 #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c
718 #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030
720 #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034
722 #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038
724 #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c
726 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040
728 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044
730 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048
732 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c
734 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050
736 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054
738 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058
740 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c
742 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060
744 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064
746 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068
748 #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c
750 #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070
752 #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074
754 #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078
756 #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c
758 #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080
760 #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084
762 #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088
764 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c
766 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090
768 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094
770 #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098
771 #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
773 #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c
775 #define REG_HDMI_8x74_ANA_CFG0 0x00000000
777 #define REG_HDMI_8x74_ANA_CFG1 0x00000004
779 #define REG_HDMI_8x74_ANA_CFG2 0x00000008
781 #define REG_HDMI_8x74_ANA_CFG3 0x0000000c
783 #define REG_HDMI_8x74_PD_CTRL0 0x00000010
785 #define REG_HDMI_8x74_PD_CTRL1 0x00000014
787 #define REG_HDMI_8x74_GLB_CFG 0x00000018
789 #define REG_HDMI_8x74_DCC_CFG0 0x0000001c
791 #define REG_HDMI_8x74_DCC_CFG1 0x00000020
793 #define REG_HDMI_8x74_TXCAL_CFG0 0x00000024
795 #define REG_HDMI_8x74_TXCAL_CFG1 0x00000028
797 #define REG_HDMI_8x74_TXCAL_CFG2 0x0000002c
799 #define REG_HDMI_8x74_TXCAL_CFG3 0x00000030
801 #define REG_HDMI_8x74_BIST_CFG0 0x00000034
803 #define REG_HDMI_8x74_BIST_PATN0 0x0000003c
805 #define REG_HDMI_8x74_BIST_PATN1 0x00000040
807 #define REG_HDMI_8x74_BIST_PATN2 0x00000044
809 #define REG_HDMI_8x74_BIST_PATN3 0x00000048
811 #define REG_HDMI_8x74_STATUS 0x0000005c
813 #define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
815 #define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
817 #define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
819 #define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
821 #define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
823 #define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
825 #define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
827 #define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
829 #define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
830 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
831 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
832 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
833 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
835 #define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
837 #define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
839 #define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
841 #define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
843 #define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
845 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
847 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
849 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
851 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
853 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
855 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
857 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
859 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
861 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
863 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
865 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
867 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
869 #define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
870 #define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
872 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
874 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
876 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
878 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
880 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
882 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
884 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
886 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
888 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
890 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
892 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
894 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
896 #define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
898 #define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
900 #define REG_HDMI_28nm_PHY_PLL_STATUS 0x000000c0
902 #define REG_HDMI_8996_PHY_CFG 0x00000000
904 #define REG_HDMI_8996_PHY_PD_CTL 0x00000004
906 #define REG_HDMI_8996_PHY_MODE 0x00000008
908 #define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c
910 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010
912 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014
914 #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018
916 #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c
918 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020
920 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024
922 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028
924 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c
926 #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030
928 #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034
930 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038
932 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c
934 #define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040
936 #define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044
938 #define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048
940 #define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c
942 #define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050
944 #define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054
946 #define REG_HDMI_8996_PHY_CLOCK 0x00000058
948 #define REG_HDMI_8996_PHY_MISC1 0x0000005c
950 #define REG_HDMI_8996_PHY_MISC2 0x00000060
952 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064
954 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068
956 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c
958 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070
960 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074
962 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078
964 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c
966 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080
968 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084
970 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088
972 #define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c
974 #define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090
976 #define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094
978 #define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098
980 #define REG_HDMI_8996_PHY_STATUS 0x0000009c
982 #define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0
984 #define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4
986 #define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8
988 #define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac
990 #define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0
992 #define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4
994 #define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8
996 #define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc
998 #define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0
1000 #define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4
1002 #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000
1004 #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004
1006 #define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008
1008 #define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c
1010 #define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010
1012 #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014
1014 #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018
1016 #define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c
1018 #define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020
1020 #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024
1022 #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028
1024 #define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c
1026 #define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030
1028 #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034
1030 #define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038
1032 #define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c
1034 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040
1036 #define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044
1038 #define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048
1040 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c
1042 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050
1044 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054
1046 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058
1048 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c
1050 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060
1052 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064
1054 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064
1056 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068
1058 #define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068
1060 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c
1062 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c
1064 #define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070
1066 #define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074
1068 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078
1070 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c
1072 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080
1074 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080
1076 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084
1078 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088
1080 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c
1082 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c
1084 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090
1086 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094
1088 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098
1090 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098
1092 #define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c
1094 #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0
1096 #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4
1098 #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8
1100 #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8
1102 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac
1104 #define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0
1106 #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4
1108 #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8
1110 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc
1112 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0
1114 #define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4
1116 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8
1118 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc
1120 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0
1122 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4
1124 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8
1126 #define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8
1128 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc
1130 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0
1132 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4
1134 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8
1136 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec
1138 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0
1140 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4
1142 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4
1144 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8
1146 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8
1148 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc
1150 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc
1152 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100
1154 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104
1156 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108
1158 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c
1160 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110
1162 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114
1164 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118
1166 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118
1168 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c
1170 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c
1172 #define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120
1174 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124
1176 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128
1178 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c
1180 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130
1182 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134
1184 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138
1186 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c
1188 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c
1190 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140
1192 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140
1194 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144
1196 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148
1198 #define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c
1200 #define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150
1202 #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154
1204 #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158
1206 #define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c
1208 #define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160
1210 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164
1212 #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168
1214 #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c
1216 #define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170
1218 #define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174
1220 #define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178
1222 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c
1224 #define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180
1226 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184
1228 #define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188
1230 #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c
1232 #define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190
1234 #define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194
1236 #define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198
1238 #define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c
1240 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0
1242 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4
1244 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8
1246 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac
1248 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0
1250 #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4
1252 #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8
1254 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc
1256 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0
1258 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4
1260 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000
1262 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004
1264 #define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008
1266 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c
1268 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010
1270 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014
1272 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018
1274 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c
1276 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020
1278 #define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024
1280 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028
1282 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c
1284 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030
1286 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034
1288 #define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038
1290 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c
1292 #define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040
1294 #define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044
1296 #define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048
1298 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c
1300 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050
1302 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054
1304 #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058
1306 #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c
1308 #define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060
1310 #define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064
1312 #define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068
1314 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c
1316 #define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070
1318 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074
1320 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078
1322 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c
1324 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080
1326 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084
1328 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088
1330 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c
1332 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090
1334 #define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094
1336 #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098
1338 #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c
1340 #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0
1342 #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4
1344 #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8
1346 #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac
1348 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0
1350 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4
1352 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8
1354 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc
1356 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0
1358 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4
1360 #define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8
1362 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc
1364 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0
1366 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4
1368 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8
1370 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc
1372 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0
1374 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4
1376 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8
1378 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec
1380 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0
1382 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4
1384 #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8
1386 #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc
1388 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100
1390 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104
1392 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108
1394 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c
1396 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110