1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2f3fcf92dSVipin KUMAR /* 3f3fcf92dSVipin KUMAR * (C) Copyright 2009 4f3fcf92dSVipin KUMAR * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 5f3fcf92dSVipin KUMAR */ 6f3fcf92dSVipin KUMAR 7f3fcf92dSVipin KUMAR #ifndef ST_SMI_H 8f3fcf92dSVipin KUMAR #define ST_SMI_H 9f3fcf92dSVipin KUMAR 10f3fcf92dSVipin KUMAR /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ 11f3fcf92dSVipin KUMAR /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ 12f3fcf92dSVipin KUMAR 13f3fcf92dSVipin KUMAR #define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE 14f3fcf92dSVipin KUMAR #define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE 15f3fcf92dSVipin KUMAR 16f3fcf92dSVipin KUMAR #define SMIBANK0_BASE (FLASH_START_ADDRESS) 17f3fcf92dSVipin KUMAR #define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) 18f3fcf92dSVipin KUMAR #define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) 19f3fcf92dSVipin KUMAR #define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) 20f3fcf92dSVipin KUMAR 21f3fcf92dSVipin KUMAR #define BANK0 0 22f3fcf92dSVipin KUMAR #define BANK1 1 23f3fcf92dSVipin KUMAR #define BANK2 2 24f3fcf92dSVipin KUMAR #define BANK3 3 25f3fcf92dSVipin KUMAR 26f3fcf92dSVipin KUMAR struct smi_regs { 27f3fcf92dSVipin KUMAR u32 smi_cr1; 28f3fcf92dSVipin KUMAR u32 smi_cr2; 29f3fcf92dSVipin KUMAR u32 smi_sr; 30f3fcf92dSVipin KUMAR u32 smi_tr; 31f3fcf92dSVipin KUMAR u32 smi_rr; 32f3fcf92dSVipin KUMAR }; 33f3fcf92dSVipin KUMAR 34f3fcf92dSVipin KUMAR /* CONTROL REG 1 */ 35f3fcf92dSVipin KUMAR #define BANK_EN 0x0000000F /* enables all banks */ 36f3fcf92dSVipin KUMAR #define DSEL_TIME 0x00000060 /* Deselect time */ 37f3fcf92dSVipin KUMAR #define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ 38f3fcf92dSVipin KUMAR #define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ 39f3fcf92dSVipin KUMAR #define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ 40f3fcf92dSVipin KUMAR #define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ 41f3fcf92dSVipin KUMAR #define SW_MODE 0x10000000 /* enables SW Mode */ 42f3fcf92dSVipin KUMAR #define WB_MODE 0x20000000 /* Write Burst Mode */ 43f3fcf92dSVipin KUMAR #define FAST_MODE 0x00008000 /* Fast Mode */ 44f3fcf92dSVipin KUMAR #define HOLD1 0x00010000 45f3fcf92dSVipin KUMAR 46f3fcf92dSVipin KUMAR /* CONTROL REG 2 */ 47f3fcf92dSVipin KUMAR #define RD_STATUS_REG 0x00000400 /* reads status reg */ 48f3fcf92dSVipin KUMAR #define WE 0x00000800 /* Write Enable */ 49f3fcf92dSVipin KUMAR #define BANK0_SEL 0x00000000 /* Select Banck0 */ 50f3fcf92dSVipin KUMAR #define BANK1_SEL 0x00001000 /* Select Banck1 */ 51f3fcf92dSVipin KUMAR #define BANK2_SEL 0x00002000 /* Select Banck2 */ 52f3fcf92dSVipin KUMAR #define BANK3_SEL 0x00003000 /* Select Banck3 */ 53f3fcf92dSVipin KUMAR #define BANKSEL_SHIFT 12 54f3fcf92dSVipin KUMAR #define SEND 0x00000080 /* Send data */ 55f3fcf92dSVipin KUMAR #define TX_LEN_1 0x00000001 /* data length = 1 byte */ 56f3fcf92dSVipin KUMAR #define TX_LEN_2 0x00000002 /* data length = 2 byte */ 57f3fcf92dSVipin KUMAR #define TX_LEN_3 0x00000003 /* data length = 3 byte */ 58f3fcf92dSVipin KUMAR #define TX_LEN_4 0x00000004 /* data length = 4 byte */ 59f3fcf92dSVipin KUMAR #define RX_LEN_1 0x00000010 /* data length = 1 byte */ 60f3fcf92dSVipin KUMAR #define RX_LEN_2 0x00000020 /* data length = 2 byte */ 61f3fcf92dSVipin KUMAR #define RX_LEN_3 0x00000030 /* data length = 3 byte */ 62f3fcf92dSVipin KUMAR #define RX_LEN_4 0x00000040 /* data length = 4 byte */ 63f3fcf92dSVipin KUMAR #define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ 64f3fcf92dSVipin KUMAR #define WCIE 0x00000200 /* WCF Interrupt Enable */ 65f3fcf92dSVipin KUMAR 66f3fcf92dSVipin KUMAR /* STATUS_REG */ 67f3fcf92dSVipin KUMAR #define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ 68f3fcf92dSVipin KUMAR #define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ 69f3fcf92dSVipin KUMAR #define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ 70f3fcf92dSVipin KUMAR #define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ 71f3fcf92dSVipin KUMAR #define RSR 0x00000005 /* Read Status regiser */ 72f3fcf92dSVipin KUMAR #define TFF 0x00000100 /* Transfer Finished FLag */ 73f3fcf92dSVipin KUMAR #define WCF 0x00000200 /* Transfer Finished FLag */ 74f3fcf92dSVipin KUMAR #define ERF1 0x00000400 /* Error Flag 1 */ 75f3fcf92dSVipin KUMAR #define ERF2 0x00000800 /* Error Flag 2 */ 76f3fcf92dSVipin KUMAR #define WM0 0x00001000 /* WM Bank 0 */ 77f3fcf92dSVipin KUMAR #define WM1 0x00002000 /* WM Bank 1 */ 78f3fcf92dSVipin KUMAR #define WM2 0x00004000 /* WM Bank 2 */ 79f3fcf92dSVipin KUMAR #define WM3 0x00008000 /* WM Bank 3 */ 80f3fcf92dSVipin KUMAR #define WM_SHIFT 12 81f3fcf92dSVipin KUMAR 82f3fcf92dSVipin KUMAR /* TR REG */ 83f3fcf92dSVipin KUMAR #define READ_ID 0x0000009F /* Read Identification */ 84f3fcf92dSVipin KUMAR #define BULK_ERASE 0x000000C7 /* BULK erase */ 85f3fcf92dSVipin KUMAR #define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ 86f3fcf92dSVipin KUMAR #define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ 87f3fcf92dSVipin KUMAR 88f3fcf92dSVipin KUMAR struct flash_dev { 89f3fcf92dSVipin KUMAR u32 density; 90f3fcf92dSVipin KUMAR ulong size; 91f3fcf92dSVipin KUMAR ushort sector_count; 92f3fcf92dSVipin KUMAR }; 93f3fcf92dSVipin KUMAR 94f3fcf92dSVipin KUMAR #define SFLASH_PAGE_SIZE 0x100 /* flash page size */ 950e88ff08SAmit Virdi #define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ 960e88ff08SAmit Virdi #define WMODE_TOUT 15 /* write enable timeout(in ms) */ 97f3fcf92dSVipin KUMAR 98f3fcf92dSVipin KUMAR extern void smi_init(void); 99f3fcf92dSVipin KUMAR 100f3fcf92dSVipin KUMAR #endif 101