1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8dxl.dtsi"
9
10/ {
11	model = "Freescale i.MX8DXL EVK";
12	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13
14	aliases {
15		i2c2 = &i2c2;
16		mmc0 = &usdhc1;
17		mmc1 = &usdhc2;
18		serial0 = &lpuart0;
19	};
20
21	chosen {
22		stdout-path = &lpuart0;
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		reg = <0x00000000 0x80000000 0 0x40000000>;
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		/*
36		 * Memory reserved for optee usage. Please do not use.
37		 * This will be automatically added to dtb if OP-TEE is installed.
38		 * optee@96000000 {
39		 *     reg = <0 0x96000000 0 0x2000000>;
40		 *     no-map;
41		 * };
42		 */
43
44		/* global autoconfigured region for contiguous allocations */
45		linux,cma {
46			compatible = "shared-dma-pool";
47			reusable;
48			size = <0 0x14000000>;
49			alloc-ranges = <0 0x98000000 0 0x14000000>;
50			linux,cma-default;
51		};
52	};
53
54	mux3_en: regulator-0 {
55		compatible = "regulator-fixed";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-name = "mux3_en";
59		gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
60		regulator-always-on;
61	};
62
63	reg_fec1_sel: regulator-1 {
64		compatible = "regulator-fixed";
65		regulator-name = "fec1_supply";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68		gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
69		regulator-always-on;
70		status = "disabled";
71	};
72
73	reg_fec1_io: regulator-2 {
74		compatible = "regulator-fixed";
75		regulator-name = "fec1_io_supply";
76		regulator-min-microvolt = <1800000>;
77		regulator-max-microvolt = <1800000>;
78		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
79		enable-active-high;
80		regulator-always-on;
81		status = "disabled";
82	};
83
84	reg_usdhc2_vmmc: regulator-3 {
85		compatible = "regulator-fixed";
86		regulator-name = "SD1_SPWR";
87		regulator-min-microvolt = <3000000>;
88		regulator-max-microvolt = <3000000>;
89		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
90		enable-active-high;
91		off-on-delay-us = <3480>;
92	};
93
94	reg_vref_1v8: regulator-adc-vref {
95		compatible = "regulator-fixed";
96		regulator-name = "vref_1v8";
97		regulator-min-microvolt = <1800000>;
98		regulator-max-microvolt = <1800000>;
99	};
100
101	mii_select: regulator-4 {
102		compatible = "regulator-fixed";
103		regulator-name = "mii-select";
104		regulator-min-microvolt = <3300000>;
105		regulator-max-microvolt = <3300000>;
106		gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
107		enable-active-high;
108		regulator-always-on;
109	};
110};
111
112&adc0 {
113	vref-supply = <&reg_vref_1v8>;
114	status = "okay";
115};
116
117&eqos {
118	pinctrl-names = "default";
119	pinctrl-0 = <&pinctrl_eqos>;
120	phy-mode = "rgmii-id";
121	phy-handle = <&ethphy0>;
122	nvmem-cells = <&fec_mac1>;
123	nvmem-cell-names = "mac-address";
124	status = "okay";
125
126	mdio {
127		compatible = "snps,dwmac-mdio";
128		#address-cells = <1>;
129		#size-cells = <0>;
130
131		ethphy0: ethernet-phy@0 {
132			compatible = "ethernet-phy-ieee802.3-c22";
133			reg = <0>;
134			eee-broken-1000t;
135			qca,disable-smarteee;
136			qca,disable-hibernation-mode;
137			reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
138			reset-assert-us = <20>;
139			reset-deassert-us = <200000>;
140			vddio-supply = <&vddio0>;
141
142			vddio0: vddio-regulator {
143				regulator-min-microvolt = <1800000>;
144				regulator-max-microvolt = <1800000>;
145			};
146		};
147	};
148};
149
150/*
151 * fec1 shares the some PINs with usdhc2.
152 * by default usdhc2 is enabled in this dts.
153 * Please disable usdhc2 to enable fec1
154 */
155&fec1 {
156	pinctrl-names = "default";
157	pinctrl-0 = <&pinctrl_fec1>;
158	phy-mode = "rgmii-txid";
159	phy-handle = <&ethphy1>;
160	fsl,magic-packet;
161	rx-internal-delay-ps = <2000>;
162	nvmem-cells = <&fec_mac0>;
163	nvmem-cell-names = "mac-address";
164	status = "disabled";
165
166	mdio {
167		#address-cells = <1>;
168		#size-cells = <0>;
169
170		ethphy1: ethernet-phy@1 {
171			compatible = "ethernet-phy-ieee802.3-c22";
172			reg = <1>;
173			reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
174			reset-assert-us = <10000>;
175			qca,disable-smarteee;
176			vddio-supply = <&vddio1>;
177
178			vddio1: vddio-regulator {
179				regulator-min-microvolt = <1800000>;
180				regulator-max-microvolt = <1800000>;
181			};
182		};
183	};
184};
185
186&flexspi0 {
187	pinctrl-names = "default";
188	pinctrl-0 = <&pinctrl_flexspi0>;
189	nxp,fspi-dll-slvdly = <4>;
190	status = "okay";
191
192	mt35xu512aba0: flash@0 {
193		reg = <0>;
194		#address-cells = <1>;
195		#size-cells = <1>;
196		compatible = "jedec,spi-nor";
197		spi-max-frequency = <133000000>;
198		spi-tx-bus-width = <8>;
199		spi-rx-bus-width = <8>;
200	};
201};
202
203&i2c2 {
204	#address-cells = <1>;
205	#size-cells = <0>;
206	clock-frequency = <100000>;
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_i2c2>;
209	status = "okay";
210
211	pca6416_1: gpio@20 {
212		compatible = "ti,tca6416";
213		reg = <0x20>;
214		gpio-controller;
215		#gpio-cells = <2>;
216	};
217
218	pca6416_2: gpio@21 {
219		compatible = "ti,tca6416";
220		reg = <0x21>;
221		gpio-controller;
222		#gpio-cells = <2>;
223	};
224
225	pca9548_1: i2c-mux@70 {
226		compatible = "nxp,pca9548";
227		#address-cells = <1>;
228		#size-cells = <0>;
229		reg = <0x70>;
230
231		i2c@0 {
232			#address-cells = <1>;
233			#size-cells = <0>;
234			reg = <0x0>;
235
236			max7322: gpio@68 {
237				compatible = "maxim,max7322";
238				reg = <0x68>;
239				gpio-controller;
240				#gpio-cells = <2>;
241				status = "disabled";
242			};
243		};
244
245		i2c@4 {
246			#address-cells = <1>;
247			#size-cells = <0>;
248			reg = <0x4>;
249		};
250
251		i2c@5 {
252			#address-cells = <1>;
253			#size-cells = <0>;
254			reg = <0x5>;
255		};
256
257		i2c@6 {
258			#address-cells = <1>;
259			#size-cells = <0>;
260			reg = <0x6>;
261		};
262	};
263};
264
265&lpuart0 {
266	pinctrl-names = "default";
267	pinctrl-0 = <&pinctrl_lpuart0>;
268	status = "okay";
269};
270
271&lsio_gpio4 {
272	status = "okay";
273};
274
275&lsio_gpio5 {
276	status = "okay";
277};
278
279&thermal_zones {
280	pmic-thermal {
281		polling-delay-passive = <250>;
282		polling-delay = <2000>;
283		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
284
285		trips {
286			pmic_alert0: trip0 {
287				temperature = <110000>;
288				hysteresis = <2000>;
289				type = "passive";
290			};
291
292			pmic_crit0: trip1 {
293				temperature = <125000>;
294				hysteresis = <2000>;
295				type = "critical";
296			};
297		};
298
299		cooling-maps {
300			map0 {
301				trip = <&pmic_alert0>;
302				cooling-device =
303					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
304					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
305			};
306		};
307	};
308};
309
310&usbphy1 {
311	/* USB eye diagram tests result */
312	fsl,tx-d-cal = <114>;
313	status = "okay";
314};
315
316&usbotg1 {
317	pinctrl-names = "default";
318	pinctrl-0 = <&pinctrl_usbotg1>;
319	srp-disable;
320	hnp-disable;
321	adp-disable;
322	power-active-high;
323	disable-over-current;
324	status = "okay";
325};
326
327&usbphy2 {
328	/* USB eye diagram tests result */
329	fsl,tx-d-cal = <111>;
330	status = "okay";
331};
332
333&usbotg2 {
334	pinctrl-names = "default";
335	pinctrl-0 = <&pinctrl_usbotg2>;
336	srp-disable;
337	hnp-disable;
338	adp-disable;
339	power-active-high;
340	disable-over-current;
341	status = "okay";
342};
343
344&usdhc1 {
345	pinctrl-names = "default";
346	pinctrl-0 = <&pinctrl_usdhc1>;
347	bus-width = <8>;
348	no-sd;
349	no-sdio;
350	non-removable;
351	status = "okay";
352};
353
354&usdhc2 {
355	pinctrl-names = "default";
356	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
357	bus-width = <4>;
358	vmmc-supply = <&reg_usdhc2_vmmc>;
359	cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
360	wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
361	status = "okay";
362};
363
364&lpspi3 {
365	fsl,spi-only-use-cs1-sel;
366	pinctrl-names = "default";
367	pinctrl-0 = <&pinctrl_lpspi3>;
368	pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
369	status = "okay";
370
371	spidev0: spi@0 {
372		reg = <0>;
373		compatible = "rohm,dh2228fv";
374		spi-max-frequency = <30000000>;
375	};
376};
377
378&iomuxc {
379	pinctrl-names = "default";
380	pinctrl-0 = <&pinctrl_hog>;
381
382	pinctrl_hog: hoggrp {
383		fsl,pins = <
384			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
385			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
386			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
387			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
388		>;
389	};
390
391	pinctrl_usbotg1: usbotg1grp {
392		fsl,pins = <
393			IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
394		>;
395	};
396
397	pinctrl_usbotg2: usbotg2grp {
398		fsl,pins = <
399			IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR		0x00000021
400		>;
401	};
402
403	pinctrl_eqos: eqosgrp {
404		fsl,pins = <
405			IMX8DXL_ENET0_MDC_CONN_EQOS_MDC				0x06000020
406			IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
407			IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x06000020
408			IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0		0x06000020
409			IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1		0x06000020
410			IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2		0x06000020
411			IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3		0x06000020
412			IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x06000020
413			IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x06000020
414			IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0		0x06000020
415			IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1		0x06000020
416			IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2		0x06000020
417			IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3		0x06000020
418			IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL	0x06000020
419		>;
420	};
421
422	pinctrl_flexspi0: flexspi0grp {
423		fsl,pins = <
424			IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
425			IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
426			IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
427			IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
428			IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
429			IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
430			IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
431			IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
432			IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
433			IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
434			IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
435			IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
436			IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
437			IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
438		>;
439	};
440
441	pinctrl_fec1: fec1grp {
442		fsl,pins = <
443			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD		0x000014a0
444			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD		0x000014a0
445			IMX8DXL_ENET0_MDC_CONN_ENET0_MDC			0x06000020
446			IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
447			IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x00000060
448			IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x00000060
449			IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x00000060
450			IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x00000060
451			IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x00000060
452			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
453			IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x00000060
454			IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x00000060
455			IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x00000060
456			IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x00000060
457			IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x00000060
458			IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
459		>;
460	};
461
462	pinctrl_lpspi3: lpspi3grp {
463		fsl,pins = <
464			IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK		0x6000040
465			IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO		0x6000040
466			IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI		0x6000040
467			IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1		0x6000040
468		>;
469	};
470
471	pinctrl_i2c2: i2c2grp {
472		fsl,pins = <
473			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
474			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
475		>;
476	};
477
478	pinctrl_cm40_lpuart: cm40lpuartgrp {
479		fsl,pins = <
480			IMX8DXL_ADC_IN2_M40_UART0_RX		0x06000020
481			IMX8DXL_ADC_IN3_M40_UART0_TX		0x06000020
482		>;
483	};
484
485	pinctrl_i2c3: i2c3grp {
486		fsl,pins = <
487			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
488			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
489		>;
490	};
491
492	pinctrl_lpuart0: lpuart0grp {
493		fsl,pins = <
494			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
495			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
496		>;
497	};
498
499	pinctrl_usdhc1: usdhc1grp {
500		fsl,pins = <
501			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
502			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
503			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
504			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
505			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
506			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
507			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
508			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
509			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
510			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
511			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
512		>;
513	};
514
515	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
516		fsl,pins = <
517			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
518			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
519			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
520		>;
521	};
522
523	pinctrl_usdhc2: usdhc2grp {
524		fsl,pins = <
525			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
526			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
527			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
528			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
529			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
530			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
531			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
532		>;
533	};
534};
535