Lines Matching +full:0 +full:x00000060
12 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
14 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
16 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
18 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
63 u32 mrcr; /* 0x100 Master Remap Control */
66 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
67 u32 womr; /* 0x1E4 Write Protect Mode */
68 u32 wpsr; /* 0x1E8 Write Protect Status */
88 #define AT91_MATRIX_CSA_DBPUC 0x00000100
89 #define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
90 #define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000
92 #define AT91_MATRIX_CSA_EBI_CS1A 0x00000002
93 #define AT91_MATRIX_CSA_EBI_CS3A 0x00000008
94 #define AT91_MATRIX_CSA_EBI_CS4A 0x00000010
95 #define AT91_MATRIX_CSA_EBI_CS5A 0x00000020
97 #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
100 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
101 #define AT91_MATRIX_MCFG_RCB0 (1 << 0)
109 #define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
110 #define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
111 #define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
112 #define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
113 #define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
116 #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
117 #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
118 #define AT91_MATRIX_MCFG_ULBT_128 0x00000007
122 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000
123 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000
124 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
129 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
136 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
139 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
144 #define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000
145 #define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000
151 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
152 #define AT91_MATRIX_MRCR_RCB0 (1 << 0)
158 #define AT91_MATRIX_MRCR_RCB2 0x00000004
159 #define AT91_MATRIX_MRCR_RCB3 0x00000008
160 #define AT91_MATRIX_MRCR_RCB4 0x00000010
161 #define AT91_MATRIX_MRCR_RCB5 0x00000020
162 #define AT91_MATRIX_MRCR_RCB6 0x00000040
163 #define AT91_MATRIX_MRCR_RCB7 0x00000080
164 #define AT91_MATRIX_MRCR_RCB8 0x00000100
167 #define AT91_MATRIX_MRCR_RCB9 0x00000200
168 #define AT91_MATRIX_MRCR_RCB10 0x00000400
169 #define AT91_MATRIX_MRCR_RCB11 0x00000800
175 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
176 #define AT91_MATRIX_TCMR_ITCM_32 0x00000040
178 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
179 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
180 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070
182 #define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000
183 #define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800
187 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
188 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005
189 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006
191 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
192 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050
193 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
197 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
198 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005
199 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006
200 #define AT91_MATRIX_TCMR_ITCM_64 0x00000007
202 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
203 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050
204 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
205 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070
210 #define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
211 #define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
213 #define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000
214 #define AT91_MATRIX_WPMR_WP_WPEN 0x00000001
215 #define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */
217 #define AT91_MATRIX_WPSR_NO_WPV 0x00000000
218 #define AT91_MATRIX_WPSR_WPV 0x00000001
219 #define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */
224 #define AT91_MATRIX_USBPUCR_PUON 0x40000000
227 #define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/
235 #define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */