Lines Matching +full:0 +full:x00000060
22 #define BR_BA 0xFFFF8000
24 #define BR_PS 0x00001800
26 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
27 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
28 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
29 #define BR_DECC 0x00000600
31 #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
32 #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
33 #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
34 #define BR_WP 0x00000100
36 #define BR_MSEL 0x000000E0
38 #define BR_MS_GPCM 0x00000000 /* GPCM */
39 #define BR_MS_FCM 0x00000020 /* FCM */
40 #define BR_MS_SDRAM 0x00000060 /* SDRAM */
41 #define BR_MS_UPMA 0x00000080 /* UPMA */
42 #define BR_MS_UPMB 0x000000A0 /* UPMB */
43 #define BR_MS_UPMC 0x000000C0 /* UPMC */
44 #define BR_V 0x00000001
45 #define BR_V_SHIFT 0
49 #define OR0 0x5004
50 #define OR1 0x500C
51 #define OR2 0x5014
52 #define OR3 0x501C
53 #define OR4 0x5024
54 #define OR5 0x502C
55 #define OR6 0x5034
56 #define OR7 0x503C
58 #define OR_FCM_AM 0xFFFF8000
60 #define OR_FCM_BCTLD 0x00001000
62 #define OR_FCM_PGS 0x00000400
64 #define OR_FCM_CSCT 0x00000200
66 #define OR_FCM_CST 0x00000100
68 #define OR_FCM_CHT 0x00000080
70 #define OR_FCM_SCY 0x00000070
72 #define OR_FCM_SCY_1 0x00000010
73 #define OR_FCM_SCY_2 0x00000020
74 #define OR_FCM_SCY_3 0x00000030
75 #define OR_FCM_SCY_4 0x00000040
76 #define OR_FCM_SCY_5 0x00000050
77 #define OR_FCM_SCY_6 0x00000060
78 #define OR_FCM_SCY_7 0x00000070
79 #define OR_FCM_RST 0x00000008
81 #define OR_FCM_TRLX 0x00000004
83 #define OR_FCM_EHTR 0x00000002
86 #define OR_GPCM_AM 0xFFFF8000
92 u8 res0[0x8];
94 u8 res1[0x4];
96 #define MxMR_OP_NO (0 << 28) /**< normal operation */
100 #define MxMR_MAD 0x3f /**< machine address */
103 u8 res2[0x8];
106 u8 res3[0x4];
109 u8 res4[0x8];
112 u8 res5[0x8];
114 #define LTESR_BM 0x80000000
115 #define LTESR_FCT 0x40000000
116 #define LTESR_PAR 0x20000000
117 #define LTESR_WP 0x04000000
118 #define LTESR_ATMW 0x00800000
119 #define LTESR_ATMR 0x00400000
120 #define LTESR_CS 0x00080000
121 #define LTESR_UPM 0x00000002
122 #define LTESR_CC 0x00000001
127 #define LTESR_CLEAR 0xFFFFFFFF
128 #define LTECCR_CLEAR 0xFFFFFFFF
131 #define LTEDR_ENABLE 0x00000000
137 u8 res6[0x8];
139 #define LBCR_LDIS 0x80000000
141 #define LBCR_BCTLC 0x00C00000
143 #define LBCR_AHD 0x00200000
144 #define LBCR_LPBSE 0x00020000
146 #define LBCR_EPAR 0x00010000
148 #define LBCR_BMT 0x0000FF00
150 #define LBCR_BMTPS 0x0000000F
151 #define LBCR_BMTPS_SHIFT 0
152 #define LBCR_INIT 0x00040000
154 #define LCRR_DBYP 0x80000000
156 #define LCRR_BUFCMDC 0x30000000
158 #define LCRR_ECL 0x03000000
160 #define LCRR_EADC 0x00030000
162 #define LCRR_CLKDIV 0x0000000F
163 #define LCRR_CLKDIV_SHIFT 0
164 u8 res7[0x8];
166 #define FMR_CWTO 0x0000F000
168 #define FMR_BOOT 0x00000800
169 #define FMR_ECCM 0x00000100
170 #define FMR_AL 0x00000030
172 #define FMR_OP 0x00000003
173 #define FMR_OP_SHIFT 0
175 #define FIR_OP0 0xF0000000
177 #define FIR_OP1 0x0F000000
179 #define FIR_OP2 0x00F00000
181 #define FIR_OP3 0x000F0000
183 #define FIR_OP4 0x0000F000
185 #define FIR_OP5 0x00000F00
187 #define FIR_OP6 0x000000F0
189 #define FIR_OP7 0x0000000F
190 #define FIR_OP7_SHIFT 0
191 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */
192 #define FIR_OP_CA 0x1 /* Issue current column address */
193 #define FIR_OP_PA 0x2 /* Issue current block+page address */
194 #define FIR_OP_UA 0x3 /* Issue user defined address */
195 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
196 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
197 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
198 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
199 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
200 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
201 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
202 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
203 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
204 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
205 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
206 #define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
208 #define FCR_CMD0 0xFF000000
210 #define FCR_CMD1 0x00FF0000
212 #define FCR_CMD2 0x0000FF00
214 #define FCR_CMD3 0x000000FF
215 #define FCR_CMD3_SHIFT 0
217 #define FBAR_BLK 0x00FFFFFF
219 #define FPAR_SP_PI 0x00007C00
221 #define FPAR_SP_MS 0x00000200
222 #define FPAR_SP_CI 0x000001FF
223 #define FPAR_SP_CI_SHIFT 0
224 #define FPAR_LP_PI 0x0003F000
226 #define FPAR_LP_MS 0x00000800
227 #define FPAR_LP_CI 0x000007FF
228 #define FPAR_LP_CI_SHIFT 0
230 #define FBCR_BC 0x00000FFF