10cf6c71dSRob Clark #ifndef HDMI_XML
20cf6c71dSRob Clark #define HDMI_XML
30cf6c71dSRob Clark
40cf6c71dSRob Clark /* Autogenerated file, DO NOT EDIT manually!
50cf6c71dSRob Clark
60cf6c71dSRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository:
722ba8b6bSRob Clark http://github.com/freedreno/envytools/
822ba8b6bSRob Clark git clone https://github.com/freedreno/envytools.git
90cf6c71dSRob Clark
100cf6c71dSRob Clark The rules-ng-ng source files this header was generated from are:
11*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
290cf6c71dSRob Clark
30*f73343faSRob Clark Copyright (C) 2013-2022 by the following authors:
310cf6c71dSRob Clark - Rob Clark <robdclark@gmail.com> (robclark)
32a2272e48SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
330cf6c71dSRob Clark
340cf6c71dSRob Clark Permission is hereby granted, free of charge, to any person obtaining
350cf6c71dSRob Clark a copy of this software and associated documentation files (the
360cf6c71dSRob Clark "Software"), to deal in the Software without restriction, including
370cf6c71dSRob Clark without limitation the rights to use, copy, modify, merge, publish,
380cf6c71dSRob Clark distribute, sublicense, and/or sell copies of the Software, and to
390cf6c71dSRob Clark permit persons to whom the Software is furnished to do so, subject to
400cf6c71dSRob Clark the following conditions:
410cf6c71dSRob Clark
420cf6c71dSRob Clark The above copyright notice and this permission notice (including the
430cf6c71dSRob Clark next paragraph) shall be included in all copies or substantial
440cf6c71dSRob Clark portions of the Software.
450cf6c71dSRob Clark
460cf6c71dSRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
470cf6c71dSRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
480cf6c71dSRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
490cf6c71dSRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
500cf6c71dSRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
510cf6c71dSRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
520cf6c71dSRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
530cf6c71dSRob Clark */
540cf6c71dSRob Clark
550cf6c71dSRob Clark
560cf6c71dSRob Clark enum hdmi_hdcp_key_state {
578a264743SRob Clark HDCP_KEYS_STATE_NO_KEYS = 0,
588a264743SRob Clark HDCP_KEYS_STATE_NOT_CHECKED = 1,
598a264743SRob Clark HDCP_KEYS_STATE_CHECKING = 2,
608a264743SRob Clark HDCP_KEYS_STATE_VALID = 3,
618a264743SRob Clark HDCP_KEYS_STATE_AKSV_NOT_VALID = 4,
628a264743SRob Clark HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5,
638a264743SRob Clark HDCP_KEYS_STATE_PROD_AKSV = 6,
648a264743SRob Clark HDCP_KEYS_STATE_RESERVED = 7,
650cf6c71dSRob Clark };
660cf6c71dSRob Clark
670cf6c71dSRob Clark enum hdmi_ddc_read_write {
680cf6c71dSRob Clark DDC_WRITE = 0,
690cf6c71dSRob Clark DDC_READ = 1,
700cf6c71dSRob Clark };
710cf6c71dSRob Clark
720cf6c71dSRob Clark enum hdmi_acr_cts {
730cf6c71dSRob Clark ACR_NONE = 0,
740cf6c71dSRob Clark ACR_32 = 1,
750cf6c71dSRob Clark ACR_44 = 2,
760cf6c71dSRob Clark ACR_48 = 3,
770cf6c71dSRob Clark };
780cf6c71dSRob Clark
790cf6c71dSRob Clark #define REG_HDMI_CTRL 0x00000000
800cf6c71dSRob Clark #define HDMI_CTRL_ENABLE 0x00000001
810cf6c71dSRob Clark #define HDMI_CTRL_HDMI 0x00000002
820cf6c71dSRob Clark #define HDMI_CTRL_ENCRYPTED 0x00000004
830cf6c71dSRob Clark
840cf6c71dSRob Clark #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
850cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
860cf6c71dSRob Clark
870cf6c71dSRob Clark #define REG_HDMI_ACR_PKT_CTRL 0x00000024
880cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_CONT 0x00000001
890cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SEND 0x00000002
900cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030
910cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4
HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)920cf6c71dSRob Clark static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
930cf6c71dSRob Clark {
940cf6c71dSRob Clark return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK;
950cf6c71dSRob Clark }
960cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100
970cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000
980cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16
HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)990cf6c71dSRob Clark static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
1000cf6c71dSRob Clark {
1010cf6c71dSRob Clark return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK;
1020cf6c71dSRob Clark }
1030cf6c71dSRob Clark #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000
1040cf6c71dSRob Clark
1050cf6c71dSRob Clark #define REG_HDMI_VBI_PKT_CTRL 0x00000028
1060cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010
1070cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020
1080cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100
1090cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200
1100cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000
1110cf6c71dSRob Clark #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000
1120cf6c71dSRob Clark
1130cf6c71dSRob Clark #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c
1140cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001
1150cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002
1160cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010
1170cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020
1180cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
1190cf6c71dSRob Clark #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
1200cf6c71dSRob Clark
12152260ae4SRob Clark #define REG_HDMI_INFOFRAME_CTRL1 0x00000030
12252260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
12352260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)12452260ae4SRob Clark static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
12552260ae4SRob Clark {
12652260ae4SRob Clark return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
12752260ae4SRob Clark }
12852260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
12952260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8
HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)13052260ae4SRob Clark static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
13152260ae4SRob Clark {
13252260ae4SRob Clark return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK;
13352260ae4SRob Clark }
13452260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
13552260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16
HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)13652260ae4SRob Clark static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
13752260ae4SRob Clark {
13852260ae4SRob Clark return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK;
13952260ae4SRob Clark }
14052260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
14152260ae4SRob Clark #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24
HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)14252260ae4SRob Clark static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
14352260ae4SRob Clark {
14452260ae4SRob Clark return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK;
14552260ae4SRob Clark }
14652260ae4SRob Clark
1470cf6c71dSRob Clark #define REG_HDMI_GEN_PKT_CTRL 0x00000034
1480cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
1490cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
1500cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c
1510cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2
HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)1520cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
1530cf6c71dSRob Clark {
1540cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK;
1550cf6c71dSRob Clark }
1560cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010
1570cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020
1580cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000
1590cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16
HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)1600cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
1610cf6c71dSRob Clark {
1620cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK;
1630cf6c71dSRob Clark }
1640cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000
1650cf6c71dSRob Clark #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24
HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)1660cf6c71dSRob Clark static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
1670cf6c71dSRob Clark {
1680cf6c71dSRob Clark return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK;
1690cf6c71dSRob Clark }
1700cf6c71dSRob Clark
1710cf6c71dSRob Clark #define REG_HDMI_GC 0x00000040
1720cf6c71dSRob Clark #define HDMI_GC_MUTE 0x00000001
1730cf6c71dSRob Clark
1740cf6c71dSRob Clark #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044
1750cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001
1760cf6c71dSRob Clark #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002
1770cf6c71dSRob Clark
REG_HDMI_AVI_INFO(uint32_t i0)1780cf6c71dSRob Clark static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
1790cf6c71dSRob Clark
1800cf6c71dSRob Clark #define REG_HDMI_GENERIC0_HDR 0x00000084
1810cf6c71dSRob Clark
REG_HDMI_GENERIC0(uint32_t i0)1820cf6c71dSRob Clark static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
1830cf6c71dSRob Clark
1840cf6c71dSRob Clark #define REG_HDMI_GENERIC1_HDR 0x000000a4
1850cf6c71dSRob Clark
REG_HDMI_GENERIC1(uint32_t i0)1860cf6c71dSRob Clark static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
1870cf6c71dSRob Clark
REG_HDMI_ACR(enum hdmi_acr_cts i0)18889301471SRob Clark static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
1890cf6c71dSRob Clark
REG_HDMI_ACR_0(enum hdmi_acr_cts i0)19089301471SRob Clark static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
1910cf6c71dSRob Clark #define HDMI_ACR_0_CTS__MASK 0xfffff000
1920cf6c71dSRob Clark #define HDMI_ACR_0_CTS__SHIFT 12
HDMI_ACR_0_CTS(uint32_t val)1930cf6c71dSRob Clark static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
1940cf6c71dSRob Clark {
1950cf6c71dSRob Clark return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
1960cf6c71dSRob Clark }
1970cf6c71dSRob Clark
REG_HDMI_ACR_1(enum hdmi_acr_cts i0)19889301471SRob Clark static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
1990cf6c71dSRob Clark #define HDMI_ACR_1_N__MASK 0xffffffff
2000cf6c71dSRob Clark #define HDMI_ACR_1_N__SHIFT 0
HDMI_ACR_1_N(uint32_t val)2010cf6c71dSRob Clark static inline uint32_t HDMI_ACR_1_N(uint32_t val)
2020cf6c71dSRob Clark {
2030cf6c71dSRob Clark return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK;
2040cf6c71dSRob Clark }
2050cf6c71dSRob Clark
2060cf6c71dSRob Clark #define REG_HDMI_AUDIO_INFO0 0x000000e4
2070cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff
2080cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0
HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)2090cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
2100cf6c71dSRob Clark {
2110cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK;
2120cf6c71dSRob Clark }
2130cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700
2140cf6c71dSRob Clark #define HDMI_AUDIO_INFO0_CC__SHIFT 8
HDMI_AUDIO_INFO0_CC(uint32_t val)2150cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
2160cf6c71dSRob Clark {
2170cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK;
2180cf6c71dSRob Clark }
2190cf6c71dSRob Clark
2200cf6c71dSRob Clark #define REG_HDMI_AUDIO_INFO1 0x000000e8
2210cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff
2220cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_CA__SHIFT 0
HDMI_AUDIO_INFO1_CA(uint32_t val)2230cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
2240cf6c71dSRob Clark {
2250cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK;
2260cf6c71dSRob Clark }
2270cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800
2280cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_LSV__SHIFT 11
HDMI_AUDIO_INFO1_LSV(uint32_t val)2290cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
2300cf6c71dSRob Clark {
2310cf6c71dSRob Clark return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK;
2320cf6c71dSRob Clark }
2330cf6c71dSRob Clark #define HDMI_AUDIO_INFO1_DM_INH 0x00008000
2340cf6c71dSRob Clark
2350cf6c71dSRob Clark #define REG_HDMI_HDCP_CTRL 0x00000110
2360cf6c71dSRob Clark #define HDMI_HDCP_CTRL_ENABLE 0x00000001
2370cf6c71dSRob Clark #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100
2380cf6c71dSRob Clark
2398a264743SRob Clark #define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114
2408a264743SRob Clark #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004
2418a264743SRob Clark
2420cf6c71dSRob Clark #define REG_HDMI_HDCP_INT_CTRL 0x00000118
2438a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001
2448a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002
2458a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004
2468a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010
2478a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020
2488a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040
2498a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080
2508a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100
2518a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200
2528a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400
2538a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000
2548a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000
2558a264743SRob Clark #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000
2560cf6c71dSRob Clark
2570cf6c71dSRob Clark #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c
2580cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100
2590cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200
2608a264743SRob Clark #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000
2618a264743SRob Clark #define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000
2620cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000
2630cf6c71dSRob Clark #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28
HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)2640cf6c71dSRob Clark static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
2650cf6c71dSRob Clark {
2660cf6c71dSRob Clark return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
2670cf6c71dSRob Clark }
2680cf6c71dSRob Clark
2698a264743SRob Clark #define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120
2708a264743SRob Clark #define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001
2718a264743SRob Clark
2728a264743SRob Clark #define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124
2738a264743SRob Clark #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001
2748a264743SRob Clark
2758a264743SRob Clark #define REG_HDMI_HDCP_DDC_STATUS 0x00000128
2768a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010
2778a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400
2788a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000
2798a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000
2808a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000
2818a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000
2828a264743SRob Clark #define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000
2838a264743SRob Clark
2848a264743SRob Clark #define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c
2858a264743SRob Clark
2868a264743SRob Clark #define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c
2878a264743SRob Clark
2880cf6c71dSRob Clark #define REG_HDMI_HDCP_RESET 0x00000130
2890cf6c71dSRob Clark #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
2900cf6c71dSRob Clark
2918a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134
2928a264743SRob Clark
2938a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138
2948a264743SRob Clark
2958a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c
2968a264743SRob Clark
2978a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140
2988a264743SRob Clark
2998a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144
3008a264743SRob Clark
3018a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148
3028a264743SRob Clark
3038a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c
3048a264743SRob Clark
3058a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150
3068a264743SRob Clark
3078a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154
3088a264743SRob Clark
3098a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158
3108a264743SRob Clark
3118a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c
3128a264743SRob Clark
3138a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160
3148a264743SRob Clark
3158a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164
3168a264743SRob Clark
3178a264743SRob Clark #define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168
3188a264743SRob Clark
319facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO0 0x0000016c
320facb4f4eSRob Clark
321facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO1 0x00000170
322facb4f4eSRob Clark
323facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO2 0x00000174
324facb4f4eSRob Clark
325facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO3 0x00000178
326facb4f4eSRob Clark
327facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO4 0x0000017c
328facb4f4eSRob Clark
329facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO5 0x00000180
330facb4f4eSRob Clark
331facb4f4eSRob Clark #define REG_HDMI_VENSPEC_INFO6 0x00000184
332facb4f4eSRob Clark
3330cf6c71dSRob Clark #define REG_HDMI_AUDIO_CFG 0x000001d0
3340cf6c71dSRob Clark #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
3350cf6c71dSRob Clark #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
3360cf6c71dSRob Clark #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4
HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)3370cf6c71dSRob Clark static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
3380cf6c71dSRob Clark {
3390cf6c71dSRob Clark return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
3400cf6c71dSRob Clark }
3410cf6c71dSRob Clark
3420cf6c71dSRob Clark #define REG_HDMI_USEC_REFTIMER 0x00000208
3430cf6c71dSRob Clark
3440cf6c71dSRob Clark #define REG_HDMI_DDC_CTRL 0x0000020c
3450cf6c71dSRob Clark #define HDMI_DDC_CTRL_GO 0x00000001
3460cf6c71dSRob Clark #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002
3470cf6c71dSRob Clark #define HDMI_DDC_CTRL_SEND_RESET 0x00000004
3480cf6c71dSRob Clark #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008
3490cf6c71dSRob Clark #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000
3500cf6c71dSRob Clark #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20
HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)3510cf6c71dSRob Clark static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
3520cf6c71dSRob Clark {
3530cf6c71dSRob Clark return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
3540cf6c71dSRob Clark }
3550cf6c71dSRob Clark
356facb4f4eSRob Clark #define REG_HDMI_DDC_ARBITRATION 0x00000210
357facb4f4eSRob Clark #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
358facb4f4eSRob Clark
3590cf6c71dSRob Clark #define REG_HDMI_DDC_INT_CTRL 0x00000214
3600cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
3610cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
3620cf6c71dSRob Clark #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004
3630cf6c71dSRob Clark
3640cf6c71dSRob Clark #define REG_HDMI_DDC_SW_STATUS 0x00000218
3650cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK0 0x00001000
3660cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK1 0x00002000
3670cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK2 0x00004000
3680cf6c71dSRob Clark #define HDMI_DDC_SW_STATUS_NACK3 0x00008000
3690cf6c71dSRob Clark
3700cf6c71dSRob Clark #define REG_HDMI_DDC_HW_STATUS 0x0000021c
3718a264743SRob Clark #define HDMI_DDC_HW_STATUS_DONE 0x00000008
3720cf6c71dSRob Clark
3730cf6c71dSRob Clark #define REG_HDMI_DDC_SPEED 0x00000220
3740cf6c71dSRob Clark #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003
3750cf6c71dSRob Clark #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0
HDMI_DDC_SPEED_THRESHOLD(uint32_t val)3760cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
3770cf6c71dSRob Clark {
3780cf6c71dSRob Clark return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK;
3790cf6c71dSRob Clark }
3800cf6c71dSRob Clark #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000
3810cf6c71dSRob Clark #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16
HDMI_DDC_SPEED_PRESCALE(uint32_t val)3820cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
3830cf6c71dSRob Clark {
3840cf6c71dSRob Clark return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK;
3850cf6c71dSRob Clark }
3860cf6c71dSRob Clark
3870cf6c71dSRob Clark #define REG_HDMI_DDC_SETUP 0x00000224
3880cf6c71dSRob Clark #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000
3890cf6c71dSRob Clark #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24
HDMI_DDC_SETUP_TIMEOUT(uint32_t val)3900cf6c71dSRob Clark static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
3910cf6c71dSRob Clark {
3920cf6c71dSRob Clark return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK;
3930cf6c71dSRob Clark }
3940cf6c71dSRob Clark
REG_HDMI_I2C_TRANSACTION(uint32_t i0)3950cf6c71dSRob Clark static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
3960cf6c71dSRob Clark
REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0)3970cf6c71dSRob Clark static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }
3980cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001
3990cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0
HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)4000cf6c71dSRob Clark static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
4010cf6c71dSRob Clark {
4020cf6c71dSRob Clark return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK;
4030cf6c71dSRob Clark }
4040cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100
4050cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_START 0x00001000
4060cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000
4070cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000
4080cf6c71dSRob Clark #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16
HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)4090cf6c71dSRob Clark static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
4100cf6c71dSRob Clark {
4110cf6c71dSRob Clark return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK;
4120cf6c71dSRob Clark }
4130cf6c71dSRob Clark
4140cf6c71dSRob Clark #define REG_HDMI_DDC_DATA 0x00000238
4150cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001
4160cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA_RW__SHIFT 0
HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)4170cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
4180cf6c71dSRob Clark {
4190cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK;
4200cf6c71dSRob Clark }
4210cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00
4220cf6c71dSRob Clark #define HDMI_DDC_DATA_DATA__SHIFT 8
HDMI_DDC_DATA_DATA(uint32_t val)4230cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
4240cf6c71dSRob Clark {
4250cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK;
4260cf6c71dSRob Clark }
4270cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000
4280cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX__SHIFT 16
HDMI_DDC_DATA_INDEX(uint32_t val)4290cf6c71dSRob Clark static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
4300cf6c71dSRob Clark {
4310cf6c71dSRob Clark return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK;
4320cf6c71dSRob Clark }
4330cf6c71dSRob Clark #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000
4340cf6c71dSRob Clark
4358a264743SRob Clark #define REG_HDMI_HDCP_SHA_CTRL 0x0000023c
4368a264743SRob Clark
4378a264743SRob Clark #define REG_HDMI_HDCP_SHA_STATUS 0x00000240
4388a264743SRob Clark #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001
4398a264743SRob Clark #define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010
4408a264743SRob Clark
4418a264743SRob Clark #define REG_HDMI_HDCP_SHA_DATA 0x00000244
4428a264743SRob Clark #define HDMI_HDCP_SHA_DATA_DONE 0x00000001
4438a264743SRob Clark
4440cf6c71dSRob Clark #define REG_HDMI_HPD_INT_STATUS 0x00000250
4450cf6c71dSRob Clark #define HDMI_HPD_INT_STATUS_INT 0x00000001
4460cf6c71dSRob Clark #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002
4470cf6c71dSRob Clark
4480cf6c71dSRob Clark #define REG_HDMI_HPD_INT_CTRL 0x00000254
4490cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001
4500cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002
4510cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004
4520cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010
4530cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020
4540cf6c71dSRob Clark #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200
4550cf6c71dSRob Clark
4560cf6c71dSRob Clark #define REG_HDMI_HPD_CTRL 0x00000258
4570cf6c71dSRob Clark #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff
4580cf6c71dSRob Clark #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0
HDMI_HPD_CTRL_TIMEOUT(uint32_t val)4590cf6c71dSRob Clark static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
4600cf6c71dSRob Clark {
4610cf6c71dSRob Clark return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK;
4620cf6c71dSRob Clark }
4630cf6c71dSRob Clark #define HDMI_HPD_CTRL_ENABLE 0x10000000
4640cf6c71dSRob Clark
4650cf6c71dSRob Clark #define REG_HDMI_DDC_REF 0x0000027c
4660cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000
4670cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff
4680cf6c71dSRob Clark #define HDMI_DDC_REF_REFTIMER__SHIFT 0
HDMI_DDC_REF_REFTIMER(uint32_t val)4690cf6c71dSRob Clark static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
4700cf6c71dSRob Clark {
4710cf6c71dSRob Clark return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
4720cf6c71dSRob Clark }
4730cf6c71dSRob Clark
4748a264743SRob Clark #define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284
4758a264743SRob Clark
4768a264743SRob Clark #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288
4778a264743SRob Clark
4782d3584ebSRob Clark #define REG_HDMI_CEC_CTRL 0x0000028c
4792d3584ebSRob Clark
4802d3584ebSRob Clark #define REG_HDMI_CEC_WR_DATA 0x00000290
4812d3584ebSRob Clark
4822d3584ebSRob Clark #define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294
4832d3584ebSRob Clark
484facb4f4eSRob Clark #define REG_HDMI_CEC_STATUS 0x00000298
485facb4f4eSRob Clark
486facb4f4eSRob Clark #define REG_HDMI_CEC_INT 0x0000029c
487facb4f4eSRob Clark
488facb4f4eSRob Clark #define REG_HDMI_CEC_ADDR 0x000002a0
489facb4f4eSRob Clark
490facb4f4eSRob Clark #define REG_HDMI_CEC_TIME 0x000002a4
491facb4f4eSRob Clark
492facb4f4eSRob Clark #define REG_HDMI_CEC_REFTIMER 0x000002a8
493facb4f4eSRob Clark
494facb4f4eSRob Clark #define REG_HDMI_CEC_RD_DATA 0x000002ac
495facb4f4eSRob Clark
496facb4f4eSRob Clark #define REG_HDMI_CEC_RD_FILTER 0x000002b0
497facb4f4eSRob Clark
4980cf6c71dSRob Clark #define REG_HDMI_ACTIVE_HSYNC 0x000002b4
49952260ae4SRob Clark #define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
5000cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_START__SHIFT 0
HDMI_ACTIVE_HSYNC_START(uint32_t val)5010cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
5020cf6c71dSRob Clark {
5030cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;
5040cf6c71dSRob Clark }
5050cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000
5060cf6c71dSRob Clark #define HDMI_ACTIVE_HSYNC_END__SHIFT 16
HDMI_ACTIVE_HSYNC_END(uint32_t val)5070cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
5080cf6c71dSRob Clark {
5090cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK;
5100cf6c71dSRob Clark }
5110cf6c71dSRob Clark
5120cf6c71dSRob Clark #define REG_HDMI_ACTIVE_VSYNC 0x000002b8
51352260ae4SRob Clark #define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
5140cf6c71dSRob Clark #define HDMI_ACTIVE_VSYNC_START__SHIFT 0
HDMI_ACTIVE_VSYNC_START(uint32_t val)5150cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
5160cf6c71dSRob Clark {
5170cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
5180cf6c71dSRob Clark }
51952260ae4SRob Clark #define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
5200cf6c71dSRob Clark #define HDMI_ACTIVE_VSYNC_END__SHIFT 16
HDMI_ACTIVE_VSYNC_END(uint32_t val)5210cf6c71dSRob Clark static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
5220cf6c71dSRob Clark {
5230cf6c71dSRob Clark return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK;
5240cf6c71dSRob Clark }
5250cf6c71dSRob Clark
5260cf6c71dSRob Clark #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
52752260ae4SRob Clark #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
5280cf6c71dSRob Clark #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)5290cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
5300cf6c71dSRob Clark {
5310cf6c71dSRob Clark return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
5320cf6c71dSRob Clark }
53352260ae4SRob Clark #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
5340cf6c71dSRob Clark #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)5350cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
5360cf6c71dSRob Clark {
5370cf6c71dSRob Clark return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK;
5380cf6c71dSRob Clark }
5390cf6c71dSRob Clark
5400cf6c71dSRob Clark #define REG_HDMI_TOTAL 0x000002c0
54152260ae4SRob Clark #define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
5420cf6c71dSRob Clark #define HDMI_TOTAL_H_TOTAL__SHIFT 0
HDMI_TOTAL_H_TOTAL(uint32_t val)5430cf6c71dSRob Clark static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
5440cf6c71dSRob Clark {
5450cf6c71dSRob Clark return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
5460cf6c71dSRob Clark }
54752260ae4SRob Clark #define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
5480cf6c71dSRob Clark #define HDMI_TOTAL_V_TOTAL__SHIFT 16
HDMI_TOTAL_V_TOTAL(uint32_t val)5490cf6c71dSRob Clark static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
5500cf6c71dSRob Clark {
5510cf6c71dSRob Clark return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK;
5520cf6c71dSRob Clark }
5530cf6c71dSRob Clark
5540cf6c71dSRob Clark #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
55552260ae4SRob Clark #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
5560cf6c71dSRob Clark #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)5570cf6c71dSRob Clark static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
5580cf6c71dSRob Clark {
5590cf6c71dSRob Clark return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK;
5600cf6c71dSRob Clark }
5610cf6c71dSRob Clark
5620cf6c71dSRob Clark #define REG_HDMI_FRAME_CTRL 0x000002c8
5630cf6c71dSRob Clark #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000
5640cf6c71dSRob Clark #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000
5650cf6c71dSRob Clark #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
5660cf6c71dSRob Clark #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
5670cf6c71dSRob Clark
568facb4f4eSRob Clark #define REG_HDMI_AUD_INT 0x000002cc
569facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
570facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
571facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
572facb4f4eSRob Clark #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
573facb4f4eSRob Clark
5740cf6c71dSRob Clark #define REG_HDMI_PHY_CTRL 0x000002d4
5750cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
5760cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
5770cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET 0x00000004
5780cf6c71dSRob Clark #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
5790cf6c71dSRob Clark
580facb4f4eSRob Clark #define REG_HDMI_CEC_WR_RANGE 0x000002dc
581facb4f4eSRob Clark
582facb4f4eSRob Clark #define REG_HDMI_CEC_RD_RANGE 0x000002e0
583facb4f4eSRob Clark
584facb4f4eSRob Clark #define REG_HDMI_VERSION 0x000002e4
585facb4f4eSRob Clark
586facb4f4eSRob Clark #define REG_HDMI_CEC_COMPL_CTL 0x00000360
587facb4f4eSRob Clark
588facb4f4eSRob Clark #define REG_HDMI_CEC_RD_START_RANGE 0x00000364
589facb4f4eSRob Clark
590facb4f4eSRob Clark #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
591facb4f4eSRob Clark
592facb4f4eSRob Clark #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
593facb4f4eSRob Clark
594facb4f4eSRob Clark #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
5950cf6c71dSRob Clark
596568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG0 0x00000000
5970cf6c71dSRob Clark #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
5980cf6c71dSRob Clark #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2
HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)5990cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
6000cf6c71dSRob Clark {
6010cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
6020cf6c71dSRob Clark }
6030cf6c71dSRob Clark
604568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG1 0x00000004
6050cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0
6060cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4
HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)6070cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
6080cf6c71dSRob Clark {
6090cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK;
6100cf6c71dSRob Clark }
6110cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f
6120cf6c71dSRob Clark #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)6130cf6c71dSRob Clark static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
6140cf6c71dSRob Clark {
6150cf6c71dSRob Clark return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
6160cf6c71dSRob Clark }
6170cf6c71dSRob Clark
618568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG2 0x00000008
6190cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001
6200cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002
6210cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
6220cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008
6230cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010
6240cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020
6250cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040
6260cf6c71dSRob Clark #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080
6270cf6c71dSRob Clark
628568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG3 0x0000000c
6290cf6c71dSRob Clark #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001
6300cf6c71dSRob Clark
631568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG4 0x00000010
6320cf6c71dSRob Clark
633568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG5 0x00000014
6340cf6c71dSRob Clark
635568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG6 0x00000018
6360cf6c71dSRob Clark
637568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG7 0x0000001c
6380cf6c71dSRob Clark
639568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG8 0x00000020
6400cf6c71dSRob Clark
641568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG9 0x00000024
6420cf6c71dSRob Clark
643568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG10 0x00000028
6440cf6c71dSRob Clark
645568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG11 0x0000002c
6460cf6c71dSRob Clark
647568be320SArchit Taneja #define REG_HDMI_8x60_PHY_REG12 0x00000030
6480cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001
6490cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002
6500cf6c71dSRob Clark #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010
6510cf6c71dSRob Clark
652568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG0 0x00000000
6530cf6c71dSRob Clark
654568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG1 0x00000004
6550cf6c71dSRob Clark
656568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG2 0x00000008
6570cf6c71dSRob Clark
658568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG3 0x0000000c
6590cf6c71dSRob Clark
660568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG4 0x00000010
6610cf6c71dSRob Clark
662568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG5 0x00000014
6630cf6c71dSRob Clark
664568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG6 0x00000018
6650cf6c71dSRob Clark
666568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG7 0x0000001c
6670cf6c71dSRob Clark
668568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG8 0x00000020
6690cf6c71dSRob Clark
670568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG9 0x00000024
6710cf6c71dSRob Clark
672568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG10 0x00000028
6730cf6c71dSRob Clark
674568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG11 0x0000002c
6750cf6c71dSRob Clark
676568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG12 0x00000030
67789301471SRob Clark #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
67889301471SRob Clark #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
67989301471SRob Clark
680568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034
68189301471SRob Clark
682568be320SArchit Taneja #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038
68389301471SRob Clark
684568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c
68589301471SRob Clark
686568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG13 0x00000040
68789301471SRob Clark
688568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG14 0x00000044
68989301471SRob Clark
690568be320SArchit Taneja #define REG_HDMI_8960_PHY_REG15 0x00000048
69189301471SRob Clark
692568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000
69389301471SRob Clark
694568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004
69589301471SRob Clark
696568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008
69789301471SRob Clark
698568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c
69989301471SRob Clark
700568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010
70189301471SRob Clark
702568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014
70389301471SRob Clark
704568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018
70589301471SRob Clark #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
70689301471SRob Clark #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
70789301471SRob Clark
708568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c
70989301471SRob Clark
710568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020
71189301471SRob Clark
712568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024
71389301471SRob Clark
714568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028
71589301471SRob Clark
716568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c
71789301471SRob Clark
718568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030
71989301471SRob Clark
720568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034
72189301471SRob Clark
722568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038
72389301471SRob Clark
724568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c
72589301471SRob Clark
726568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040
72789301471SRob Clark
728568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044
72989301471SRob Clark
730568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048
73189301471SRob Clark
732568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c
73389301471SRob Clark
734568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050
73589301471SRob Clark
736568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054
73789301471SRob Clark
738568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058
73989301471SRob Clark
740568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c
74189301471SRob Clark
742568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060
74389301471SRob Clark
744568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064
74589301471SRob Clark
746568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068
74789301471SRob Clark
748568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c
74989301471SRob Clark
750568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070
75189301471SRob Clark
752568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074
75389301471SRob Clark
754568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078
75589301471SRob Clark
756568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c
75789301471SRob Clark
758568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080
75989301471SRob Clark
760568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084
76189301471SRob Clark
762568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088
76389301471SRob Clark
764568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c
76589301471SRob Clark
766568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090
76789301471SRob Clark
768568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094
76989301471SRob Clark
770568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098
77189301471SRob Clark #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
77289301471SRob Clark
773568be320SArchit Taneja #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c
7740cf6c71dSRob Clark
775facb4f4eSRob Clark #define REG_HDMI_8x74_ANA_CFG0 0x00000000
776facb4f4eSRob Clark
777facb4f4eSRob Clark #define REG_HDMI_8x74_ANA_CFG1 0x00000004
778facb4f4eSRob Clark
779*f73343faSRob Clark #define REG_HDMI_8x74_ANA_CFG2 0x00000008
780*f73343faSRob Clark
781*f73343faSRob Clark #define REG_HDMI_8x74_ANA_CFG3 0x0000000c
782*f73343faSRob Clark
783facb4f4eSRob Clark #define REG_HDMI_8x74_PD_CTRL0 0x00000010
784facb4f4eSRob Clark
785facb4f4eSRob Clark #define REG_HDMI_8x74_PD_CTRL1 0x00000014
786facb4f4eSRob Clark
787*f73343faSRob Clark #define REG_HDMI_8x74_GLB_CFG 0x00000018
788*f73343faSRob Clark
789*f73343faSRob Clark #define REG_HDMI_8x74_DCC_CFG0 0x0000001c
790*f73343faSRob Clark
791*f73343faSRob Clark #define REG_HDMI_8x74_DCC_CFG1 0x00000020
792*f73343faSRob Clark
793*f73343faSRob Clark #define REG_HDMI_8x74_TXCAL_CFG0 0x00000024
794*f73343faSRob Clark
795*f73343faSRob Clark #define REG_HDMI_8x74_TXCAL_CFG1 0x00000028
796*f73343faSRob Clark
797*f73343faSRob Clark #define REG_HDMI_8x74_TXCAL_CFG2 0x0000002c
798*f73343faSRob Clark
799*f73343faSRob Clark #define REG_HDMI_8x74_TXCAL_CFG3 0x00000030
800*f73343faSRob Clark
801facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_CFG0 0x00000034
802facb4f4eSRob Clark
803facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN0 0x0000003c
804facb4f4eSRob Clark
805facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN1 0x00000040
806facb4f4eSRob Clark
807facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN2 0x00000044
808facb4f4eSRob Clark
809facb4f4eSRob Clark #define REG_HDMI_8x74_BIST_PATN3 0x00000048
810facb4f4eSRob Clark
811*f73343faSRob Clark #define REG_HDMI_8x74_STATUS 0x0000005c
812*f73343faSRob Clark
813af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
814af6cb4c1SRob Clark
815af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
816af6cb4c1SRob Clark
817af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
818af6cb4c1SRob Clark
819af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
820af6cb4c1SRob Clark
821af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
822af6cb4c1SRob Clark
823af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
824af6cb4c1SRob Clark
825af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
826af6cb4c1SRob Clark
827af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
828af6cb4c1SRob Clark
829af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
830af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
831af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
832af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
833af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
834af6cb4c1SRob Clark
835af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
836af6cb4c1SRob Clark
837af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
838af6cb4c1SRob Clark
839af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
840af6cb4c1SRob Clark
841af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
842af6cb4c1SRob Clark
843af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
844af6cb4c1SRob Clark
845af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
846af6cb4c1SRob Clark
847af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
848af6cb4c1SRob Clark
849af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
850af6cb4c1SRob Clark
851af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
852af6cb4c1SRob Clark
853af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
854af6cb4c1SRob Clark
855af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
856af6cb4c1SRob Clark
857af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
858af6cb4c1SRob Clark
859af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
860af6cb4c1SRob Clark
861af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
862af6cb4c1SRob Clark
863af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
864af6cb4c1SRob Clark
865af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
866af6cb4c1SRob Clark
867af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
868af6cb4c1SRob Clark
869af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
870af6cb4c1SRob Clark #define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
871af6cb4c1SRob Clark
872af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
873af6cb4c1SRob Clark
874af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
875af6cb4c1SRob Clark
876af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
877af6cb4c1SRob Clark
878af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
879af6cb4c1SRob Clark
880af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
881af6cb4c1SRob Clark
882af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
883af6cb4c1SRob Clark
884af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
885af6cb4c1SRob Clark
886af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
887af6cb4c1SRob Clark
888af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
889af6cb4c1SRob Clark
890af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
891af6cb4c1SRob Clark
892af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
893af6cb4c1SRob Clark
894af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
895af6cb4c1SRob Clark
896af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
897af6cb4c1SRob Clark
898af6cb4c1SRob Clark #define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
899af6cb4c1SRob Clark
900*f73343faSRob Clark #define REG_HDMI_28nm_PHY_PLL_STATUS 0x000000c0
901*f73343faSRob Clark
902e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_CFG 0x00000000
903e9a2ce13SArchit Taneja
904e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PD_CTL 0x00000004
905e9a2ce13SArchit Taneja
906e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MODE 0x00000008
907e9a2ce13SArchit Taneja
908e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c
909e9a2ce13SArchit Taneja
910e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010
911e9a2ce13SArchit Taneja
912e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014
913e9a2ce13SArchit Taneja
914e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018
915e9a2ce13SArchit Taneja
916e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c
917e9a2ce13SArchit Taneja
918e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020
919e9a2ce13SArchit Taneja
920e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024
921e9a2ce13SArchit Taneja
922e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028
923e9a2ce13SArchit Taneja
924e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c
925e9a2ce13SArchit Taneja
926e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030
927e9a2ce13SArchit Taneja
928e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034
929e9a2ce13SArchit Taneja
930e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038
931e9a2ce13SArchit Taneja
932e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c
933e9a2ce13SArchit Taneja
934e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040
935e9a2ce13SArchit Taneja
936e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044
937e9a2ce13SArchit Taneja
938e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048
939e9a2ce13SArchit Taneja
940e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c
941e9a2ce13SArchit Taneja
942e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050
943e9a2ce13SArchit Taneja
944e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054
945e9a2ce13SArchit Taneja
946e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_CLOCK 0x00000058
947e9a2ce13SArchit Taneja
948e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISC1 0x0000005c
949e9a2ce13SArchit Taneja
950e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISC2 0x00000060
951e9a2ce13SArchit Taneja
952e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064
953e9a2ce13SArchit Taneja
954e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068
955e9a2ce13SArchit Taneja
956e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c
957e9a2ce13SArchit Taneja
958e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070
959e9a2ce13SArchit Taneja
960e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074
961e9a2ce13SArchit Taneja
962e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078
963e9a2ce13SArchit Taneja
964e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c
965e9a2ce13SArchit Taneja
966e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080
967e9a2ce13SArchit Taneja
968e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084
969e9a2ce13SArchit Taneja
970e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088
971e9a2ce13SArchit Taneja
972e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c
973e9a2ce13SArchit Taneja
974e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090
975e9a2ce13SArchit Taneja
976e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094
977e9a2ce13SArchit Taneja
978e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098
979e9a2ce13SArchit Taneja
980e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_STATUS 0x0000009c
981e9a2ce13SArchit Taneja
982e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0
983e9a2ce13SArchit Taneja
984e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4
985e9a2ce13SArchit Taneja
986e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8
987e9a2ce13SArchit Taneja
988e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac
989e9a2ce13SArchit Taneja
990e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0
991e9a2ce13SArchit Taneja
992e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4
993e9a2ce13SArchit Taneja
994e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8
995e9a2ce13SArchit Taneja
996e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc
997e9a2ce13SArchit Taneja
998e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0
999e9a2ce13SArchit Taneja
1000e9a2ce13SArchit Taneja #define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4
1001e9a2ce13SArchit Taneja
1002e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000
1003e9a2ce13SArchit Taneja
1004e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004
1005e9a2ce13SArchit Taneja
1006e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008
1007e9a2ce13SArchit Taneja
1008e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c
1009e9a2ce13SArchit Taneja
1010e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010
1011e9a2ce13SArchit Taneja
1012e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014
1013e9a2ce13SArchit Taneja
1014e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018
1015e9a2ce13SArchit Taneja
1016e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c
1017e9a2ce13SArchit Taneja
1018e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020
1019e9a2ce13SArchit Taneja
1020e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024
1021e9a2ce13SArchit Taneja
1022e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028
1023e9a2ce13SArchit Taneja
1024e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c
1025e9a2ce13SArchit Taneja
1026e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030
1027e9a2ce13SArchit Taneja
1028e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034
1029e9a2ce13SArchit Taneja
1030e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038
1031e9a2ce13SArchit Taneja
1032e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c
1033e9a2ce13SArchit Taneja
1034e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040
1035e9a2ce13SArchit Taneja
1036e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044
1037e9a2ce13SArchit Taneja
1038e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048
1039e9a2ce13SArchit Taneja
1040e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c
1041e9a2ce13SArchit Taneja
1042e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050
1043e9a2ce13SArchit Taneja
1044e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054
1045e9a2ce13SArchit Taneja
1046e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058
1047e9a2ce13SArchit Taneja
1048e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c
1049e9a2ce13SArchit Taneja
1050e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060
1051e9a2ce13SArchit Taneja
1052e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064
1053e9a2ce13SArchit Taneja
1054e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064
1055e9a2ce13SArchit Taneja
1056e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068
1057e9a2ce13SArchit Taneja
1058e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068
1059e9a2ce13SArchit Taneja
1060e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c
1061e9a2ce13SArchit Taneja
1062e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c
1063e9a2ce13SArchit Taneja
1064e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070
1065e9a2ce13SArchit Taneja
1066e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074
1067e9a2ce13SArchit Taneja
1068e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078
1069e9a2ce13SArchit Taneja
1070e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c
1071e9a2ce13SArchit Taneja
1072e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080
1073e9a2ce13SArchit Taneja
1074e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080
1075e9a2ce13SArchit Taneja
1076e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084
1077e9a2ce13SArchit Taneja
1078e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088
1079e9a2ce13SArchit Taneja
1080e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c
1081e9a2ce13SArchit Taneja
1082e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c
1083e9a2ce13SArchit Taneja
1084e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090
1085e9a2ce13SArchit Taneja
1086e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094
1087e9a2ce13SArchit Taneja
1088e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098
1089e9a2ce13SArchit Taneja
1090e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098
1091e9a2ce13SArchit Taneja
1092e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c
1093e9a2ce13SArchit Taneja
1094e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0
1095e9a2ce13SArchit Taneja
1096e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4
1097e9a2ce13SArchit Taneja
1098e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8
1099e9a2ce13SArchit Taneja
1100e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8
1101e9a2ce13SArchit Taneja
1102e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac
1103e9a2ce13SArchit Taneja
1104e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0
1105e9a2ce13SArchit Taneja
1106e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4
1107e9a2ce13SArchit Taneja
1108e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8
1109e9a2ce13SArchit Taneja
1110e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc
1111e9a2ce13SArchit Taneja
1112e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0
1113e9a2ce13SArchit Taneja
1114e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4
1115e9a2ce13SArchit Taneja
1116e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8
1117e9a2ce13SArchit Taneja
1118e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc
1119e9a2ce13SArchit Taneja
1120e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0
1121e9a2ce13SArchit Taneja
1122e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4
1123e9a2ce13SArchit Taneja
1124e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8
1125e9a2ce13SArchit Taneja
1126e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8
1127e9a2ce13SArchit Taneja
1128e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc
1129e9a2ce13SArchit Taneja
1130e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0
1131e9a2ce13SArchit Taneja
1132e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4
1133e9a2ce13SArchit Taneja
1134e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8
1135e9a2ce13SArchit Taneja
1136e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec
1137e9a2ce13SArchit Taneja
1138e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0
1139e9a2ce13SArchit Taneja
1140e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4
1141e9a2ce13SArchit Taneja
1142e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4
1143e9a2ce13SArchit Taneja
1144e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8
1145e9a2ce13SArchit Taneja
1146e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8
1147e9a2ce13SArchit Taneja
1148e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc
1149e9a2ce13SArchit Taneja
1150e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc
1151e9a2ce13SArchit Taneja
1152e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100
1153e9a2ce13SArchit Taneja
1154e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104
1155e9a2ce13SArchit Taneja
1156e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108
1157e9a2ce13SArchit Taneja
1158e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c
1159e9a2ce13SArchit Taneja
1160e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110
1161e9a2ce13SArchit Taneja
1162e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114
1163e9a2ce13SArchit Taneja
1164e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118
1165e9a2ce13SArchit Taneja
1166e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118
1167e9a2ce13SArchit Taneja
1168e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c
1169e9a2ce13SArchit Taneja
1170e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c
1171e9a2ce13SArchit Taneja
1172e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120
1173e9a2ce13SArchit Taneja
1174e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124
1175e9a2ce13SArchit Taneja
1176e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128
1177e9a2ce13SArchit Taneja
1178e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c
1179e9a2ce13SArchit Taneja
1180e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130
1181e9a2ce13SArchit Taneja
1182e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134
1183e9a2ce13SArchit Taneja
1184e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138
1185e9a2ce13SArchit Taneja
1186e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c
1187e9a2ce13SArchit Taneja
1188e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c
1189e9a2ce13SArchit Taneja
1190e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140
1191e9a2ce13SArchit Taneja
1192e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140
1193e9a2ce13SArchit Taneja
1194e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144
1195e9a2ce13SArchit Taneja
1196e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148
1197e9a2ce13SArchit Taneja
1198e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c
1199e9a2ce13SArchit Taneja
1200e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150
1201e9a2ce13SArchit Taneja
1202e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154
1203e9a2ce13SArchit Taneja
1204e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158
1205e9a2ce13SArchit Taneja
1206e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c
1207e9a2ce13SArchit Taneja
1208e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160
1209e9a2ce13SArchit Taneja
1210e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164
1211e9a2ce13SArchit Taneja
1212e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168
1213e9a2ce13SArchit Taneja
1214e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c
1215e9a2ce13SArchit Taneja
1216e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170
1217e9a2ce13SArchit Taneja
1218e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174
1219e9a2ce13SArchit Taneja
1220e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178
1221e9a2ce13SArchit Taneja
1222e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c
1223e9a2ce13SArchit Taneja
1224e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180
1225e9a2ce13SArchit Taneja
1226e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184
1227e9a2ce13SArchit Taneja
1228e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188
1229e9a2ce13SArchit Taneja
1230e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c
1231e9a2ce13SArchit Taneja
1232e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190
1233e9a2ce13SArchit Taneja
1234e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194
1235e9a2ce13SArchit Taneja
1236e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198
1237e9a2ce13SArchit Taneja
1238e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c
1239e9a2ce13SArchit Taneja
1240e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0
1241e9a2ce13SArchit Taneja
1242e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4
1243e9a2ce13SArchit Taneja
1244e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8
1245e9a2ce13SArchit Taneja
1246e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac
1247e9a2ce13SArchit Taneja
1248e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0
1249e9a2ce13SArchit Taneja
1250e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4
1251e9a2ce13SArchit Taneja
1252e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8
1253e9a2ce13SArchit Taneja
1254e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc
1255e9a2ce13SArchit Taneja
1256e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0
1257e9a2ce13SArchit Taneja
1258e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4
1259e9a2ce13SArchit Taneja
1260e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000
1261e9a2ce13SArchit Taneja
1262e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004
1263e9a2ce13SArchit Taneja
1264e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008
1265e9a2ce13SArchit Taneja
1266e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c
1267e9a2ce13SArchit Taneja
1268e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010
1269e9a2ce13SArchit Taneja
1270e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014
1271e9a2ce13SArchit Taneja
1272e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018
1273e9a2ce13SArchit Taneja
1274e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c
1275e9a2ce13SArchit Taneja
1276e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020
1277e9a2ce13SArchit Taneja
1278e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024
1279e9a2ce13SArchit Taneja
1280e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028
1281e9a2ce13SArchit Taneja
1282e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c
1283e9a2ce13SArchit Taneja
1284e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030
1285e9a2ce13SArchit Taneja
1286e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034
1287e9a2ce13SArchit Taneja
1288e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038
1289e9a2ce13SArchit Taneja
1290e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c
1291e9a2ce13SArchit Taneja
1292e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040
1293e9a2ce13SArchit Taneja
1294e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044
1295e9a2ce13SArchit Taneja
1296e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048
1297e9a2ce13SArchit Taneja
1298e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c
1299e9a2ce13SArchit Taneja
1300e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050
1301e9a2ce13SArchit Taneja
1302e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054
1303e9a2ce13SArchit Taneja
1304e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058
1305e9a2ce13SArchit Taneja
1306e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c
1307e9a2ce13SArchit Taneja
1308e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060
1309e9a2ce13SArchit Taneja
1310e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064
1311e9a2ce13SArchit Taneja
1312e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068
1313e9a2ce13SArchit Taneja
1314e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c
1315e9a2ce13SArchit Taneja
1316e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070
1317e9a2ce13SArchit Taneja
1318e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074
1319e9a2ce13SArchit Taneja
1320e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078
1321e9a2ce13SArchit Taneja
1322e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c
1323e9a2ce13SArchit Taneja
1324e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080
1325e9a2ce13SArchit Taneja
1326e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084
1327e9a2ce13SArchit Taneja
1328e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088
1329e9a2ce13SArchit Taneja
1330e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c
1331e9a2ce13SArchit Taneja
1332e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090
1333e9a2ce13SArchit Taneja
1334e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094
1335e9a2ce13SArchit Taneja
1336e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098
1337e9a2ce13SArchit Taneja
1338e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c
1339e9a2ce13SArchit Taneja
1340e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0
1341e9a2ce13SArchit Taneja
1342e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4
1343e9a2ce13SArchit Taneja
1344e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8
1345e9a2ce13SArchit Taneja
1346e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac
1347e9a2ce13SArchit Taneja
1348e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0
1349e9a2ce13SArchit Taneja
1350e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4
1351e9a2ce13SArchit Taneja
1352e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8
1353e9a2ce13SArchit Taneja
1354e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc
1355e9a2ce13SArchit Taneja
1356e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0
1357e9a2ce13SArchit Taneja
1358e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4
1359e9a2ce13SArchit Taneja
1360e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8
1361e9a2ce13SArchit Taneja
1362e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc
1363e9a2ce13SArchit Taneja
1364e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0
1365e9a2ce13SArchit Taneja
1366e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4
1367e9a2ce13SArchit Taneja
1368e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8
1369e9a2ce13SArchit Taneja
1370e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc
1371e9a2ce13SArchit Taneja
1372e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0
1373e9a2ce13SArchit Taneja
1374e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4
1375e9a2ce13SArchit Taneja
1376e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8
1377e9a2ce13SArchit Taneja
1378e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec
1379e9a2ce13SArchit Taneja
1380e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0
1381e9a2ce13SArchit Taneja
1382e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4
1383e9a2ce13SArchit Taneja
1384e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8
1385e9a2ce13SArchit Taneja
1386e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc
1387e9a2ce13SArchit Taneja
1388e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100
1389e9a2ce13SArchit Taneja
1390e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104
1391e9a2ce13SArchit Taneja
1392e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108
1393e9a2ce13SArchit Taneja
1394e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c
1395e9a2ce13SArchit Taneja
1396e9a2ce13SArchit Taneja #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110
1397e9a2ce13SArchit Taneja
13980cf6c71dSRob Clark
13990cf6c71dSRob Clark #endif /* HDMI_XML */
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