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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
[all …]
/openbmc/u-boot/arch/riscv/lib/
H A Dsifive_clint.c1 // SPDX-License-Identifier: GPL-2.0+
5 * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
6 * The CLINT block holds memory-mapped control and status registers
30 if (!gd->arch.clint) { \
34 gd->arch.clint = ret; \
42 *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); in riscv_get_time()
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
60 writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_send_ipi()
69 writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_clear_ipi()
/openbmc/linux/drivers/clocksource/
H A Dtimer-clint.c1 // SPDX-License-Identifier: GPL-2.0
5 * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
6 * CLINT MMIO timer device.
9 #define pr_fmt(fmt) "clint: " fmt
18 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <asm/clint.h>
35 /* CLINT manages IPI and Timer for RISC-V M-mode */
133 ce->cpumask = cpumask_of(cpu); in clint_timer_starting_cpu()
149 * via generic IPI-Mux in clint_timer_dying_cpu()
159 evdev->event_handler(evdev); in clint_timer_interrupt()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_TIMER_OF) += timer-of.o
3 obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
4 obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
5 obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
6 obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o
7 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
8 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
9 obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o
10 obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
[all …]
/openbmc/u-boot/arch/riscv/include/asm/
H A Dsyscon.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * System controllers in a RISC-V system
12 * So far only SiFive's Core Local Interruptor (CLINT) is defined.
16 RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
H A Dglobal_data.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 /* Architecture-specific global data */
17 void __iomem *clint; /* clint base address */ member
21 #include <asm-generic/global_data.h>
/openbmc/qemu/docs/system/riscv/
H A Dsifive_u.rst4 SiFive HiFive Unleashed Development Board is the ultimate RISC-V development
5 board featuring the Freedom U540 multi-core RISC-V processor.
8 -----------------
14 * Core Local Interruptor (CLINT)
15 * Platform-Level Interrupt Controller (PLIC)
17 * L2 Loosely Integrated Memory (L2-LIM)
22 * 1 One-Time Programmable (OTP) memory with stored serial number
30 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
32 is also possible to create a 32-bit variant with the same peripherals except
33 that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help
[all …]
H A Dvirt.rst8 real-world hardware.
11 -----------------
16 * Core Local Interruptor (CLINT)
17 * Platform-Level Interrupt Controller (PLIC)
22 * 8 virtio-mmio transport devices
31 ----------------------------------
34 which it passes to the guest, if there is no ``-dtb`` option. This provides
39 If users want to provide their own DTB, they can use the ``-dtb`` option.
42 * The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
43 * The /memory reg size should match QEMU’s selected ram_size via ``-m``
[all …]
H A Dmicrochip-icicle-kit.rst1 Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
5 SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
8 https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
11 https://www.microsemi.com/existing-parts/parts/152514
14 -----------------
16 The ``microchip-icicle-kit`` machine supports the following devices:
20 * Core Level Interruptor (CLINT)
21 * Platform-Level Interrupt Controller (PLIC)
22 * L2 Loosely Integrated Memory (L2-LIM)
30 ------------
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H A Dshakti-c.rst7 Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
11 https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/REA…
13 For more info on the Shakti C-class core, please see:
14 https://c-class.readthedocs.io/en/latest/
17 -----------------
21 * 1 C-class core
22 * Core Level Interruptor (CLINT)
23 * Platform-Level Interrupt Controller (PLIC)
27 ------------
29 The ``shakti_c`` machine can start using the standard -bios
[all …]
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/openbmc/linux/arch/riscv/include/asm/
H A Dclint.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * This lives in the CLINT driver, but is accessed directly by timex.h to avoid
17 * The ISA defines mtime as a 64-bit memory-mapped register that increments at
21 * like "riscv_mtime", to signify that these non-ISA assumptions must hold.
H A Dtimex.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/clint.h>
/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
[all …]
/openbmc/u-boot/doc/
H A DREADME.qemu-riscv1 # SPDX-License-Identifier: GPL-2.0+
5 U-Boot on QEMU's 'virt' machine on RISC-V
8 QEMU for RISC-V supports a special 'virt' machine designed for emulation and
9 virtualization purposes. This document describes how to run U-Boot under it.
10 Both 32-bit 64-bit targets are supported.
12 The QEMU virt machine models a generic RISC-V virtual machine with support for
13 the VirtIO standard networking and block storage devices. It has CLINT, PLIC,
14 16550A UART devices in addition to VirtIO and it also uses device-tree to pass
15 configuration information to guest software. It implements RISC-V privileged
18 Building U-Boot
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/openbmc/u-boot/arch/riscv/
H A DKconfig1 menu "RISC-V architecture"
12 bool "Support ax25-ae350"
22 # board-specific options below
23 source "board/AndesTech/ax25-ae350/Kconfig"
24 source "board/emulation/qemu-riscv/Kconfig"
27 # platform-specific options below
31 # architecture-specific options below
59 U-Boot and its statically defined symbols must lie within a single 2 GiB
60 address range and must lie between absolute addresses -2 GiB and +2 GiB.
65 U-Boot and its statically defined symbols must be within any single 2 GiB
[all …]
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
[all …]
/openbmc/qemu/hw/riscv/
H A Dspike.c2 * QEMU RISC-V Spike Board
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This provides a RISC-V Board with the following devices:
10 * 1) CLINT (Timer and IPI)
26 #include "qemu/error-report.h"
68 fdt = ms->fdt = create_device_tree(&fdt_size); in create_fdt()
74 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); in create_fdt()
75 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); in create_fdt()
76 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
[all …]
H A Dmicrochip_pfsoc.c2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
11 * 0) CLINT (Core Level Interruptor)
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
38 #include "qemu/error-report.h"
59 * See https://github.com/polarfire-soc/hart-software-services
64 /* CLINT timebase frequency */
76 * https://www.microsemi.com/document-portal/doc_download/
77 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
81 * https://www.microsemi.com/document-portal/doc_download/
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H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
11 * 1) CLINT (Core Level Interruptor)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
65 /* CLINT timebase frequency */
99 uint64_t mem_size = ms->ram_size; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
122 "sifive,hifive-unleashed-a00"); in create_fdt()
[all …]
H A Dsifive_e.c2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
9 * 1) CLINT (Core Level Interruptor)
33 #include "qemu/error-report.h"
82 if (machine->ram_size != mc->default_ram_size) { in sifive_e_machine_init()
83 char *sz = size_to_str(mc->default_ram_size); in sifive_e_machine_init()
90 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); in sifive_e_machine_init()
91 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in sifive_e_machine_init()
95 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); in sifive_e_machine_init()
100 if (s->revb) { in sifive_e_machine_init()
116 if (machine->kernel_filename) { in sifive_e_machine_init()
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
29 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
36 * On RISC-V systems local interrupts are masked or unmasked by writing
44 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
49 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
55 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
56 * are defined as (256 + n) and controlled by n-th bit in andes_intc_irq_mask()
59 unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); in andes_intc_irq_mask()
[all …]
/openbmc/openbmc/poky/meta/files/common-licenses/
H A DSMAIL_GPL4 Guy Maor <maor@debian.org>, and are now maintained by Clint Adams
9 found on Debian systems in the file /usr/share/common-licenses/GPL.
19 #ident "@(#)smail:RELEASE-3_2:COPYING,v 1.2 1996/06/14 18:59:10 woods Exp"
99 a) accompany it with the complete corresponding machine-readable
105 shipping charge) a complete machine-readable copy of the
111 allowed only for non-commercial distribution and only if you
130 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. We have not yet
139 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301,
140 USA, or call (617) 542-5942 for details on copylefted material in

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