2  * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
9  * 1) CLINT (Core Level Interruptor)
33 #include "qemu/error-report.h"
82     if (machine->ram_size != mc->default_ram_size) {  in sifive_e_machine_init()
83         char *sz = size_to_str(mc->default_ram_size);  in sifive_e_machine_init()
90     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);  in sifive_e_machine_init()
91     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);  in sifive_e_machine_init()
95         memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);  in sifive_e_machine_init()
100     if (s->revb) {  in sifive_e_machine_init()
116     if (machine->kernel_filename) {  in sifive_e_machine_init()
117         riscv_load_kernel(machine, &s->soc.cpus,  in sifive_e_machine_init()
127     return s->revb;  in sifive_e_machine_get_revb()
134     s->revb = value;  in sifive_e_machine_set_revb()
141     s->revb = false;  in sifive_e_machine_instance_init()
148     mc->desc = "RISC-V Board compatible with SiFive E SDK";  in sifive_e_machine_class_init()
149     mc->init = sifive_e_machine_init;  in sifive_e_machine_class_init()
150     mc->max_cpus = 1;  in sifive_e_machine_class_init()
151     mc->default_cpu_type = SIFIVE_E_CPU;  in sifive_e_machine_class_init()
152     mc->default_ram_id = "riscv.sifive.e.ram";  in sifive_e_machine_class_init()
153     mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;  in sifive_e_machine_class_init()
182     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);  in type_init()
183     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,  in type_init()
185     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);  in type_init()
186     object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,  in type_init()
188     object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon,  in type_init()
199     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,  in sifive_e_soc_realize()
201     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);  in sifive_e_soc_realize()
204     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",  in sifive_e_soc_realize()
207         memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);  in sifive_e_soc_realize()
210     s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,  in sifive_e_soc_realize()
211         (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,  in sifive_e_soc_realize()
222         0, ms->smp.cpus, false);  in sifive_e_soc_realize()
225         RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,  in sifive_e_soc_realize()
232     if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) {  in sifive_e_soc_realize()
237     sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base);  in sifive_e_soc_realize()
241     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {  in sifive_e_soc_realize()
246     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);  in sifive_e_soc_realize()
249     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);  in sifive_e_soc_realize()
253         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,  in sifive_e_soc_realize()
254                            qdev_get_gpio_in(DEVICE(s->plic),  in sifive_e_soc_realize()
257     sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0,  in sifive_e_soc_realize()
258                        qdev_get_gpio_in(DEVICE(s->plic),  in sifive_e_soc_realize()
262         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));  in sifive_e_soc_realize()
268         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));  in sifive_e_soc_realize()
279     memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",  in sifive_e_soc_realize()
282         &s->xip_mem);  in sifive_e_soc_realize()
289     dc->realize = sifive_e_soc_realize;  in sifive_e_soc_class_init()
291     dc->user_creatable = false;  in sifive_e_soc_class_init()