1eb637edbSMichael Clark /*
2eb637edbSMichael Clark * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3eb637edbSMichael Clark *
4eb637edbSMichael Clark * Copyright (c) 2017 SiFive, Inc.
5eb637edbSMichael Clark *
6eb637edbSMichael Clark * Provides a board compatible with the SiFive Freedom E SDK:
7eb637edbSMichael Clark *
8eb637edbSMichael Clark * 0) UART
9eb637edbSMichael Clark * 1) CLINT (Core Level Interruptor)
10eb637edbSMichael Clark * 2) PLIC (Platform Level Interrupt Controller)
11eb637edbSMichael Clark * 3) PRCI (Power, Reset, Clock, Interrupt)
12eb637edbSMichael Clark * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
13eb637edbSMichael Clark * 5) Flash memory emulated as RAM
14eb637edbSMichael Clark *
15eb637edbSMichael Clark * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
16eb637edbSMichael Clark * The OTP ROM and Flash boot code will be emulated in a future version.
17eb637edbSMichael Clark *
18eb637edbSMichael Clark * This program is free software; you can redistribute it and/or modify it
19eb637edbSMichael Clark * under the terms and conditions of the GNU General Public License,
20eb637edbSMichael Clark * version 2 or later, as published by the Free Software Foundation.
21eb637edbSMichael Clark *
22eb637edbSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT
23eb637edbSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24eb637edbSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
25eb637edbSMichael Clark * more details.
26eb637edbSMichael Clark *
27eb637edbSMichael Clark * You should have received a copy of the GNU General Public License along with
28eb637edbSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>.
29eb637edbSMichael Clark */
30eb637edbSMichael Clark
31eb637edbSMichael Clark #include "qemu/osdep.h"
32e2b3ef75SBin Meng #include "qemu/cutils.h"
33eb637edbSMichael Clark #include "qemu/error-report.h"
34eb637edbSMichael Clark #include "qapi/error.h"
35eb637edbSMichael Clark #include "hw/boards.h"
36eb637edbSMichael Clark #include "hw/loader.h"
37eb637edbSMichael Clark #include "hw/sysbus.h"
38eb637edbSMichael Clark #include "hw/char/serial.h"
3968c9a9b3SBin Meng #include "hw/misc/unimp.h"
40eb637edbSMichael Clark #include "target/riscv/cpu.h"
41eb637edbSMichael Clark #include "hw/riscv/riscv_hart.h"
42eb637edbSMichael Clark #include "hw/riscv/sifive_e.h"
430ac24d56SAlistair Francis #include "hw/riscv/boot.h"
44b609b7e3SBin Meng #include "hw/char/sifive_uart.h"
45cc63a182SAnup Patel #include "hw/intc/riscv_aclint.h"
4684fcf3c1SBin Meng #include "hw/intc/sifive_plic.h"
4789ece6f7SBin Meng #include "hw/misc/sifive_e_prci.h"
4882193640STommy Wu #include "hw/misc/sifive_e_aon.h"
49eb637edbSMichael Clark #include "chardev/char.h"
5046517dd4SMarkus Armbruster #include "sysemu/sysemu.h"
51eb637edbSMichael Clark
523de70cecSBin Meng static const MemMapEntry sifive_e_memmap[] = {
535488f276SEduardo Habkost [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
545488f276SEduardo Habkost [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
555488f276SEduardo Habkost [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
565488f276SEduardo Habkost [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
575488f276SEduardo Habkost [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
585488f276SEduardo Habkost [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
595488f276SEduardo Habkost [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
605488f276SEduardo Habkost [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
615488f276SEduardo Habkost [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
625488f276SEduardo Habkost [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
635488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
645488f276SEduardo Habkost [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
655488f276SEduardo Habkost [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
665488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
675488f276SEduardo Habkost [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
685488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
695488f276SEduardo Habkost [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
705488f276SEduardo Habkost [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
715488f276SEduardo Habkost [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
72eb637edbSMichael Clark };
73eb637edbSMichael Clark
sifive_e_machine_init(MachineState * machine)748f8c6c1aSBin Meng static void sifive_e_machine_init(MachineState *machine)
75eb637edbSMichael Clark {
76e2b3ef75SBin Meng MachineClass *mc = MACHINE_GET_CLASS(machine);
7773261285SBin Meng const MemMapEntry *memmap = sifive_e_memmap;
78eb637edbSMichael Clark
790869490bSAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(machine);
80eb637edbSMichael Clark MemoryRegion *sys_mem = get_system_memory();
815aec3247SMichael Clark int i;
82eb637edbSMichael Clark
83e2b3ef75SBin Meng if (machine->ram_size != mc->default_ram_size) {
84e2b3ef75SBin Meng char *sz = size_to_str(mc->default_ram_size);
85e2b3ef75SBin Meng error_report("Invalid RAM size, should be %s", sz);
86e2b3ef75SBin Meng g_free(sz);
87e2b3ef75SBin Meng exit(EXIT_FAILURE);
88e2b3ef75SBin Meng }
89e2b3ef75SBin Meng
90651cd8b7SAlistair Francis /* Initialize SoC */
919fc7fc4dSMarkus Armbruster object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
928f972e5bSAlistair Francis qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
93eb637edbSMichael Clark
94eb637edbSMichael Clark /* Data Tightly Integrated Memory */
95eb637edbSMichael Clark memory_region_add_subregion(sys_mem,
96e2b3ef75SBin Meng memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
97eb637edbSMichael Clark
98651cd8b7SAlistair Francis /* Mask ROM reset vector */
99495134b7SBin Meng uint32_t reset_vec[4];
1005a842062SAlistair Francis
1015a842062SAlistair Francis if (s->revb) {
102495134b7SBin Meng reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */
1035a842062SAlistair Francis } else {
104495134b7SBin Meng reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */
1055a842062SAlistair Francis }
106495134b7SBin Meng reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */
107495134b7SBin Meng
108495134b7SBin Meng reset_vec[0] = reset_vec[3] = 0;
109651cd8b7SAlistair Francis
110651cd8b7SAlistair Francis /* copy in the reset vector in little_endian byte order */
111651cd8b7SAlistair Francis for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
112651cd8b7SAlistair Francis reset_vec[i] = cpu_to_le32(reset_vec[i]);
113651cd8b7SAlistair Francis }
114651cd8b7SAlistair Francis rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
1155488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
116651cd8b7SAlistair Francis
117651cd8b7SAlistair Francis if (machine->kernel_filename) {
11862c5bc34SDaniel Henrique Barboza riscv_load_kernel(machine, &s->soc.cpus,
119487d73fcSDaniel Henrique Barboza memmap[SIFIVE_E_DEV_DTIM].base,
120487d73fcSDaniel Henrique Barboza false, NULL);
121651cd8b7SAlistair Francis }
122651cd8b7SAlistair Francis }
123651cd8b7SAlistair Francis
sifive_e_machine_get_revb(Object * obj,Error ** errp)1245a842062SAlistair Francis static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
1255a842062SAlistair Francis {
1265a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj);
1275a842062SAlistair Francis
1285a842062SAlistair Francis return s->revb;
1295a842062SAlistair Francis }
1305a842062SAlistair Francis
sifive_e_machine_set_revb(Object * obj,bool value,Error ** errp)1315a842062SAlistair Francis static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
1325a842062SAlistair Francis {
1335a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj);
1345a842062SAlistair Francis
1355a842062SAlistair Francis s->revb = value;
1365a842062SAlistair Francis }
1375a842062SAlistair Francis
sifive_e_machine_instance_init(Object * obj)1380869490bSAlistair Francis static void sifive_e_machine_instance_init(Object *obj)
1390869490bSAlistair Francis {
1405a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj);
1415a842062SAlistair Francis
1425a842062SAlistair Francis s->revb = false;
1430869490bSAlistair Francis }
1440869490bSAlistair Francis
sifive_e_machine_class_init(ObjectClass * oc,void * data)1450869490bSAlistair Francis static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
1460869490bSAlistair Francis {
1470869490bSAlistair Francis MachineClass *mc = MACHINE_CLASS(oc);
1480869490bSAlistair Francis
1490869490bSAlistair Francis mc->desc = "RISC-V Board compatible with SiFive E SDK";
1508f8c6c1aSBin Meng mc->init = sifive_e_machine_init;
1510869490bSAlistair Francis mc->max_cpus = 1;
1520869490bSAlistair Francis mc->default_cpu_type = SIFIVE_E_CPU;
153e2b3ef75SBin Meng mc->default_ram_id = "riscv.sifive.e.ram";
154e2b3ef75SBin Meng mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
155fabbcbd9SEduardo Habkost
156fabbcbd9SEduardo Habkost object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
157fabbcbd9SEduardo Habkost sifive_e_machine_set_revb);
158fabbcbd9SEduardo Habkost object_class_property_set_description(oc, "revb",
159fabbcbd9SEduardo Habkost "Set on to tell QEMU that it should model "
160fabbcbd9SEduardo Habkost "the revB HiFive1 board");
1610869490bSAlistair Francis }
1620869490bSAlistair Francis
1630869490bSAlistair Francis static const TypeInfo sifive_e_machine_typeinfo = {
1640869490bSAlistair Francis .name = MACHINE_TYPE_NAME("sifive_e"),
1650869490bSAlistair Francis .parent = TYPE_MACHINE,
1660869490bSAlistair Francis .class_init = sifive_e_machine_class_init,
1670869490bSAlistair Francis .instance_init = sifive_e_machine_instance_init,
1680869490bSAlistair Francis .instance_size = sizeof(SiFiveEState),
1690869490bSAlistair Francis };
1700869490bSAlistair Francis
sifive_e_machine_init_register_types(void)1710869490bSAlistair Francis static void sifive_e_machine_init_register_types(void)
1720869490bSAlistair Francis {
1730869490bSAlistair Francis type_register_static(&sifive_e_machine_typeinfo);
1740869490bSAlistair Francis }
1750869490bSAlistair Francis
type_init(sifive_e_machine_init_register_types)1760869490bSAlistair Francis type_init(sifive_e_machine_init_register_types)
1770869490bSAlistair Francis
1788f8c6c1aSBin Meng static void sifive_e_soc_init(Object *obj)
179651cd8b7SAlistair Francis {
180c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine());
181651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(obj);
182651cd8b7SAlistair Francis
183db873cc5SMarkus Armbruster object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
1845325cc34SMarkus Armbruster object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
185651cd8b7SAlistair Francis &error_abort);
18673f6ed97SBin Meng object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
187db873cc5SMarkus Armbruster object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
18830efbf33SFabien Chouteau TYPE_SIFIVE_GPIO);
18982193640STommy Wu object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon,
19082193640STommy Wu TYPE_SIFIVE_E_AON);
191651cd8b7SAlistair Francis }
192651cd8b7SAlistair Francis
sifive_e_soc_realize(DeviceState * dev,Error ** errp)1938f8c6c1aSBin Meng static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
194651cd8b7SAlistair Francis {
195c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine());
19673261285SBin Meng const MemMapEntry *memmap = sifive_e_memmap;
197651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(dev);
198651cd8b7SAlistair Francis MemoryRegion *sys_mem = get_system_memory();
199651cd8b7SAlistair Francis
2005325cc34SMarkus Armbruster object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
20174dbba9bSCorey Wharton &error_abort);
20291a3387dSTsukasa OI sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
203651cd8b7SAlistair Francis
204eb637edbSMichael Clark /* Mask ROM */
205414c47d2SPhilippe Mathieu-Daudé memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
2065488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
207eb637edbSMichael Clark memory_region_add_subregion(sys_mem,
2085488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
209eb637edbSMichael Clark
210eb637edbSMichael Clark /* MMIO */
2115488f276SEduardo Habkost s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
212f436ecc3SAlistair Francis (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,
213eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_SOURCES,
214eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_PRIORITIES,
215eb637edbSMichael Clark SIFIVE_E_PLIC_PRIORITY_BASE,
216eb637edbSMichael Clark SIFIVE_E_PLIC_PENDING_BASE,
217eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_BASE,
218eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_STRIDE,
219eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_BASE,
220eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_STRIDE,
2215488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PLIC].size);
222b8fb878aSAnup Patel riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
223b8fb878aSAnup Patel 0, ms->smp.cpus, false);
224b8fb878aSAnup Patel riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
225b8fb878aSAnup Patel RISCV_ACLINT_SWI_SIZE,
226b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
227b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
228*a7472560SRomán Cárdenas SIFIVE_E_LFCLK_DEFAULT_FREQ, false);
2295488f276SEduardo Habkost sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
23030efbf33SFabien Chouteau
23182193640STommy Wu /* AON */
23282193640STommy Wu
23382193640STommy Wu if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) {
23482193640STommy Wu return;
23582193640STommy Wu }
23682193640STommy Wu
23782193640STommy Wu /* Map AON registers */
23882193640STommy Wu sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base);
23982193640STommy Wu
24030efbf33SFabien Chouteau /* GPIO */
24130efbf33SFabien Chouteau
242668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
24330efbf33SFabien Chouteau return;
24430efbf33SFabien Chouteau }
24530efbf33SFabien Chouteau
24630efbf33SFabien Chouteau /* Map GPIO registers */
2475488f276SEduardo Habkost sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
24830efbf33SFabien Chouteau
24930efbf33SFabien Chouteau /* Pass all GPIOs to the SOC layer so they are available to the board */
25030efbf33SFabien Chouteau qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
25130efbf33SFabien Chouteau
25230efbf33SFabien Chouteau /* Connect GPIO interrupts to the PLIC */
25330efbf33SFabien Chouteau for (int i = 0; i < 32; i++) {
25430efbf33SFabien Chouteau sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
25530efbf33SFabien Chouteau qdev_get_gpio_in(DEVICE(s->plic),
25630efbf33SFabien Chouteau SIFIVE_E_GPIO0_IRQ0 + i));
25730efbf33SFabien Chouteau }
25882193640STommy Wu sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0,
25982193640STommy Wu qdev_get_gpio_in(DEVICE(s->plic),
26082193640STommy Wu SIFIVE_E_AON_WDT_IRQ));
26130efbf33SFabien Chouteau
2625488f276SEduardo Habkost sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
263647a70a1SAlistair Francis serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
26468c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi0",
2655488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
26668c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm0",
2675488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
2685488f276SEduardo Habkost sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
269194eef09SMichael Clark serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
27068c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi1",
2715488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
27268c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm1",
2735488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
27468c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi2",
2755488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
27668c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm2",
2775488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
278eb637edbSMichael Clark
279eb637edbSMichael Clark /* Flash memory */
280414c47d2SPhilippe Mathieu-Daudé memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
2815488f276SEduardo Habkost memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
2825488f276SEduardo Habkost memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
283c988de41SPalmer Dabbelt &s->xip_mem);
284eb637edbSMichael Clark }
285eb637edbSMichael Clark
sifive_e_soc_class_init(ObjectClass * oc,void * data)2868f8c6c1aSBin Meng static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
287651cd8b7SAlistair Francis {
288651cd8b7SAlistair Francis DeviceClass *dc = DEVICE_CLASS(oc);
289651cd8b7SAlistair Francis
2908f8c6c1aSBin Meng dc->realize = sifive_e_soc_realize;
291651cd8b7SAlistair Francis /* Reason: Uses serial_hds in realize function, thus can't be used twice */
292651cd8b7SAlistair Francis dc->user_creatable = false;
293651cd8b7SAlistair Francis }
294651cd8b7SAlistair Francis
2958f8c6c1aSBin Meng static const TypeInfo sifive_e_soc_type_info = {
296651cd8b7SAlistair Francis .name = TYPE_RISCV_E_SOC,
297651cd8b7SAlistair Francis .parent = TYPE_DEVICE,
298651cd8b7SAlistair Francis .instance_size = sizeof(SiFiveESoCState),
2998f8c6c1aSBin Meng .instance_init = sifive_e_soc_init,
3008f8c6c1aSBin Meng .class_init = sifive_e_soc_class_init,
301651cd8b7SAlistair Francis };
302651cd8b7SAlistair Francis
sifive_e_soc_register_types(void)3038f8c6c1aSBin Meng static void sifive_e_soc_register_types(void)
304651cd8b7SAlistair Francis {
3058f8c6c1aSBin Meng type_register_static(&sifive_e_soc_type_info);
306651cd8b7SAlistair Francis }
307651cd8b7SAlistair Francis
3088f8c6c1aSBin Meng type_init(sifive_e_soc_register_types)
309