1117a433dSBin Mengmenu "RISC-V architecture" 2f94c44e5SRick Chen depends on RISCV 3f94c44e5SRick Chen 4f94c44e5SRick Chenconfig SYS_ARCH 5f94c44e5SRick Chen default "riscv" 6f94c44e5SRick Chen 7f94c44e5SRick Chenchoice 8f94c44e5SRick Chen prompt "Target select" 9f94c44e5SRick Chen optional 10f94c44e5SRick Chen 116f4dd62fSRick Chenconfig TARGET_AX25_AE350 126f4dd62fSRick Chen bool "Support ax25-ae350" 13f94c44e5SRick Chen 14510e379cSBin Mengconfig TARGET_QEMU_VIRT 15510e379cSBin Meng bool "Support QEMU Virt Board" 16510e379cSBin Meng 17*3fda0262SAnup Patelconfig TARGET_SIFIVE_FU540 18*3fda0262SAnup Patel bool "Support SiFive FU540 Board" 19*3fda0262SAnup Patel 20f94c44e5SRick Chenendchoice 21f94c44e5SRick Chen 2252923c6dSRick Chen# board-specific options below 236f4dd62fSRick Chensource "board/AndesTech/ax25-ae350/Kconfig" 24510e379cSBin Mengsource "board/emulation/qemu-riscv/Kconfig" 25*3fda0262SAnup Patelsource "board/sifive/fu540/Kconfig" 26f94c44e5SRick Chen 2752923c6dSRick Chen# platform-specific options below 2852923c6dSRick Chensource "arch/riscv/cpu/ax25/Kconfig" 29fdff1f96SAnup Patelsource "arch/riscv/cpu/generic/Kconfig" 3052923c6dSRick Chen 3152923c6dSRick Chen# architecture-specific options below 3252923c6dSRick Chen 33f94c44e5SRick Chenchoice 34862e2e75SLukas Auer prompt "Base ISA" 35862e2e75SLukas Auer default ARCH_RV32I 36f94c44e5SRick Chen 37862e2e75SLukas Auerconfig ARCH_RV32I 38862e2e75SLukas Auer bool "RV32I" 39f94c44e5SRick Chen select 32BIT 40f94c44e5SRick Chen help 41862e2e75SLukas Auer Choose this option to target the RV32I base integer instruction set. 42f94c44e5SRick Chen 43862e2e75SLukas Auerconfig ARCH_RV64I 44862e2e75SLukas Auer bool "RV64I" 45f94c44e5SRick Chen select 64BIT 4671158564SLukas Auer select PHYS_64BIT 47f94c44e5SRick Chen help 48862e2e75SLukas Auer Choose this option to target the RV64I base integer instruction set. 49f94c44e5SRick Chen 50f94c44e5SRick Chenendchoice 51f94c44e5SRick Chen 528176ea4dSLukas Auerchoice 538176ea4dSLukas Auer prompt "Code Model" 548176ea4dSLukas Auer default CMODEL_MEDLOW 558176ea4dSLukas Auer 568176ea4dSLukas Auerconfig CMODEL_MEDLOW 578176ea4dSLukas Auer bool "medium low code model" 588176ea4dSLukas Auer help 598176ea4dSLukas Auer U-Boot and its statically defined symbols must lie within a single 2 GiB 608176ea4dSLukas Auer address range and must lie between absolute addresses -2 GiB and +2 GiB. 618176ea4dSLukas Auer 628176ea4dSLukas Auerconfig CMODEL_MEDANY 638176ea4dSLukas Auer bool "medium any code model" 648176ea4dSLukas Auer help 658176ea4dSLukas Auer U-Boot and its statically defined symbols must be within any single 2 GiB 668176ea4dSLukas Auer address range. 678176ea4dSLukas Auer 688176ea4dSLukas Auerendchoice 698176ea4dSLukas Auer 703cfc8252SAnup Patelchoice 713cfc8252SAnup Patel prompt "Run Mode" 723cfc8252SAnup Patel default RISCV_MMODE 733cfc8252SAnup Patel 743cfc8252SAnup Patelconfig RISCV_MMODE 753cfc8252SAnup Patel bool "Machine" 763cfc8252SAnup Patel help 773cfc8252SAnup Patel Choose this option to build U-Boot for RISC-V M-Mode. 783cfc8252SAnup Patel 793cfc8252SAnup Patelconfig RISCV_SMODE 803cfc8252SAnup Patel bool "Supervisor" 813cfc8252SAnup Patel help 823cfc8252SAnup Patel Choose this option to build U-Boot for RISC-V S-Mode. 833cfc8252SAnup Patel 843cfc8252SAnup Patelendchoice 853cfc8252SAnup Patel 86d57ffa65SLukas Auerconfig RISCV_ISA_C 87d57ffa65SLukas Auer bool "Emit compressed instructions" 88d57ffa65SLukas Auer default y 89d57ffa65SLukas Auer help 90d57ffa65SLukas Auer Adds "C" to the ISA subsets that the toolchain is allowed to emit 91d57ffa65SLukas Auer when building U-Boot, which results in compressed instructions in the 92d57ffa65SLukas Auer U-Boot binary. 93d57ffa65SLukas Auer 94d57ffa65SLukas Auerconfig RISCV_ISA_A 95d57ffa65SLukas Auer def_bool y 96d57ffa65SLukas Auer 97f94c44e5SRick Chenconfig 32BIT 98f94c44e5SRick Chen bool 99f94c44e5SRick Chen 100f94c44e5SRick Chenconfig 64BIT 101f94c44e5SRick Chen bool 102f94c44e5SRick Chen 103644a3cd7SBin Mengconfig SIFIVE_CLINT 104644a3cd7SBin Meng bool 105644a3cd7SBin Meng depends on RISCV_MMODE 106644a3cd7SBin Meng select REGMAP 107644a3cd7SBin Meng select SYSCON 108644a3cd7SBin Meng help 109644a3cd7SBin Meng The SiFive CLINT block holds memory-mapped control and status registers 110644a3cd7SBin Meng associated with software and timer interrupts. 111644a3cd7SBin Meng 112511107d8SAnup Patelconfig RISCV_RDTIME 113511107d8SAnup Patel bool 114511107d8SAnup Patel default y if RISCV_SMODE 115511107d8SAnup Patel help 116511107d8SAnup Patel The provides the riscv_get_time() API that is implemented using the 117511107d8SAnup Patel standard rdtime instruction. This is the case for S-mode U-Boot, and 118511107d8SAnup Patel is useful for processors that support rdtime in M-mode too. 119511107d8SAnup Patel 12092b64fefSBin Mengconfig SYS_MALLOC_F_LEN 12192b64fefSBin Meng default 0x1000 12292b64fefSBin Meng 123f94c44e5SRick Chenendmenu 124