Lines Matching +full:- +full:clint
2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
11 * 0) CLINT (Core Level Interruptor)
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
38 #include "qemu/error-report.h"
59 * See https://github.com/polarfire-soc/hart-software-services
64 /* CLINT timebase frequency */
76 * https://www.microsemi.com/document-portal/doc_download/
77 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
81 * https://www.microsemi.com/document-portal/doc_download/
82 * 1244581-polarfire-soc-register-map, contains the following 2 major parts:
83 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
85 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
151 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); in microchip_pfsoc_soc_instance_init()
152 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); in microchip_pfsoc_soc_instance_init()
154 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, in microchip_pfsoc_soc_instance_init()
156 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); in microchip_pfsoc_soc_instance_init()
157 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); in microchip_pfsoc_soc_instance_init()
158 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", in microchip_pfsoc_soc_instance_init()
160 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); in microchip_pfsoc_soc_instance_init()
162 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); in microchip_pfsoc_soc_instance_init()
163 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); in microchip_pfsoc_soc_instance_init()
165 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, in microchip_pfsoc_soc_instance_init()
167 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); in microchip_pfsoc_soc_instance_init()
168 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); in microchip_pfsoc_soc_instance_init()
169 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", in microchip_pfsoc_soc_instance_init()
171 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); in microchip_pfsoc_soc_instance_init()
173 object_initialize_child(obj, "dma-controller", &s->dma, in microchip_pfsoc_soc_instance_init()
176 object_initialize_child(obj, "sysreg", &s->sysreg, in microchip_pfsoc_soc_instance_init()
179 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, in microchip_pfsoc_soc_instance_init()
181 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, in microchip_pfsoc_soc_instance_init()
184 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); in microchip_pfsoc_soc_instance_init()
185 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); in microchip_pfsoc_soc_instance_init()
187 object_initialize_child(obj, "sd-controller", &s->sdhci, in microchip_pfsoc_soc_instance_init()
190 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); in microchip_pfsoc_soc_instance_init()
207 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); in microchip_pfsoc_soc_realize()
208 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); in microchip_pfsoc_soc_realize()
210 * The cluster must be realized after the RISC-V hart array container, in microchip_pfsoc_soc_realize()
215 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); in microchip_pfsoc_soc_realize()
216 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); in microchip_pfsoc_soc_realize()
249 /* CLINT */ in microchip_pfsoc_soc_realize()
251 0, ms->smp.cpus, false); in microchip_pfsoc_soc_realize()
254 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, in microchip_pfsoc_soc_realize()
263 * Add L2-LIM at reset size. in microchip_pfsoc_soc_realize()
278 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); in microchip_pfsoc_soc_realize()
281 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, in microchip_pfsoc_soc_realize()
282 plic_hart_config, ms->smp.cpus, 0, in microchip_pfsoc_soc_realize()
295 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); in microchip_pfsoc_soc_realize()
296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, in microchip_pfsoc_soc_realize()
299 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, in microchip_pfsoc_soc_realize()
300 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
305 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); in microchip_pfsoc_soc_realize()
306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, in microchip_pfsoc_soc_realize()
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0, in microchip_pfsoc_soc_realize()
309 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
328 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); in microchip_pfsoc_soc_realize()
329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, in microchip_pfsoc_soc_realize()
333 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); in microchip_pfsoc_soc_realize()
334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, in microchip_pfsoc_soc_realize()
338 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); in microchip_pfsoc_soc_realize()
339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, in microchip_pfsoc_soc_realize()
341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, in microchip_pfsoc_soc_realize()
342 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); in microchip_pfsoc_soc_realize()
345 s->serial0 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
347 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), in microchip_pfsoc_soc_realize()
349 s->serial1 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
351 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), in microchip_pfsoc_soc_realize()
353 s->serial2 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
355 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), in microchip_pfsoc_soc_realize()
357 s->serial3 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
359 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), in microchip_pfsoc_soc_realize()
361 s->serial4 = mchp_pfsoc_mmuart_create(system_memory, in microchip_pfsoc_soc_realize()
363 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), in microchip_pfsoc_soc_realize()
413 qemu_configure_nic_device(DEVICE(&s->gem0), true, NULL); in microchip_pfsoc_soc_realize()
414 qemu_configure_nic_device(DEVICE(&s->gem1), true, NULL); in microchip_pfsoc_soc_realize()
416 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); in microchip_pfsoc_soc_realize()
417 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); in microchip_pfsoc_soc_realize()
418 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); in microchip_pfsoc_soc_realize()
419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, in microchip_pfsoc_soc_realize()
421 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, in microchip_pfsoc_soc_realize()
422 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); in microchip_pfsoc_soc_realize()
424 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); in microchip_pfsoc_soc_realize()
425 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); in microchip_pfsoc_soc_realize()
426 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); in microchip_pfsoc_soc_realize()
427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, in microchip_pfsoc_soc_realize()
429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, in microchip_pfsoc_soc_realize()
430 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); in microchip_pfsoc_soc_realize()
452 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); in microchip_pfsoc_soc_realize()
453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, in microchip_pfsoc_soc_realize()
455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0, in microchip_pfsoc_soc_realize()
456 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
486 dc->realize = microchip_pfsoc_soc_realize; in microchip_pfsoc_soc_class_init()
488 dc->user_creatable = false; in microchip_pfsoc_soc_class_init()
526 if (machine->ram_size < mc->default_ram_size) { in type_init()
527 char *sz = size_to_str(mc->default_ram_size); in type_init()
534 object_initialize_child(OBJECT(machine), "soc", &s->soc, in type_init()
536 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in type_init()
538 /* Split RAM into low and high regions using aliases to machine->ram */ in type_init()
540 mem_high_size = machine->ram_size - mem_low_size; in type_init()
542 "microchip.icicle.kit.ram_low", machine->ram, in type_init()
545 "microchip.icicle.kit.ram_high", machine->ram, in type_init()
572 CadenceSDHCIState *sdhci = &(s->soc.sdhci); in type_init()
577 qdev_realize_and_unref(card, sdhci->bus, &error_fatal); in type_init()
583 * -bios | -kernel | payload in type_init()
584 * -------+------------+-------- in type_init()
589 * This ensures backwards compatibility with how we used to expose -bios in type_init()
592 * When -kernel is used for direct boot, -dtb must be present to provide in type_init()
596 if (machine->kernel_filename && machine->dtb) { in type_init()
598 machine->fdt = load_device_tree(machine->dtb, &fdt_size); in type_init()
599 if (!machine->fdt) { in type_init()
619 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, in type_init()
622 kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, in type_init()
629 riscv_load_fdt(fdt_load_addr, machine->fdt); in type_init()
632 riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, in type_init()
643 mc->desc = "Microchip PolarFire SoC Icicle Kit"; in microchip_icicle_kit_machine_class_init()
644 mc->init = microchip_icicle_kit_machine_init; in microchip_icicle_kit_machine_class_init()
645 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + in microchip_icicle_kit_machine_class_init()
647 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; in microchip_icicle_kit_machine_class_init()
648 mc->default_cpus = mc->min_cpus; in microchip_icicle_kit_machine_class_init()
649 mc->default_ram_id = "microchip.icicle.kit.ram"; in microchip_icicle_kit_machine_class_init()
658 mc->default_ram_size = 1537 * MiB; in microchip_icicle_kit_machine_class_init()
662 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"),