2  * QEMU RISC-V Spike Board
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
7  * This provides a RISC-V Board with the following devices:
10  * 1) CLINT (Timer and IPI)
26 #include "qemu/error-report.h"
68     fdt = ms->fdt = create_device_tree(&fdt_size);  in create_fdt()
74     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");  in create_fdt()
75     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");  in create_fdt()
76     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);  in create_fdt()
77     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);  in create_fdt()
88     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");  in create_fdt()
89     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);  in create_fdt()
90     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);  in create_fdt()
93     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",  in create_fdt()
95     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);  in create_fdt()
96     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);  in create_fdt()
97     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");  in create_fdt()
99     for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) {  in create_fdt()
100         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);  in create_fdt()
103         clint_cells =  g_new0(uint32_t, s->soc[socket].num_harts * 4);  in create_fdt()
105         for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {  in create_fdt()
109                 s->soc[socket].hartid_base + cpu);  in create_fdt()
112                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");  in create_fdt()
114                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");  in create_fdt()
116             riscv_isa_write_fdt(&s->soc[socket].harts[cpu], fdt, cpu_name);  in create_fdt()
120                 s->soc[socket].hartid_base + cpu);  in create_fdt()
125             intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);  in create_fdt()
130                 "riscv,cpu-intc");  in create_fdt()
131             qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);  in create_fdt()
132             qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);  in create_fdt()
160         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);  in create_fdt()
166         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",  in create_fdt()
167             clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);  in create_fdt()
178     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");  in create_fdt()
237         object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],  in spike_board_init()
240         object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",  in spike_board_init()
241                                 machine->cpu_type, &error_abort);  in spike_board_init()
242         object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",  in spike_board_init()
244         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",  in spike_board_init()
246         sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal);  in spike_board_init()
262         machine->ram);  in spike_board_init()
271     firmware_name = riscv_find_firmware(machine->firmware,  in spike_board_init()
272                         riscv_default_firmware_name(&s->soc[0]));  in spike_board_init()
280     if (!firmware_name && !machine->kernel_filename) {  in spike_board_init()
286         if (!htif_custom_base && machine->kernel_filename) {  in spike_board_init()
287             htif_custom_base = !spike_test_elf_image(machine->kernel_filename);  in spike_board_init()
300     create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);  in spike_board_init()
303     if (machine->kernel_filename) {  in spike_board_init()
304         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],  in spike_board_init()
307         kernel_entry = riscv_load_kernel(machine, &s->soc[0],  in spike_board_init()
321     riscv_load_fdt(fdt_load_addr, machine->fdt);  in spike_board_init()
324     riscv_setup_rom_reset_vec(machine, &s->soc[0], firmware_load_addr,  in spike_board_init()
347     mc->desc = "RISC-V Spike board";  in spike_machine_class_init()
348     mc->init = spike_board_init;  in spike_machine_class_init()
349     mc->max_cpus = SPIKE_CPUS_MAX;  in spike_machine_class_init()
350     mc->is_default = true;  in spike_machine_class_init()
351     mc->default_cpu_type = TYPE_RISCV_CPU_BASE;  in spike_machine_class_init()
352     mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;  in spike_machine_class_init()
353     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;  in spike_machine_class_init()
354     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;  in spike_machine_class_init()
355     mc->numa_mem_supported = true;  in spike_machine_class_init()
357     mc->cpu_cluster_has_numa_boundary = true;  in spike_machine_class_init()
358     mc->default_ram_id = "riscv.spike.ram";  in spike_machine_class_init()
362     object_class_property_add_uint8_ptr(oc, "signature-granularity",  in spike_machine_class_init()
364     object_class_property_set_description(oc, "signature-granularity",  in spike_machine_class_init()