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/openbmc/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Samsung EXYNOS5 SoC series G-Scaler driver
12 #include "gsc-core.h"
16 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); in gsc_hw_set_sw_reset()
22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
31 return -EBUSY; in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
[all …]
/openbmc/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
18 * of the D-PHY specification (v1.2).
24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
29 return -EINVAL; in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
[all …]
/openbmc/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
13 #include <media/drv-intf/exynos-fimc.h>
14 #include "media-dev.h"
16 #include "fimc-reg.h"
17 #include "fimc-core.h"
21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
[all …]
H A Dfimc-lite-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Register interface file for EXYNOS FIMC-LITE (camera interface) driver
12 #include <media/drv-intf/exynos-fimc.h>
14 #include "fimc-lite-reg.h"
15 #include "fimc-lite.h"
16 #include "fimc-core.h"
23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
[all …]
/openbmc/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "camif-regs.h"
13 #define camif_write(_camif, _off, _val) writel(_val, (_camif)->io_base + (_off))
14 #define camif_read(_camif, _off) readl((_camif)->io_base + (_off))
18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
[all …]
/openbmc/linux/tools/testing/selftests/bpf/prog_tests/
H A Dcore_extern.c1 // SPDX-License-Identifier: GPL-2.0
21 #define CFG "CONFIG_BPF_SYSCALL=n\n" macro
25 const char *cfg; member
32 .cfg = "CONFIG_BPF_SYSCALL=n\n"
54 { .name = "tristate (y)", .cfg = CFG"CONFIG_TRISTATE=y\n",
56 { .name = "tristate (n)", .cfg = CFG"CONFIG_TRISTATE=n\n",
58 { .name = "tristate (m)", .cfg = CFG"CONFIG_TRISTATE=m\n",
60 { .name = "tristate (int)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=1" },
61 { .name = "tristate (bad)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=M" },
63 { .name = "bool (y)", .cfg = CFG"CONFIG_BOOL=y\n",
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/openbmc/linux/drivers/pci/
H A Decam.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-ecam.h>
15 * On 64-bit systems, we do a single ioremap for the whole config space
16 * since we have enough virtual address range available. On 32-bit, we
23 * - reserve mem region
24 * - alloc struct pci_config_window with space for all mappings
25 * - ioremap the config space
31 unsigned int bus_shift = ops->bus_shift; in pci_ecam_create()
32 struct pci_config_window *cfg; in pci_ecam_create() local
37 if (busr->start > busr->end) in pci_ecam_create()
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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.c1 // SPDX-License-Identifier: GPL-2.0
85 return (rpm->pdev->device == PCI_DEVID_CN10KB_RPM); in is_dev_rpm2()
133 u64 cfg, last; in rpm_lmac_tx_enable() local
136 return -ENODEV; in rpm_lmac_tx_enable()
138 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
139 last = cfg; in rpm_lmac_tx_enable()
141 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
143 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
145 if (cfg != last) in rpm_lmac_tx_enable()
146 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
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H A Dcgx.c1 // SPDX-License-Identifier: GPL-2.0
24 #define DRV_NAME "Marvell-CGX/RPM"
80 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) || in is_dev_rpm()
81 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM); in is_dev_rpm()
86 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac) in is_lmac_valid()
88 return test_bit(lmac_id, &cgx->lmac_bmap); in is_lmac_valid()
98 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { in get_sequence_id_of_lmac()
112 return ((struct cgx *)cgxd)->mac_ops; in get_mac_ops()
117 return ((struct cgx *)cgxd)->fifo_len; in cgx_get_fifo_len()
122 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + in cgx_write()
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/openbmc/qemu/tests/qtest/
H A Dsifive-e-aon-watchdog-test.c64 QTestState *qts = qtest_init("-machine sifive_e"); in test_wdogcount()
94 QTestState *qts = qtest_init("-machine sifive_e"); in test_wdogcfg()
131 QTestState *qts = qtest_init("-machine sifive_e"); in test_wdogcmp0()
148 QTestState *qts = qtest_init("-machine sifive_e"); in test_wdogkey()
168 QTestState *qts = qtest_init("-machine sifive_e"); in test_wdogfeed()
182 uint32_t cfg; in test_scaled_wdogs() local
184 QTestState *qts = qtest_init("-machine sifive_e"); in test_scaled_wdogs()
195 cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG); in test_scaled_wdogs()
196 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, i); in test_scaled_wdogs()
198 qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg); in test_scaled_wdogs()
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
48 #define OCTEP_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
53 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
54 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
55 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
56 #define CFG_GET_IQ_PKIND(cfg) ((cfg)->iq.pkind) argument
57 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
58 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
59 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
61 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
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/openbmc/linux/sound/pci/hda/
H A Dhda_auto_parser.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BIOS auto-parser helper functions for HD-audio
38 return (int)(a->seq - b->seq); in compare_seq()
55 /* add the found input-pin to the cfg->inputs[] table */
56 static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, in add_auto_cfg_input_pin() argument
59 if (cfg->num_inputs < AUTO_CFG_MAX_INS) { in add_auto_cfg_input_pin()
60 cfg->inputs[cfg->num_inputs].pin = nid; in add_auto_cfg_input_pin()
61 cfg->inputs[cfg->num_inputs].type = type; in add_auto_cfg_input_pin()
62 cfg->inputs[cfg->num_inputs].has_boost_on_pin = in add_auto_cfg_input_pin()
64 cfg->num_inputs++; in add_auto_cfg_input_pin()
[all …]
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dphy_tbl.h1 /* SPDX-License-Identifier: GPL-2.0+ */
45 PHY_ENGINE cfg; member
54 .cfg.fp_set = phy_realtek5,
55 .cfg.fp_clr = recov_phy_realtek5 },
59 .name = "RTL8211FD-VX",
60 .cfg.fp_set = phy_realtek5,
61 .cfg.fp_clr = recov_phy_realtek5 },
65 .name = "RTL8211F-VD",
66 .cfg.fp_set = phy_realtek5,
67 .cfg.fp_clr = recov_phy_realtek5 },
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #include "regs-fimc.h"
115 return readl(ctx->regs + reg); in fimc_read()
120 writel(val, ctx->regs + reg); in fimc_write()
125 void __iomem *r = ctx->regs + reg; in fimc_set_bits()
132 void __iomem *r = ctx->regs + reg; in fimc_clear_bits()
139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
[all …]
/openbmc/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8996.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
100 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
154 return dividend - 1; in pll_get_pll_cmp()
179 vco_optimal_index = -1; in pll_get_post_div()
201 if (vco_optimal_index == -1) { in pll_get_post_div()
207 pd->vco_freq = vco_optimal; in pll_get_post_div()
[all …]
/openbmc/linux/arch/x86/pci/
H A Dmmconfig-shared.c1 // SPDX-License-Identifier: GPL-2.0
3 * mmconfig-shared.c - Low-level direct PCI config space access via
4 * MMCONFIG - common code between i386 and x86-64.
7 * - known chipset handling
8 * - ACPI decoding and validation
10 * Per-architecture code takes care of the mappings and accesses
37 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) in pci_mmconfig_remove() argument
39 if (cfg->res.parent) in pci_mmconfig_remove()
40 release_resource(&cfg->res); in pci_mmconfig_remove()
41 list_del(&cfg->list); in pci_mmconfig_remove()
[all …]
/openbmc/u-boot/drivers/video/
H A Dssd2828.c1 // SPDX-License-Identifier: GPL-2.0+
109 #define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F)
112 * SPI transfer, using the "24-bit 3 wire" mode (that's how it is called in
113 * the SSD2828 documentation). The 'dout' input parameter specifies 24-bits
114 * of data to be written to SSD2828. Returns the lowest 16-bits of data,
133 gpio_set_value(drv->csx_pin, 0); in soft_spi_xfer_24bit_3wire()
135 for (j = bitlen - 1; j >= 0; j--) { in soft_spi_xfer_24bit_3wire()
136 gpio_set_value(drv->sck_pin, 0); in soft_spi_xfer_24bit_3wire()
137 gpio_set_value(drv->sdi_pin, (dout & (1 << j)) != 0); in soft_spi_xfer_24bit_3wire()
139 if (drv->sdo_pin != -1) in soft_spi_xfer_24bit_3wire()
[all …]
/openbmc/linux/drivers/net/wireless/microchip/wilc1000/
H A Dwlan_cfg.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
142 struct wilc_cfg *cfg = &wl->cfg; in wilc_wlan_parse_response_frame() local
150 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) in wilc_wlan_parse_response_frame()
153 if (cfg->b[i].id == wid) in wilc_wlan_parse_response_frame()
154 cfg->b[i].val = info[4]; in wilc_wlan_parse_response_frame()
160 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) in wilc_wlan_parse_response_frame()
163 if (cfg->hw[i].id == wid) in wilc_wlan_parse_response_frame()
164 cfg->hw[i].val = get_unaligned_le16(&info[4]); in wilc_wlan_parse_response_frame()
170 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) in wilc_wlan_parse_response_frame()
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
25 /*--------------------------CONFIG VALUES------------------------*/
121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
[all …]
/openbmc/linux/net/bridge/
H A Dbr_mdb.c1 // SPDX-License-Identifier: GPL-2.0
23 *timer = br_timer_value(&pmctx->ip4_mc_router_timer); in br_ip4_rports_get_timer()
24 return !hlist_unhashed(&pmctx->ip4_rlist); in br_ip4_rports_get_timer()
32 *timer = br_timer_value(&pmctx->ip6_mc_router_timer); in br_ip6_rports_get_timer()
33 return !hlist_unhashed(&pmctx->ip6_rlist); in br_ip6_rports_get_timer()
56 hlist_for_each_entry_rcu(pmctx, &brmctx->ip4_mc_router_list, in br_rports_size()
61 hlist_for_each_entry_rcu(pmctx, &brmctx->ip6_mc_router_list, in br_rports_size()
73 u16 vid = brmctx->vlan ? brmctx->vlan->vid : 0; in br_rports_fill_info()
79 if (!brmctx->multicast_router || !br_rports_have_mc_router(brmctx)) in br_rports_fill_info()
84 return -EMSGSIZE; in br_rports_fill_info()
[all …]
/openbmc/qemu/target/microblaze/
H A Dcpu.c5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
29 #include "hw/qdev-properties.h"
30 #include "exec/exec-all.h"
33 #include "fpu/softfloat-helpers.h"
85 cpu->env.pc = value; in mb_cpu_set_pc()
87 cpu->env.iflags = 0; in mb_cpu_set_pc()
94 return cpu->env.pc; in mb_cpu_get_pc()
103 cpu->env.pc = tb->pc; in mb_cpu_synchronize_from_tb()
104 cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; in mb_cpu_synchronize_from_tb()
[all …]
/openbmc/linux/drivers/scsi/cxlflash/
H A Dmain.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 * process_cmd_err() - command error handler
44 struct afu *afu = cmd->parent; in process_cmd_err()
45 struct cxlflash_cfg *cfg = afu->parent; in process_cmd_err() local
46 struct device *dev = &cfg->dev->dev; in process_cmd_err()
50 ioasa = &(cmd->sa); in process_cmd_err()
52 if (ioasa->rc.flags & SISL_RC_FLAGS_UNDERRUN) { in process_cmd_err()
53 resid = ioasa->resid; in process_cmd_err()
59 if (ioasa->rc.flags & SISL_RC_FLAGS_OVERRUN) { in process_cmd_err()
62 scp->result = (DID_ERROR << 16); in process_cmd_err()
[all …]
/openbmc/linux/sound/soc/intel/avs/
H A Dpath.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <sound/intel-nhlt.h>
17 /* Must be called with adev->comp_list_mutex held. */
23 list_for_each_entry(acomp, &adev->comp_list, node) in avs_path_find_tplg()
24 if (!strcmp(acomp->tplg->name, name)) in avs_path_find_tplg()
25 return acomp->tplg; in avs_path_find_tplg()
34 list_for_each_entry(mod, &ppl->mod_list, node) in avs_path_find_module()
35 if (mod->template->id == template_id) in avs_path_find_module()
45 list_for_each_entry(ppl, &path->ppl_list, node) in avs_path_find_pipeline()
46 if (ppl->template->id == template_id) in avs_path_find_pipeline()
[all …]
/openbmc/qemu/util/
H A Dthrottle.c4 * Copyright (C) Nodalink, EURL. 2013-2014
41 leak = (bkt->avg * (double) delta_ns) / NANOSECONDS_PER_SECOND; in throttle_leak_bucket()
44 bkt->level = MAX(bkt->level - leak, 0); in throttle_leak_bucket()
47 * keep track of bkt->burst_level so the bkt->max goal per second in throttle_leak_bucket()
49 if (bkt->burst_length > 1) { in throttle_leak_bucket()
50 leak = (bkt->max * (double) delta_ns) / NANOSECONDS_PER_SECOND; in throttle_leak_bucket()
51 bkt->burst_level = MAX(bkt->burst_level - leak, 0); in throttle_leak_bucket()
62 int64_t delta_ns = now - ts->previous_leak; in throttle_do_leak()
65 ts->previous_leak = now; in throttle_do_leak()
73 throttle_leak_bucket(&ts->cfg.buckets[i], delta_ns); in throttle_do_leak()
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/runtime/isys/src/
H A Dvirtual_isys.c1 // SPDX-License-Identifier: GPL-2.0
36 isp2401_input_system_cfg_t *cfg,
44 isp2401_input_system_cfg_t *cfg,
104 pixelgen_tpg_cfg_t *cfg);
110 pixelgen_prbs_cfg_t *cfg);
114 csi_rx_frontend_cfg_t *cfg);
120 csi_rx_backend_cfg_t *cfg);
125 stream2mmio_cfg_t *cfg);
131 ibuf_ctrl_cfg_t *cfg);
136 isys2401_dma_cfg_t *cfg);
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