1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2b8329acfSSiarhei Siamashka /*
3b8329acfSSiarhei Siamashka * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
4b8329acfSSiarhei Siamashka */
5b8329acfSSiarhei Siamashka
6b8329acfSSiarhei Siamashka /*
7b8329acfSSiarhei Siamashka * Support for the SSD2828 bridge chip, which can take pixel data coming
8b8329acfSSiarhei Siamashka * from a parallel LCD interface and translate it on the flight into MIPI DSI
9b8329acfSSiarhei Siamashka * interface for driving a MIPI compatible TFT display.
10b8329acfSSiarhei Siamashka */
11b8329acfSSiarhei Siamashka
12b8329acfSSiarhei Siamashka #include <common.h>
13b8329acfSSiarhei Siamashka #include <mipi_display.h>
14b8329acfSSiarhei Siamashka #include <asm/arch/gpio.h>
15b8329acfSSiarhei Siamashka #include <asm/gpio.h>
16b8329acfSSiarhei Siamashka
17b8329acfSSiarhei Siamashka #include "videomodes.h"
18b8329acfSSiarhei Siamashka #include "ssd2828.h"
19b8329acfSSiarhei Siamashka
20b8329acfSSiarhei Siamashka #define SSD2828_DIR 0xB0
21b8329acfSSiarhei Siamashka #define SSD2828_VICR1 0xB1
22b8329acfSSiarhei Siamashka #define SSD2828_VICR2 0xB2
23b8329acfSSiarhei Siamashka #define SSD2828_VICR3 0xB3
24b8329acfSSiarhei Siamashka #define SSD2828_VICR4 0xB4
25b8329acfSSiarhei Siamashka #define SSD2828_VICR5 0xB5
26b8329acfSSiarhei Siamashka #define SSD2828_VICR6 0xB6
27b8329acfSSiarhei Siamashka #define SSD2828_CFGR 0xB7
28b8329acfSSiarhei Siamashka #define SSD2828_VCR 0xB8
29b8329acfSSiarhei Siamashka #define SSD2828_PCR 0xB9
30b8329acfSSiarhei Siamashka #define SSD2828_PLCR 0xBA
31b8329acfSSiarhei Siamashka #define SSD2828_CCR 0xBB
32b8329acfSSiarhei Siamashka #define SSD2828_PSCR1 0xBC
33b8329acfSSiarhei Siamashka #define SSD2828_PSCR2 0xBD
34b8329acfSSiarhei Siamashka #define SSD2828_PSCR3 0xBE
35b8329acfSSiarhei Siamashka #define SSD2828_PDR 0xBF
36b8329acfSSiarhei Siamashka #define SSD2828_OCR 0xC0
37b8329acfSSiarhei Siamashka #define SSD2828_MRSR 0xC1
38b8329acfSSiarhei Siamashka #define SSD2828_RDCR 0xC2
39b8329acfSSiarhei Siamashka #define SSD2828_ARSR 0xC3
40b8329acfSSiarhei Siamashka #define SSD2828_LCR 0xC4
41b8329acfSSiarhei Siamashka #define SSD2828_ICR 0xC5
42b8329acfSSiarhei Siamashka #define SSD2828_ISR 0xC6
43b8329acfSSiarhei Siamashka #define SSD2828_ESR 0xC7
44b8329acfSSiarhei Siamashka #define SSD2828_DAR1 0xC9
45b8329acfSSiarhei Siamashka #define SSD2828_DAR2 0xCA
46b8329acfSSiarhei Siamashka #define SSD2828_DAR3 0xCB
47b8329acfSSiarhei Siamashka #define SSD2828_DAR4 0xCC
48b8329acfSSiarhei Siamashka #define SSD2828_DAR5 0xCD
49b8329acfSSiarhei Siamashka #define SSD2828_DAR6 0xCE
50b8329acfSSiarhei Siamashka #define SSD2828_HTTR1 0xCF
51b8329acfSSiarhei Siamashka #define SSD2828_HTTR2 0xD0
52b8329acfSSiarhei Siamashka #define SSD2828_LRTR1 0xD1
53b8329acfSSiarhei Siamashka #define SSD2828_LRTR2 0xD2
54b8329acfSSiarhei Siamashka #define SSD2828_TSR 0xD3
55b8329acfSSiarhei Siamashka #define SSD2828_LRR 0xD4
56b8329acfSSiarhei Siamashka #define SSD2828_PLLR 0xD5
57b8329acfSSiarhei Siamashka #define SSD2828_TR 0xD6
58b8329acfSSiarhei Siamashka #define SSD2828_TECR 0xD7
59b8329acfSSiarhei Siamashka #define SSD2828_ACR1 0xD8
60b8329acfSSiarhei Siamashka #define SSD2828_ACR2 0xD9
61b8329acfSSiarhei Siamashka #define SSD2828_ACR3 0xDA
62b8329acfSSiarhei Siamashka #define SSD2828_ACR4 0xDB
63b8329acfSSiarhei Siamashka #define SSD2828_IOCR 0xDC
64b8329acfSSiarhei Siamashka #define SSD2828_VICR7 0xDD
65b8329acfSSiarhei Siamashka #define SSD2828_LCFR 0xDE
66b8329acfSSiarhei Siamashka #define SSD2828_DAR7 0xDF
67b8329acfSSiarhei Siamashka #define SSD2828_PUCR1 0xE0
68b8329acfSSiarhei Siamashka #define SSD2828_PUCR2 0xE1
69b8329acfSSiarhei Siamashka #define SSD2828_PUCR3 0xE2
70b8329acfSSiarhei Siamashka #define SSD2828_CBCR1 0xE9
71b8329acfSSiarhei Siamashka #define SSD2828_CBCR2 0xEA
72b8329acfSSiarhei Siamashka #define SSD2828_CBSR 0xEB
73b8329acfSSiarhei Siamashka #define SSD2828_ECR 0xEC
74b8329acfSSiarhei Siamashka #define SSD2828_VSDR 0xED
75b8329acfSSiarhei Siamashka #define SSD2828_TMR 0xEE
76b8329acfSSiarhei Siamashka #define SSD2828_GPIO1 0xEF
77b8329acfSSiarhei Siamashka #define SSD2828_GPIO2 0xF0
78b8329acfSSiarhei Siamashka #define SSD2828_DLYA01 0xF1
79b8329acfSSiarhei Siamashka #define SSD2828_DLYA23 0xF2
80b8329acfSSiarhei Siamashka #define SSD2828_DLYB01 0xF3
81b8329acfSSiarhei Siamashka #define SSD2828_DLYB23 0xF4
82b8329acfSSiarhei Siamashka #define SSD2828_DLYC01 0xF5
83b8329acfSSiarhei Siamashka #define SSD2828_DLYC23 0xF6
84b8329acfSSiarhei Siamashka #define SSD2828_ACR5 0xF7
85b8329acfSSiarhei Siamashka #define SSD2828_RR 0xFF
86b8329acfSSiarhei Siamashka
87b8329acfSSiarhei Siamashka #define SSD2828_CFGR_HS (1 << 0)
88b8329acfSSiarhei Siamashka #define SSD2828_CFGR_CKE (1 << 1)
89b8329acfSSiarhei Siamashka #define SSD2828_CFGR_SLP (1 << 2)
90b8329acfSSiarhei Siamashka #define SSD2828_CFGR_VEN (1 << 3)
91b8329acfSSiarhei Siamashka #define SSD2828_CFGR_HCLK (1 << 4)
92b8329acfSSiarhei Siamashka #define SSD2828_CFGR_CSS (1 << 5)
93b8329acfSSiarhei Siamashka #define SSD2828_CFGR_DCS (1 << 6)
94b8329acfSSiarhei Siamashka #define SSD2828_CFGR_REN (1 << 7)
95b8329acfSSiarhei Siamashka #define SSD2828_CFGR_ECD (1 << 8)
96b8329acfSSiarhei Siamashka #define SSD2828_CFGR_EOT (1 << 9)
97b8329acfSSiarhei Siamashka #define SSD2828_CFGR_LPE (1 << 10)
98b8329acfSSiarhei Siamashka #define SSD2828_CFGR_TXD (1 << 11)
99b8329acfSSiarhei Siamashka
100b8329acfSSiarhei Siamashka #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2)
101b8329acfSSiarhei Siamashka #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2)
102b8329acfSSiarhei Siamashka #define SSD2828_VIDEO_MODE_BURST (2 << 2)
103b8329acfSSiarhei Siamashka
104b8329acfSSiarhei Siamashka #define SSD2828_VIDEO_PIXEL_FORMAT_16BPP 0
105b8329acfSSiarhei Siamashka #define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED 1
106b8329acfSSiarhei Siamashka #define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED 2
107b8329acfSSiarhei Siamashka #define SSD2828_VIDEO_PIXEL_FORMAT_24BPP 3
108b8329acfSSiarhei Siamashka
109b8329acfSSiarhei Siamashka #define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F)
110b8329acfSSiarhei Siamashka
111b8329acfSSiarhei Siamashka /*
112b8329acfSSiarhei Siamashka * SPI transfer, using the "24-bit 3 wire" mode (that's how it is called in
113b8329acfSSiarhei Siamashka * the SSD2828 documentation). The 'dout' input parameter specifies 24-bits
114b8329acfSSiarhei Siamashka * of data to be written to SSD2828. Returns the lowest 16-bits of data,
115b8329acfSSiarhei Siamashka * that is received back.
116b8329acfSSiarhei Siamashka */
soft_spi_xfer_24bit_3wire(const struct ssd2828_config * drv,u32 dout)117b8329acfSSiarhei Siamashka static u32 soft_spi_xfer_24bit_3wire(const struct ssd2828_config *drv, u32 dout)
118b8329acfSSiarhei Siamashka {
119b8329acfSSiarhei Siamashka int j, bitlen = 24;
120b8329acfSSiarhei Siamashka u32 tmpdin = 0;
121b8329acfSSiarhei Siamashka /*
122b8329acfSSiarhei Siamashka * According to the "24 Bit 3 Wire SPI Interface Timing Characteristics"
123b8329acfSSiarhei Siamashka * and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet,
124b8329acfSSiarhei Siamashka * the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs
125b8329acfSSiarhei Siamashka * at 1/8 of that after reset. So using 1 microsecond delays is safe in
126b8329acfSSiarhei Siamashka * the main loop. But the delays around chip select pin manipulations
127b8329acfSSiarhei Siamashka * need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in
128b8329acfSSiarhei Siamashka * the worst case).
129b8329acfSSiarhei Siamashka */
130b8329acfSSiarhei Siamashka const int spi_delay_us = 1;
131b8329acfSSiarhei Siamashka const int spi_cs_delay_us = 2;
132b8329acfSSiarhei Siamashka
133b8329acfSSiarhei Siamashka gpio_set_value(drv->csx_pin, 0);
134b8329acfSSiarhei Siamashka udelay(spi_cs_delay_us);
135b8329acfSSiarhei Siamashka for (j = bitlen - 1; j >= 0; j--) {
136b8329acfSSiarhei Siamashka gpio_set_value(drv->sck_pin, 0);
137b8329acfSSiarhei Siamashka gpio_set_value(drv->sdi_pin, (dout & (1 << j)) != 0);
138b8329acfSSiarhei Siamashka udelay(spi_delay_us);
139b8329acfSSiarhei Siamashka if (drv->sdo_pin != -1)
140b8329acfSSiarhei Siamashka tmpdin = (tmpdin << 1) | gpio_get_value(drv->sdo_pin);
141b8329acfSSiarhei Siamashka gpio_set_value(drv->sck_pin, 1);
142b8329acfSSiarhei Siamashka udelay(spi_delay_us);
143b8329acfSSiarhei Siamashka }
144b8329acfSSiarhei Siamashka udelay(spi_cs_delay_us);
145b8329acfSSiarhei Siamashka gpio_set_value(drv->csx_pin, 1);
146b8329acfSSiarhei Siamashka udelay(spi_cs_delay_us);
147b8329acfSSiarhei Siamashka return tmpdin & 0xFFFF;
148b8329acfSSiarhei Siamashka }
149b8329acfSSiarhei Siamashka
150b8329acfSSiarhei Siamashka /*
151b8329acfSSiarhei Siamashka * Read from a SSD2828 hardware register (regnum >= 0xB0)
152b8329acfSSiarhei Siamashka */
read_hw_register(const struct ssd2828_config * cfg,u8 regnum)153b8329acfSSiarhei Siamashka static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum)
154b8329acfSSiarhei Siamashka {
155b8329acfSSiarhei Siamashka soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
156b8329acfSSiarhei Siamashka return soft_spi_xfer_24bit_3wire(cfg, 0x730000);
157b8329acfSSiarhei Siamashka }
158b8329acfSSiarhei Siamashka
159b8329acfSSiarhei Siamashka /*
160b8329acfSSiarhei Siamashka * Write to a SSD2828 hardware register (regnum >= 0xB0)
161b8329acfSSiarhei Siamashka */
write_hw_register(const struct ssd2828_config * cfg,u8 regnum,u16 val)162b8329acfSSiarhei Siamashka static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum,
163b8329acfSSiarhei Siamashka u16 val)
164b8329acfSSiarhei Siamashka {
165b8329acfSSiarhei Siamashka soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
166b8329acfSSiarhei Siamashka soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val);
167b8329acfSSiarhei Siamashka }
168b8329acfSSiarhei Siamashka
169b8329acfSSiarhei Siamashka /*
170b8329acfSSiarhei Siamashka * Send MIPI command to the LCD panel (cmdnum < 0xB0)
171b8329acfSSiarhei Siamashka */
send_mipi_dcs_command(const struct ssd2828_config * cfg,u8 cmdnum)172b8329acfSSiarhei Siamashka static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum)
173b8329acfSSiarhei Siamashka {
174b8329acfSSiarhei Siamashka /* Set packet size to 1 (a single command with no parameters) */
175b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_PSCR1, 1);
176b8329acfSSiarhei Siamashka /* Send the command */
177b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_PDR, cmdnum);
178b8329acfSSiarhei Siamashka }
179b8329acfSSiarhei Siamashka
180b8329acfSSiarhei Siamashka /*
181b8329acfSSiarhei Siamashka * Reset SSD2828
182b8329acfSSiarhei Siamashka */
ssd2828_reset(const struct ssd2828_config * cfg)183b8329acfSSiarhei Siamashka static void ssd2828_reset(const struct ssd2828_config *cfg)
184b8329acfSSiarhei Siamashka {
185b8329acfSSiarhei Siamashka /* RESET needs 10 milliseconds according to the datasheet */
186b8329acfSSiarhei Siamashka gpio_set_value(cfg->reset_pin, 0);
187b8329acfSSiarhei Siamashka mdelay(10);
188b8329acfSSiarhei Siamashka gpio_set_value(cfg->reset_pin, 1);
189b8329acfSSiarhei Siamashka mdelay(10);
190b8329acfSSiarhei Siamashka }
191b8329acfSSiarhei Siamashka
ssd2828_enable_gpio(const struct ssd2828_config * cfg)192b8329acfSSiarhei Siamashka static int ssd2828_enable_gpio(const struct ssd2828_config *cfg)
193b8329acfSSiarhei Siamashka {
194b8329acfSSiarhei Siamashka if (gpio_request(cfg->csx_pin, "ssd2828_csx")) {
195b8329acfSSiarhei Siamashka printf("SSD2828: request for 'ssd2828_csx' pin failed\n");
196b8329acfSSiarhei Siamashka return 1;
197b8329acfSSiarhei Siamashka }
198b8329acfSSiarhei Siamashka if (gpio_request(cfg->sck_pin, "ssd2828_sck")) {
199b8329acfSSiarhei Siamashka gpio_free(cfg->csx_pin);
200b8329acfSSiarhei Siamashka printf("SSD2828: request for 'ssd2828_sck' pin failed\n");
201b8329acfSSiarhei Siamashka return 1;
202b8329acfSSiarhei Siamashka }
203b8329acfSSiarhei Siamashka if (gpio_request(cfg->sdi_pin, "ssd2828_sdi")) {
204b8329acfSSiarhei Siamashka gpio_free(cfg->csx_pin);
205b8329acfSSiarhei Siamashka gpio_free(cfg->sck_pin);
206b8329acfSSiarhei Siamashka printf("SSD2828: request for 'ssd2828_sdi' pin failed\n");
207b8329acfSSiarhei Siamashka return 1;
208b8329acfSSiarhei Siamashka }
209b8329acfSSiarhei Siamashka if (gpio_request(cfg->reset_pin, "ssd2828_reset")) {
210b8329acfSSiarhei Siamashka gpio_free(cfg->csx_pin);
211b8329acfSSiarhei Siamashka gpio_free(cfg->sck_pin);
212b8329acfSSiarhei Siamashka gpio_free(cfg->sdi_pin);
213b8329acfSSiarhei Siamashka printf("SSD2828: request for 'ssd2828_reset' pin failed\n");
214b8329acfSSiarhei Siamashka return 1;
215b8329acfSSiarhei Siamashka }
216b8329acfSSiarhei Siamashka if (cfg->sdo_pin != -1 && gpio_request(cfg->sdo_pin, "ssd2828_sdo")) {
217b8329acfSSiarhei Siamashka gpio_free(cfg->csx_pin);
218b8329acfSSiarhei Siamashka gpio_free(cfg->sck_pin);
219b8329acfSSiarhei Siamashka gpio_free(cfg->sdi_pin);
220b8329acfSSiarhei Siamashka gpio_free(cfg->reset_pin);
221b8329acfSSiarhei Siamashka printf("SSD2828: request for 'ssd2828_sdo' pin failed\n");
222b8329acfSSiarhei Siamashka return 1;
223b8329acfSSiarhei Siamashka }
224b8329acfSSiarhei Siamashka gpio_direction_output(cfg->reset_pin, 0);
225b8329acfSSiarhei Siamashka gpio_direction_output(cfg->csx_pin, 1);
226b8329acfSSiarhei Siamashka gpio_direction_output(cfg->sck_pin, 1);
227b8329acfSSiarhei Siamashka gpio_direction_output(cfg->sdi_pin, 1);
228b8329acfSSiarhei Siamashka if (cfg->sdo_pin != -1)
229b8329acfSSiarhei Siamashka gpio_direction_input(cfg->sdo_pin);
230b8329acfSSiarhei Siamashka
231b8329acfSSiarhei Siamashka return 0;
232b8329acfSSiarhei Siamashka }
233b8329acfSSiarhei Siamashka
ssd2828_free_gpio(const struct ssd2828_config * cfg)234b8329acfSSiarhei Siamashka static int ssd2828_free_gpio(const struct ssd2828_config *cfg)
235b8329acfSSiarhei Siamashka {
236b8329acfSSiarhei Siamashka gpio_free(cfg->csx_pin);
237b8329acfSSiarhei Siamashka gpio_free(cfg->sck_pin);
238b8329acfSSiarhei Siamashka gpio_free(cfg->sdi_pin);
239b8329acfSSiarhei Siamashka gpio_free(cfg->reset_pin);
240b8329acfSSiarhei Siamashka if (cfg->sdo_pin != -1)
241b8329acfSSiarhei Siamashka gpio_free(cfg->sdo_pin);
242b8329acfSSiarhei Siamashka return 1;
243b8329acfSSiarhei Siamashka }
244b8329acfSSiarhei Siamashka
245b8329acfSSiarhei Siamashka /*
246b8329acfSSiarhei Siamashka * PLL configuration register settings.
247b8329acfSSiarhei Siamashka *
248b8329acfSSiarhei Siamashka * See the "PLL Configuration Register Description" in the SSD2828 datasheet.
249b8329acfSSiarhei Siamashka */
construct_pll_config(u32 desired_pll_freq_kbps,u32 reference_freq_khz)250b8329acfSSiarhei Siamashka static u32 construct_pll_config(u32 desired_pll_freq_kbps,
251b8329acfSSiarhei Siamashka u32 reference_freq_khz)
252b8329acfSSiarhei Siamashka {
253b8329acfSSiarhei Siamashka u32 div_factor = 1, mul_factor, fr = 0;
254b8329acfSSiarhei Siamashka u32 output_freq_kbps;
255b8329acfSSiarhei Siamashka
256b8329acfSSiarhei Siamashka /* The intermediate clock after division can't be less than 5MHz */
257b8329acfSSiarhei Siamashka while (reference_freq_khz / (div_factor + 1) >= 5000)
258b8329acfSSiarhei Siamashka div_factor++;
259b8329acfSSiarhei Siamashka if (div_factor > 31)
260b8329acfSSiarhei Siamashka div_factor = 31;
261b8329acfSSiarhei Siamashka
262b8329acfSSiarhei Siamashka mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
263b8329acfSSiarhei Siamashka reference_freq_khz);
264b8329acfSSiarhei Siamashka
265b8329acfSSiarhei Siamashka output_freq_kbps = reference_freq_khz * mul_factor / div_factor;
266b8329acfSSiarhei Siamashka
267b8329acfSSiarhei Siamashka if (output_freq_kbps >= 501000)
268b8329acfSSiarhei Siamashka fr = 3;
269b8329acfSSiarhei Siamashka else if (output_freq_kbps >= 251000)
270b8329acfSSiarhei Siamashka fr = 2;
271b8329acfSSiarhei Siamashka else if (output_freq_kbps >= 126000)
272b8329acfSSiarhei Siamashka fr = 1;
273b8329acfSSiarhei Siamashka
274b8329acfSSiarhei Siamashka return (fr << 14) | (div_factor << 8) | mul_factor;
275b8329acfSSiarhei Siamashka }
276b8329acfSSiarhei Siamashka
decode_pll_config(u32 pll_config,u32 reference_freq_khz)277b8329acfSSiarhei Siamashka static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz)
278b8329acfSSiarhei Siamashka {
279b8329acfSSiarhei Siamashka u32 mul_factor = pll_config & 0xFF;
280b8329acfSSiarhei Siamashka u32 div_factor = (pll_config >> 8) & 0x1F;
281b8329acfSSiarhei Siamashka if (mul_factor == 0)
282b8329acfSSiarhei Siamashka mul_factor = 1;
283b8329acfSSiarhei Siamashka if (div_factor == 0)
284b8329acfSSiarhei Siamashka div_factor = 1;
285b8329acfSSiarhei Siamashka return reference_freq_khz * mul_factor / div_factor;
286b8329acfSSiarhei Siamashka }
287b8329acfSSiarhei Siamashka
ssd2828_configure_video_interface(const struct ssd2828_config * cfg,const struct ctfb_res_modes * mode)288b8329acfSSiarhei Siamashka static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg,
289b8329acfSSiarhei Siamashka const struct ctfb_res_modes *mode)
290b8329acfSSiarhei Siamashka {
291b8329acfSSiarhei Siamashka u32 val;
292b8329acfSSiarhei Siamashka
293b8329acfSSiarhei Siamashka /* RGB Interface Control Register 1 */
294b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_VICR1, (mode->vsync_len << 8) |
295b8329acfSSiarhei Siamashka (mode->hsync_len));
296b8329acfSSiarhei Siamashka
297b8329acfSSiarhei Siamashka /* RGB Interface Control Register 2 */
298b8329acfSSiarhei Siamashka u32 vbp = mode->vsync_len + mode->upper_margin;
299b8329acfSSiarhei Siamashka u32 hbp = mode->hsync_len + mode->left_margin;
300b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_VICR2, (vbp << 8) | hbp);
301b8329acfSSiarhei Siamashka
302b8329acfSSiarhei Siamashka /* RGB Interface Control Register 3 */
303b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_VICR3, (mode->lower_margin << 8) |
304b8329acfSSiarhei Siamashka (mode->right_margin));
305b8329acfSSiarhei Siamashka
306b8329acfSSiarhei Siamashka /* RGB Interface Control Register 4 */
307b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_VICR4, mode->xres);
308b8329acfSSiarhei Siamashka
309b8329acfSSiarhei Siamashka /* RGB Interface Control Register 5 */
310b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_VICR5, mode->yres);
311b8329acfSSiarhei Siamashka
312b8329acfSSiarhei Siamashka /* RGB Interface Control Register 6 */
313b8329acfSSiarhei Siamashka val = SSD2828_VIDEO_MODE_BURST;
314b8329acfSSiarhei Siamashka switch (cfg->ssd2828_color_depth) {
315b8329acfSSiarhei Siamashka case 16:
316b8329acfSSiarhei Siamashka val |= SSD2828_VIDEO_PIXEL_FORMAT_16BPP;
317b8329acfSSiarhei Siamashka break;
318b8329acfSSiarhei Siamashka case 18:
319b8329acfSSiarhei Siamashka val |= cfg->mipi_dsi_loosely_packed_pixel_format ?
320b8329acfSSiarhei Siamashka SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED :
321b8329acfSSiarhei Siamashka SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED;
322b8329acfSSiarhei Siamashka break;
323b8329acfSSiarhei Siamashka case 24:
324b8329acfSSiarhei Siamashka val |= SSD2828_VIDEO_PIXEL_FORMAT_24BPP;
325b8329acfSSiarhei Siamashka break;
326b8329acfSSiarhei Siamashka default:
327b8329acfSSiarhei Siamashka printf("SSD2828: unsupported color depth\n");
328b8329acfSSiarhei Siamashka return 1;
329b8329acfSSiarhei Siamashka }
330b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_VICR6, val);
331b8329acfSSiarhei Siamashka
332b8329acfSSiarhei Siamashka /* Lane Configuration Register */
333b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_LCFR,
334b8329acfSSiarhei Siamashka cfg->mipi_dsi_number_of_data_lanes - 1);
335b8329acfSSiarhei Siamashka
336b8329acfSSiarhei Siamashka return 0;
337b8329acfSSiarhei Siamashka }
338b8329acfSSiarhei Siamashka
ssd2828_init(const struct ssd2828_config * cfg,const struct ctfb_res_modes * mode)339b8329acfSSiarhei Siamashka int ssd2828_init(const struct ssd2828_config *cfg,
340b8329acfSSiarhei Siamashka const struct ctfb_res_modes *mode)
341b8329acfSSiarhei Siamashka {
342dddccd69SSiarhei Siamashka u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config;
343b8329acfSSiarhei Siamashka /* The LP clock speed is limited by 10MHz */
344b8329acfSSiarhei Siamashka const u32 mipi_dsi_low_power_clk_khz = 10000;
345b8329acfSSiarhei Siamashka /*
346b8329acfSSiarhei Siamashka * This is just the reset default value of CFGR register (0x301).
347b8329acfSSiarhei Siamashka * Because we are not always able to read back from SPI, have
348b8329acfSSiarhei Siamashka * it initialized here.
349b8329acfSSiarhei Siamashka */
350b8329acfSSiarhei Siamashka u32 cfgr_reg = SSD2828_CFGR_EOT | /* EOT Packet Enable */
351b8329acfSSiarhei Siamashka SSD2828_CFGR_ECD | /* Disable ECC and CRC */
352b8329acfSSiarhei Siamashka SSD2828_CFGR_HS; /* Data lanes are in HS mode */
353b8329acfSSiarhei Siamashka
354b8329acfSSiarhei Siamashka /* Initialize the pins */
355b8329acfSSiarhei Siamashka if (ssd2828_enable_gpio(cfg) != 0)
356b8329acfSSiarhei Siamashka return 1;
357b8329acfSSiarhei Siamashka
358b8329acfSSiarhei Siamashka /* Reset the chip */
359b8329acfSSiarhei Siamashka ssd2828_reset(cfg);
360b8329acfSSiarhei Siamashka
361b8329acfSSiarhei Siamashka /*
362b8329acfSSiarhei Siamashka * If there is a pin to read data back from SPI, then we are lucky. Try
363b8329acfSSiarhei Siamashka * to check if SPI is configured correctly and SSD2828 is actually able
364b8329acfSSiarhei Siamashka * to talk back.
365b8329acfSSiarhei Siamashka */
366b8329acfSSiarhei Siamashka if (cfg->sdo_pin != -1) {
367b8329acfSSiarhei Siamashka if (read_hw_register(cfg, SSD2828_DIR) != 0x2828 ||
368b8329acfSSiarhei Siamashka read_hw_register(cfg, SSD2828_CFGR) != cfgr_reg) {
369b8329acfSSiarhei Siamashka printf("SSD2828: SPI communication failed.\n");
370b8329acfSSiarhei Siamashka ssd2828_free_gpio(cfg);
371b8329acfSSiarhei Siamashka return 1;
372b8329acfSSiarhei Siamashka }
373b8329acfSSiarhei Siamashka }
374b8329acfSSiarhei Siamashka
375b8329acfSSiarhei Siamashka /*
376dddccd69SSiarhei Siamashka * Pick the reference clock for PLL. If we know the exact 'tx_clk'
377dddccd69SSiarhei Siamashka * clock speed, then everything is good. If not, then we can fallback
378dddccd69SSiarhei Siamashka * to 'pclk' (pixel clock from the parallel LCD interface). In the
379dddccd69SSiarhei Siamashka * case of using this fallback, it is necessary to have parallel LCD
380dddccd69SSiarhei Siamashka * already initialized and running at this point.
381dddccd69SSiarhei Siamashka */
382dddccd69SSiarhei Siamashka reference_freq_khz = cfg->ssd2828_tx_clk_khz;
383dddccd69SSiarhei Siamashka if (reference_freq_khz == 0) {
384dddccd69SSiarhei Siamashka reference_freq_khz = mode->pixclock_khz;
385dddccd69SSiarhei Siamashka /* Use 'pclk' as the reference clock for PLL */
386dddccd69SSiarhei Siamashka cfgr_reg |= SSD2828_CFGR_CSS;
387dddccd69SSiarhei Siamashka }
388dddccd69SSiarhei Siamashka
389dddccd69SSiarhei Siamashka /*
390b8329acfSSiarhei Siamashka * Setup the parallel LCD timings in the appropriate registers.
391b8329acfSSiarhei Siamashka */
392b8329acfSSiarhei Siamashka if (ssd2828_configure_video_interface(cfg, mode) != 0) {
393b8329acfSSiarhei Siamashka ssd2828_free_gpio(cfg);
394b8329acfSSiarhei Siamashka return 1;
395b8329acfSSiarhei Siamashka }
396b8329acfSSiarhei Siamashka
397b8329acfSSiarhei Siamashka /* Configuration Register */
398b8329acfSSiarhei Siamashka cfgr_reg &= ~SSD2828_CFGR_HS; /* Data lanes are in LP mode */
399b8329acfSSiarhei Siamashka cfgr_reg |= SSD2828_CFGR_CKE; /* Clock lane is in HS mode */
400b8329acfSSiarhei Siamashka cfgr_reg |= SSD2828_CFGR_DCS; /* Only use DCS packets */
401b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
402b8329acfSSiarhei Siamashka
403b8329acfSSiarhei Siamashka /* PLL Configuration Register */
404b8329acfSSiarhei Siamashka pll_config = construct_pll_config(
405b8329acfSSiarhei Siamashka cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000,
406dddccd69SSiarhei Siamashka reference_freq_khz);
407b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_PLCR, pll_config);
408b8329acfSSiarhei Siamashka
409dddccd69SSiarhei Siamashka pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz);
410b8329acfSSiarhei Siamashka lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8);
411b8329acfSSiarhei Siamashka
412b8329acfSSiarhei Siamashka /* VC Control Register */
413b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_VCR, 0);
414b8329acfSSiarhei Siamashka
415b8329acfSSiarhei Siamashka /* Clock Control Register */
416b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_CCR, SSD2828_LP_CLOCK_DIVIDER(lp_div));
417b8329acfSSiarhei Siamashka
418b8329acfSSiarhei Siamashka /* PLL Control Register */
419b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_PCR, 1); /* Enable PLL */
420b8329acfSSiarhei Siamashka
421b8329acfSSiarhei Siamashka /* Wait for PLL lock */
422b8329acfSSiarhei Siamashka udelay(500);
423b8329acfSSiarhei Siamashka
424b8329acfSSiarhei Siamashka send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE);
425b8329acfSSiarhei Siamashka mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms);
426b8329acfSSiarhei Siamashka
427b8329acfSSiarhei Siamashka send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON);
428b8329acfSSiarhei Siamashka mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms);
429b8329acfSSiarhei Siamashka
430b8329acfSSiarhei Siamashka cfgr_reg |= SSD2828_CFGR_HS; /* Enable HS mode for data lanes */
431b8329acfSSiarhei Siamashka cfgr_reg |= SSD2828_CFGR_VEN; /* Enable video pipeline */
432b8329acfSSiarhei Siamashka write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
433b8329acfSSiarhei Siamashka
434b8329acfSSiarhei Siamashka return 0;
435b8329acfSSiarhei Siamashka }
436