1862cd659SVeerasenareddy Burru /* SPDX-License-Identifier: GPL-2.0 */ 2862cd659SVeerasenareddy Burru /* Marvell Octeon EP (EndPoint) Ethernet Driver 3862cd659SVeerasenareddy Burru * 4862cd659SVeerasenareddy Burru * Copyright (C) 2020 Marvell. 5862cd659SVeerasenareddy Burru * 6862cd659SVeerasenareddy Burru */ 7862cd659SVeerasenareddy Burru 8862cd659SVeerasenareddy Burru #ifndef _OCTEP_CONFIG_H_ 9862cd659SVeerasenareddy Burru #define _OCTEP_CONFIG_H_ 10862cd659SVeerasenareddy Burru 11862cd659SVeerasenareddy Burru /* Tx instruction types by length */ 12862cd659SVeerasenareddy Burru #define OCTEP_32BYTE_INSTR 32 13862cd659SVeerasenareddy Burru #define OCTEP_64BYTE_INSTR 64 14862cd659SVeerasenareddy Burru 15862cd659SVeerasenareddy Burru /* Tx Queue: maximum descriptors per ring */ 16862cd659SVeerasenareddy Burru #define OCTEP_IQ_MAX_DESCRIPTORS 1024 17862cd659SVeerasenareddy Burru /* Minimum input (Tx) requests to be enqueued to ring doorbell */ 18862cd659SVeerasenareddy Burru #define OCTEP_DB_MIN 1 19862cd659SVeerasenareddy Burru /* Packet threshold for Tx queue interrupt */ 20862cd659SVeerasenareddy Burru #define OCTEP_IQ_INTR_THRESHOLD 0x0 21862cd659SVeerasenareddy Burru 22862cd659SVeerasenareddy Burru /* Rx Queue: maximum descriptors per ring */ 23862cd659SVeerasenareddy Burru #define OCTEP_OQ_MAX_DESCRIPTORS 1024 24862cd659SVeerasenareddy Burru 25862cd659SVeerasenareddy Burru /* Rx buffer size: Use page size buffers. 26862cd659SVeerasenareddy Burru * Build skb from allocated page buffer once the packet is received. 27862cd659SVeerasenareddy Burru * When a gathered packet is received, make head page as skb head and 28862cd659SVeerasenareddy Burru * page buffers in consecutive Rx descriptors as fragments. 29862cd659SVeerasenareddy Burru */ 30862cd659SVeerasenareddy Burru #define OCTEP_OQ_BUF_SIZE (SKB_WITH_OVERHEAD(PAGE_SIZE)) 31862cd659SVeerasenareddy Burru #define OCTEP_OQ_PKTS_PER_INTR 128 32862cd659SVeerasenareddy Burru #define OCTEP_OQ_REFILL_THRESHOLD (OCTEP_OQ_MAX_DESCRIPTORS / 4) 33862cd659SVeerasenareddy Burru 34862cd659SVeerasenareddy Burru #define OCTEP_OQ_INTR_PKT_THRESHOLD 1 35862cd659SVeerasenareddy Burru #define OCTEP_OQ_INTR_TIME_THRESHOLD 10 36862cd659SVeerasenareddy Burru 37862cd659SVeerasenareddy Burru #define OCTEP_MSIX_NAME_SIZE (IFNAMSIZ + 32) 38862cd659SVeerasenareddy Burru 39862cd659SVeerasenareddy Burru /* Tx Queue wake threshold 40862cd659SVeerasenareddy Burru * wakeup a stopped Tx queue if minimum 2 descriptors are available. 41862cd659SVeerasenareddy Burru * Even a skb with fragments consume only one Tx queue descriptor entry. 42862cd659SVeerasenareddy Burru */ 43862cd659SVeerasenareddy Burru #define OCTEP_WAKE_QUEUE_THRESHOLD 2 44862cd659SVeerasenareddy Burru 45862cd659SVeerasenareddy Burru /* Minimum MTU supported by Octeon network interface */ 46862cd659SVeerasenareddy Burru #define OCTEP_MIN_MTU ETH_MIN_MTU 47862cd659SVeerasenareddy Burru /* Maximum MTU supported by Octeon interface*/ 48862cd659SVeerasenareddy Burru #define OCTEP_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN)) 49862cd659SVeerasenareddy Burru /* Default MTU */ 50862cd659SVeerasenareddy Burru #define OCTEP_DEFAULT_MTU 1500 51862cd659SVeerasenareddy Burru 52862cd659SVeerasenareddy Burru /* Macros to get octeon config params */ 53862cd659SVeerasenareddy Burru #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) 54862cd659SVeerasenareddy Burru #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) 55862cd659SVeerasenareddy Burru #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) 56862cd659SVeerasenareddy Burru #define CFG_GET_IQ_PKIND(cfg) ((cfg)->iq.pkind) 57862cd659SVeerasenareddy Burru #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) 58862cd659SVeerasenareddy Burru #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) 59862cd659SVeerasenareddy Burru #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) 60862cd659SVeerasenareddy Burru 61862cd659SVeerasenareddy Burru #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) 62862cd659SVeerasenareddy Burru #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) 63862cd659SVeerasenareddy Burru #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) 64862cd659SVeerasenareddy Burru #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) 65862cd659SVeerasenareddy Burru #define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time) 66862cd659SVeerasenareddy Burru 67862cd659SVeerasenareddy Burru #define CFG_GET_PORTS_MAX_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.max_io_rings) 68862cd659SVeerasenareddy Burru #define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.active_io_rings) 69862cd659SVeerasenareddy Burru #define CFG_GET_PORTS_PF_SRN(cfg) ((cfg)->pf_ring_cfg.srn) 70862cd659SVeerasenareddy Burru 71862cd659SVeerasenareddy Burru #define CFG_GET_DPI_PKIND(cfg) ((cfg)->core_cfg.dpi_pkind) 72862cd659SVeerasenareddy Burru #define CFG_GET_CORE_TICS_PER_US(cfg) ((cfg)->core_cfg.core_tics_per_us) 73862cd659SVeerasenareddy Burru #define CFG_GET_COPROC_TICS_PER_US(cfg) ((cfg)->core_cfg.coproc_tics_per_us) 74862cd659SVeerasenareddy Burru 75862cd659SVeerasenareddy Burru #define CFG_GET_MAX_VFS(cfg) ((cfg)->sriov_cfg.max_vfs) 76862cd659SVeerasenareddy Burru #define CFG_GET_ACTIVE_VFS(cfg) ((cfg)->sriov_cfg.active_vfs) 77862cd659SVeerasenareddy Burru #define CFG_GET_MAX_RPVF(cfg) ((cfg)->sriov_cfg.max_rings_per_vf) 78862cd659SVeerasenareddy Burru #define CFG_GET_ACTIVE_RPVF(cfg) ((cfg)->sriov_cfg.active_rings_per_vf) 79862cd659SVeerasenareddy Burru #define CFG_GET_VF_SRN(cfg) ((cfg)->sriov_cfg.vf_srn) 80862cd659SVeerasenareddy Burru 81862cd659SVeerasenareddy Burru #define CFG_GET_IOQ_MSIX(cfg) ((cfg)->msix_cfg.ioq_msix) 82862cd659SVeerasenareddy Burru #define CFG_GET_NON_IOQ_MSIX(cfg) ((cfg)->msix_cfg.non_ioq_msix) 83862cd659SVeerasenareddy Burru #define CFG_GET_NON_IOQ_MSIX_NAMES(cfg) ((cfg)->msix_cfg.non_ioq_msix_names) 84862cd659SVeerasenareddy Burru 85862cd659SVeerasenareddy Burru #define CFG_GET_CTRL_MBOX_MEM_ADDR(cfg) ((cfg)->ctrl_mbox_cfg.barmem_addr) 86862cd659SVeerasenareddy Burru 87862cd659SVeerasenareddy Burru /* Hardware Tx Queue configuration. */ 88862cd659SVeerasenareddy Burru struct octep_iq_config { 89862cd659SVeerasenareddy Burru /* Size of the Input queue (number of commands) */ 90862cd659SVeerasenareddy Burru u16 num_descs; 91862cd659SVeerasenareddy Burru 92862cd659SVeerasenareddy Burru /* Command size - 32 or 64 bytes */ 93862cd659SVeerasenareddy Burru u16 instr_type; 94862cd659SVeerasenareddy Burru 95862cd659SVeerasenareddy Burru /* pkind for packets sent to Octeon */ 96862cd659SVeerasenareddy Burru u16 pkind; 97862cd659SVeerasenareddy Burru 98862cd659SVeerasenareddy Burru /* Minimum number of commands pending to be posted to Octeon before driver 99862cd659SVeerasenareddy Burru * hits the Input queue doorbell. 100862cd659SVeerasenareddy Burru */ 101862cd659SVeerasenareddy Burru u16 db_min; 102862cd659SVeerasenareddy Burru 103862cd659SVeerasenareddy Burru /* Trigger the IQ interrupt when processed cmd count reaches 104862cd659SVeerasenareddy Burru * this level. 105862cd659SVeerasenareddy Burru */ 106862cd659SVeerasenareddy Burru u32 intr_threshold; 107862cd659SVeerasenareddy Burru }; 108862cd659SVeerasenareddy Burru 109862cd659SVeerasenareddy Burru /* Hardware Rx Queue configuration. */ 110862cd659SVeerasenareddy Burru struct octep_oq_config { 111862cd659SVeerasenareddy Burru /* Size of Output queue (number of descriptors) */ 112862cd659SVeerasenareddy Burru u16 num_descs; 113862cd659SVeerasenareddy Burru 114862cd659SVeerasenareddy Burru /* Size of buffer in this Output queue. */ 115862cd659SVeerasenareddy Burru u16 buf_size; 116862cd659SVeerasenareddy Burru 117862cd659SVeerasenareddy Burru /* The number of buffers that were consumed during packet processing 118862cd659SVeerasenareddy Burru * by the driver on this Output queue before the driver attempts to 119862cd659SVeerasenareddy Burru * replenish the descriptor ring with new buffers. 120862cd659SVeerasenareddy Burru */ 121862cd659SVeerasenareddy Burru u16 refill_threshold; 122862cd659SVeerasenareddy Burru 123862cd659SVeerasenareddy Burru /* Interrupt Coalescing (Packet Count). Octeon will interrupt the host 124862cd659SVeerasenareddy Burru * only if it sent as many packets as specified by this field. 125862cd659SVeerasenareddy Burru * The driver usually does not use packet count interrupt coalescing. 126862cd659SVeerasenareddy Burru */ 127862cd659SVeerasenareddy Burru u32 oq_intr_pkt; 128862cd659SVeerasenareddy Burru 129862cd659SVeerasenareddy Burru /* Interrupt Coalescing (Time Interval). Octeon will interrupt the host 130862cd659SVeerasenareddy Burru * if at least one packet was sent in the time interval specified by 131862cd659SVeerasenareddy Burru * this field. The driver uses time interval interrupt coalescing by 132862cd659SVeerasenareddy Burru * default. The time is specified in microseconds. 133862cd659SVeerasenareddy Burru */ 134862cd659SVeerasenareddy Burru u32 oq_intr_time; 135862cd659SVeerasenareddy Burru }; 136862cd659SVeerasenareddy Burru 137862cd659SVeerasenareddy Burru /* Tx/Rx configuration */ 138862cd659SVeerasenareddy Burru struct octep_pf_ring_config { 139862cd659SVeerasenareddy Burru /* Max number of IOQs */ 140862cd659SVeerasenareddy Burru u16 max_io_rings; 141862cd659SVeerasenareddy Burru 142862cd659SVeerasenareddy Burru /* Number of active IOQs */ 143862cd659SVeerasenareddy Burru u16 active_io_rings; 144862cd659SVeerasenareddy Burru 145862cd659SVeerasenareddy Burru /* Starting IOQ number: this changes based on which PEM is used */ 146862cd659SVeerasenareddy Burru u16 srn; 147862cd659SVeerasenareddy Burru }; 148862cd659SVeerasenareddy Burru 149862cd659SVeerasenareddy Burru /* Octeon Hardware SRIOV config */ 150862cd659SVeerasenareddy Burru struct octep_sriov_config { 151862cd659SVeerasenareddy Burru /* Max number of VF devices supported */ 152862cd659SVeerasenareddy Burru u16 max_vfs; 153862cd659SVeerasenareddy Burru 154862cd659SVeerasenareddy Burru /* Number of VF devices enabled */ 155862cd659SVeerasenareddy Burru u16 active_vfs; 156862cd659SVeerasenareddy Burru 157862cd659SVeerasenareddy Burru /* Max number of rings assigned to VF */ 158862cd659SVeerasenareddy Burru u8 max_rings_per_vf; 159862cd659SVeerasenareddy Burru 160862cd659SVeerasenareddy Burru /* Number of rings enabled per VF */ 161862cd659SVeerasenareddy Burru u8 active_rings_per_vf; 162862cd659SVeerasenareddy Burru 163862cd659SVeerasenareddy Burru /* starting ring number of VF's: ring-0 of VF-0 of the PF */ 164862cd659SVeerasenareddy Burru u16 vf_srn; 165862cd659SVeerasenareddy Burru }; 166862cd659SVeerasenareddy Burru 167862cd659SVeerasenareddy Burru /* Octeon MSI-x config. */ 168862cd659SVeerasenareddy Burru struct octep_msix_config { 169862cd659SVeerasenareddy Burru /* Number of IOQ interrupts */ 170862cd659SVeerasenareddy Burru u16 ioq_msix; 171862cd659SVeerasenareddy Burru 172862cd659SVeerasenareddy Burru /* Number of Non IOQ interrupts */ 173862cd659SVeerasenareddy Burru u16 non_ioq_msix; 174862cd659SVeerasenareddy Burru 175862cd659SVeerasenareddy Burru /* Names of Non IOQ interrupts */ 176862cd659SVeerasenareddy Burru char **non_ioq_msix_names; 177862cd659SVeerasenareddy Burru }; 178862cd659SVeerasenareddy Burru 179862cd659SVeerasenareddy Burru struct octep_ctrl_mbox_config { 180862cd659SVeerasenareddy Burru /* Barmem address for control mbox */ 181862cd659SVeerasenareddy Burru void __iomem *barmem_addr; 182862cd659SVeerasenareddy Burru }; 183862cd659SVeerasenareddy Burru 184862cd659SVeerasenareddy Burru /* Data Structure to hold configuration limits and active config */ 185862cd659SVeerasenareddy Burru struct octep_config { 186862cd659SVeerasenareddy Burru /* Input Queue attributes. */ 187862cd659SVeerasenareddy Burru struct octep_iq_config iq; 188862cd659SVeerasenareddy Burru 189862cd659SVeerasenareddy Burru /* Output Queue attributes. */ 190862cd659SVeerasenareddy Burru struct octep_oq_config oq; 191862cd659SVeerasenareddy Burru 192862cd659SVeerasenareddy Burru /* NIC Port Configuration */ 193862cd659SVeerasenareddy Burru struct octep_pf_ring_config pf_ring_cfg; 194862cd659SVeerasenareddy Burru 195862cd659SVeerasenareddy Burru /* SRIOV configuration of the PF */ 196862cd659SVeerasenareddy Burru struct octep_sriov_config sriov_cfg; 197862cd659SVeerasenareddy Burru 198862cd659SVeerasenareddy Burru /* MSI-X interrupt config */ 199862cd659SVeerasenareddy Burru struct octep_msix_config msix_cfg; 200862cd659SVeerasenareddy Burru 201862cd659SVeerasenareddy Burru /* ctrl mbox config */ 202862cd659SVeerasenareddy Burru struct octep_ctrl_mbox_config ctrl_mbox_cfg; 203*5cb96c29SVeerasenareddy Burru 204*5cb96c29SVeerasenareddy Burru /* Configured maximum heartbeat miss count */ 205*5cb96c29SVeerasenareddy Burru u32 max_hb_miss_cnt; 206*5cb96c29SVeerasenareddy Burru 207*5cb96c29SVeerasenareddy Burru /* Configured firmware heartbeat interval in secs */ 208*5cb96c29SVeerasenareddy Burru u32 hb_interval; 209862cd659SVeerasenareddy Burru }; 210862cd659SVeerasenareddy Burru #endif /* _OCTEP_CONFIG_H_ */ 211