The patch introduces the CRITICAL feature of POST tests. If the test
marked as POST_CRITICAL fails then the alternative, post_critical,
boot-command is used. If this command is not defined then U-Boo

The patch introduces the CRITICAL feature of POST tests. If the test
marked as POST_CRITICAL fails then the alternative, post_critical,
boot-command is used. If this command is not defined then U-Boot
enters into interactive mode.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

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The patch adds new POST tests for the Lwmon5 board.
These are:

* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Sig

The patch adds new POST tests for the Lwmon5 board.
These are:

* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

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Enable CODEC POST with CFG_POST_CODEC rather than with CFG_POST_DSP.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>

ppc4xx: program_tlb now uses 64bit physical addess

This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB

ppc4xx: program_tlb now uses 64bit physical addess

This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).

Signed-off-by: Stefan Roese <sr@denx.de>

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Fix warnings while compilation of post/drivers/memory.c

Fix warnings while compilation with new gcc in eldk-4.2

Signed-off-by: Anatolij Gustschin <agust@denx.de>

POST: Disable cache while SPR POST

Currently (since commit b2e2142c) u-boot crashes on
sequoia board while SPR test if CONFIG_4xx_DCACHE is
enabled. This patch disables the cache while SPR test.

Si

POST: Disable cache while SPR POST

Currently (since commit b2e2142c) u-boot crashes on
sequoia board while SPR test if CONFIG_4xx_DCACHE is
enabled. This patch disables the cache while SPR test.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

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Fix CPU POST test failure

The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the
ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered
by it. The gcc-4.2 with its

Fix CPU POST test failure

The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the
ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered
by it. The gcc-4.2 with its more aggressive optimization exposes this fact.
This patch just saves the CR value before running the test code, so allowing
it to do anything it wants with CR.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Acked-by: Yuri Tikhonov <yur@emcraft.com>
--

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Add attribute POST_PREREL to ECC memory POST

Signed-off-by: Larry Johnson <lrj@acm.org>

ppc4xx: Refactor ECC POST for AMCC Denali core

The ECC POST reported intermittent failures running after power-up on
the Korat PPC440EPx board. Even when the test passed, the debugging
output occas

ppc4xx: Refactor ECC POST for AMCC Denali core

The ECC POST reported intermittent failures running after power-up on
the Korat PPC440EPx board. Even when the test passed, the debugging
output occasionally reported additional unexpected ECC errors.

This refactoring has three main objectives: (1) minimize the code
executed with ECC enabled during the tests, (2) add more checking of the
results so any unexpected ECC errors would cause the test to fail, and
(3) use synchronization (only) where required by the processor.

Signed-off-by: Larry Johnson <lrj@acm.org>

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ppc_4xx: Fix post spr.c for PPC405

post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.co

ppc_4xx: Fix post spr.c for PPC405

post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>

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POST: Execute SPR test after relocation

On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses
self modifying code and this doesn't work with stack in d-cache, since
I can't move

POST: Execute SPR test after relocation

On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses
self modifying code and this doesn't work with stack in d-cache, since
I can't move the code from d-cache to i-cache. We move the SPR test to
be executed a little later, after relocation. Then stack is located in
SDRAM and this self-modifying code is no problem anymore.

Signed-off-by: Stefan Roese <sr@denx.de>

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Cosmetic changes to ECC POST for AMCC Denali core

Signed-off-by: Larry Johnson <lrj@acm.org>

ppc4xx: Fix compilation problem in 405 cache POST test

Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Fix problem in 44x cache POST routine

As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for th

ppc4xx: Fix problem in 44x cache POST routine

As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for the cache test after the test has completed. Since this
TLB was only setup once, a 2nd attempt to run this cache test
failed with a crash. Now this TLB entry is created every time the
routine is called.

Signed-off-by: Stefan Roese <sr@denx.de>

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ppc4xx: Fix lwmon5 compilation problem

Now that the 440EPx ECC test is not board specific anymore
remove this Makefile.

Signed-off-by: Stefan Roese <sr@denx.de>

Fix/enhance ECC POST for 440EPx/GRx

This patch allows the ECC POST to be used for different boards with the
PPC440 Denali SDRAM controller. Modifications include skipping the test
if ECC is not ena

Fix/enhance ECC POST for 440EPx/GRx

This patch allows the ECC POST to be used for different boards with the
PPC440 Denali SDRAM controller. Modifications include skipping the test
if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization
to prevent timing errors.

Signed-off-by: Larry Johnson <lrj@acm.org>

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PPC4xx: Move/rename ECC POST for 440EPx/GRx

Signed-off-by: Larry Johnson <lrj@acm.org>

ppc4xx: use correct io accessors for 4xx ethernet POST

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

ppc4xx: Enable CPU POST test for 4xx with dcache enabled

Now with caches enabled (i- and d-cache) on 44x, we need a chance to
disable the cache for the CPU POST tests, since these tests consist
of s

ppc4xx: Enable CPU POST test for 4xx with dcache enabled

Now with caches enabled (i- and d-cache) on 44x, we need a chance to
disable the cache for the CPU POST tests, since these tests consist
of self modifying code. This is done via the new change_tlb() function.

Signed-off-by: Stefan Roese <sr@denx.de>

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ppc4xx: Change 4xx POST ethernet test to handle cached memory too

This patch enables the 4xx EMAC POST driver to work too, when dcache is
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Remove temporary TLB entry in POST cache test only for 440

Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Remove compiler warning from previous commit

Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Remove temporary TLB entry in POST cache test

Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Fix POST ethernet test for Haleakala

The POST ethernet test needed to be changed to dynamically determine
the count of ethernet devices. This code is cloned from the 4xx
ethernet driver.

Si

ppc4xx: Fix POST ethernet test for Haleakala

The POST ethernet test needed to be changed to dynamically determine
the count of ethernet devices. This code is cloned from the 4xx
ethernet driver.

Signed-off-by: Stefan Roese <sr@denx.de>

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POST: Add 405EX support to 4xx UART POST test

Signed-off-by: Stefan Roese <sr@denx.de>