1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Kevin Lam <kevin.lam@freescale.com>
4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  */
14 
15 #include <common.h>
16 #include <i2c.h>
17 #include <asm/io.h>
18 #include <spd_sdram.h>
19 
20 #if defined(CFG_DRAM_TEST)
21 int
22 testdram(void)
23 {
24 	uint *pstart = (uint *) CFG_MEMTEST_START;
25 	uint *pend = (uint *) CFG_MEMTEST_END;
26 	uint *p;
27 
28 	printf("Testing DRAM from 0x%08x to 0x%08x\n",
29 	       CFG_MEMTEST_START,
30 	       CFG_MEMTEST_END);
31 
32 	printf("DRAM test phase 1:\n");
33 	for (p = pstart; p < pend; p++)
34 		*p = 0xaaaaaaaa;
35 
36 	for (p = pstart; p < pend; p++) {
37 		if (*p != 0xaaaaaaaa) {
38 			printf("DRAM test fails at: %08x\n", (uint) p);
39 			return 1;
40 		}
41 	}
42 
43 	printf("DRAM test phase 2:\n");
44 	for (p = pstart; p < pend; p++)
45 		*p = 0x55555555;
46 
47 	for (p = pstart; p < pend; p++) {
48 		if (*p != 0x55555555) {
49 			printf("DRAM test fails at: %08x\n", (uint) p);
50 			return 1;
51 		}
52 	}
53 
54 	printf("DRAM test passed.\n");
55 	return 0;
56 }
57 #endif
58 
59 int board_early_init_f(void)
60 {
61 	return 0;
62 }
63 
64 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
65 void ddr_enable_ecc(unsigned int dram_size);
66 #endif
67 int fixed_sdram(void);
68 
69 long int initdram(int board_type)
70 {
71 	immap_t *im = (immap_t *) CFG_IMMR;
72 	u32 msize = 0;
73 
74 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
75 		return -1;
76 
77 #if defined(CONFIG_SPD_EEPROM)
78 	msize = spd_sdram();
79 #else
80 	msize = fixed_sdram();
81 #endif
82 
83 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
84 	/* Initialize DDR ECC byte */
85 	ddr_enable_ecc(msize * 1024 * 1024);
86 #endif
87 	/* return total bus DDR size(bytes) */
88 	return (msize * 1024 * 1024);
89 }
90 
91 #if !defined(CONFIG_SPD_EEPROM)
92 /*************************************************************************
93  *  fixed sdram init -- doesn't use serial presence detect.
94  ************************************************************************/
95 int fixed_sdram(void)
96 {
97 	immap_t *im = (immap_t *) CFG_IMMR;
98 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
99 	u32 msize_log2 = __ilog2(msize);
100 
101 	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
102 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
103 
104 	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
105 	udelay(50000);
106 
107 	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
108 	udelay(1000);
109 
110 	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
111 	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
112 	udelay(1000);
113 
114 	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
115 	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
116 	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
117 	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
118 	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
119 	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
120 	im->ddr.sdram_mode = CFG_DDR_MODE;
121 	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
122 	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
123 	sync();
124 	udelay(1000);
125 
126 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
127 	udelay(2000);
128 	return CFG_DDR_SIZE;
129 }
130 #endif	/*!CFG_SPD_EEPROM */
131 
132 int checkboard(void)
133 {
134 	puts("Board: Freescale MPC837xERDB\n");
135 	return 0;
136 }
137 
138 #if defined(CONFIG_OF_BOARD_SETUP)
139 
140 void ft_board_setup(void *blob, bd_t *bd)
141 {
142 #ifdef CONFIG_PCI
143 	ft_pci_setup(blob, bd);
144 #endif
145 	ft_cpu_setup(blob, bd);
146 }
147 #endif /* CONFIG_OF_BOARD_SETUP */
148