1 /* 2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Joe Hamman joe.hamman@embeddedspecialties.com 5 * 6 * Copyright 2004 Freescale Semiconductor. 7 * Jeff Brown 8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 9 * 10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #include <common.h> 32 #include <command.h> 33 #include <pci.h> 34 #include <asm/processor.h> 35 #include <asm/immap_86xx.h> 36 #include <asm/immap_fsl_pci.h> 37 #include <spd.h> 38 #include <libfdt.h> 39 #include <fdt_support.h> 40 41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 42 extern void ddr_enable_ecc (unsigned int dram_size); 43 #endif 44 45 #if defined(CONFIG_SPD_EEPROM) 46 #include "spd_sdram.h" 47 #endif 48 49 void sdram_init (void); 50 long int fixed_sdram (void); 51 52 int board_early_init_f (void) 53 { 54 return 0; 55 } 56 57 int checkboard (void) 58 { 59 puts ("Board: Wind River SBC8641D\n"); 60 61 return 0; 62 } 63 64 long int initdram (int board_type) 65 { 66 long dram_size = 0; 67 68 #if defined(CONFIG_SPD_EEPROM) 69 dram_size = spd_sdram (); 70 #else 71 dram_size = fixed_sdram (); 72 #endif 73 74 #if defined(CFG_RAMBOOT) 75 puts (" DDR: "); 76 return dram_size; 77 #endif 78 79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 80 /* 81 * Initialize and enable DDR ECC. 82 */ 83 ddr_enable_ecc (dram_size); 84 #endif 85 86 puts (" DDR: "); 87 return dram_size; 88 } 89 90 #if defined(CFG_DRAM_TEST) 91 int testdram (void) 92 { 93 uint *pstart = (uint *) CFG_MEMTEST_START; 94 uint *pend = (uint *) CFG_MEMTEST_END; 95 uint *p; 96 97 puts ("SDRAM test phase 1:\n"); 98 for (p = pstart; p < pend; p++) 99 *p = 0xaaaaaaaa; 100 101 for (p = pstart; p < pend; p++) { 102 if (*p != 0xaaaaaaaa) { 103 printf ("SDRAM test fails at: %08x\n", (uint) p); 104 return 1; 105 } 106 } 107 108 puts ("SDRAM test phase 2:\n"); 109 for (p = pstart; p < pend; p++) 110 *p = 0x55555555; 111 112 for (p = pstart; p < pend; p++) { 113 if (*p != 0x55555555) { 114 printf ("SDRAM test fails at: %08x\n", (uint) p); 115 return 1; 116 } 117 } 118 119 puts ("SDRAM test passed.\n"); 120 return 0; 121 } 122 #endif 123 124 #if !defined(CONFIG_SPD_EEPROM) 125 /* 126 * Fixed sdram init -- doesn't use serial presence detect. 127 */ 128 long int fixed_sdram (void) 129 { 130 #if !defined(CFG_RAMBOOT) 131 volatile immap_t *immap = (immap_t *) CFG_IMMR; 132 volatile ccsr_ddr_t *ddr = &immap->im_ddr1; 133 134 ddr->cs0_bnds = CFG_DDR_CS0_BNDS; 135 ddr->cs1_bnds = CFG_DDR_CS1_BNDS; 136 ddr->cs2_bnds = CFG_DDR_CS2_BNDS; 137 ddr->cs3_bnds = CFG_DDR_CS3_BNDS; 138 ddr->cs0_config = CFG_DDR_CS0_CONFIG; 139 ddr->cs1_config = CFG_DDR_CS1_CONFIG; 140 ddr->cs2_config = CFG_DDR_CS2_CONFIG; 141 ddr->cs3_config = CFG_DDR_CS3_CONFIG; 142 ddr->ext_refrec = CFG_DDR_EXT_REFRESH; 143 ddr->timing_cfg_0 = CFG_DDR_TIMING_0; 144 ddr->timing_cfg_1 = CFG_DDR_TIMING_1; 145 ddr->timing_cfg_2 = CFG_DDR_TIMING_2; 146 ddr->sdram_cfg_1 = CFG_DDR_CFG_1A; 147 ddr->sdram_cfg_2 = CFG_DDR_CFG_2; 148 ddr->sdram_mode_1 = CFG_DDR_MODE_1; 149 ddr->sdram_mode_2 = CFG_DDR_MODE_2; 150 ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL; 151 ddr->sdram_interval = CFG_DDR_INTERVAL; 152 ddr->sdram_data_init = CFG_DDR_DATA_INIT; 153 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; 154 155 asm ("sync;isync"); 156 157 udelay (500); 158 159 ddr->sdram_cfg_1 = CFG_DDR_CFG_1B; 160 asm ("sync; isync"); 161 162 udelay (500); 163 ddr = &immap->im_ddr2; 164 165 ddr->cs0_bnds = CFG_DDR2_CS0_BNDS; 166 ddr->cs1_bnds = CFG_DDR2_CS1_BNDS; 167 ddr->cs2_bnds = CFG_DDR2_CS2_BNDS; 168 ddr->cs3_bnds = CFG_DDR2_CS3_BNDS; 169 ddr->cs0_config = CFG_DDR2_CS0_CONFIG; 170 ddr->cs1_config = CFG_DDR2_CS1_CONFIG; 171 ddr->cs2_config = CFG_DDR2_CS2_CONFIG; 172 ddr->cs3_config = CFG_DDR2_CS3_CONFIG; 173 ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; 174 ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; 175 ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; 176 ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; 177 ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A; 178 ddr->sdram_cfg_2 = CFG_DDR2_CFG_2; 179 ddr->sdram_mode_1 = CFG_DDR2_MODE_1; 180 ddr->sdram_mode_2 = CFG_DDR2_MODE_2; 181 ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL; 182 ddr->sdram_interval = CFG_DDR2_INTERVAL; 183 ddr->sdram_data_init = CFG_DDR2_DATA_INIT; 184 ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL; 185 186 asm ("sync;isync"); 187 188 udelay (500); 189 190 ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B; 191 asm ("sync; isync"); 192 193 udelay (500); 194 #endif 195 return CFG_SDRAM_SIZE * 1024 * 1024; 196 } 197 #endif /* !defined(CONFIG_SPD_EEPROM) */ 198 199 #if defined(CONFIG_PCI) 200 /* 201 * Initialize PCI Devices, report devices found. 202 */ 203 204 #ifndef CONFIG_PCI_PNP 205 static struct pci_config_table pci_fsl86xxads_config_table[] = { 206 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 207 PCI_IDSEL_NUMBER, PCI_ANY_ID, 208 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 209 PCI_ENET0_MEMADDR, 210 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, 211 {} 212 }; 213 #endif 214 215 static struct pci_controller pci1_hose = { 216 #ifndef CONFIG_PCI_PNP 217 config_table:pci_mpc86xxcts_config_table 218 #endif 219 }; 220 #endif /* CONFIG_PCI */ 221 222 #ifdef CONFIG_PCI2 223 static struct pci_controller pci2_hose; 224 #endif /* CONFIG_PCI2 */ 225 226 int first_free_busno = 0; 227 228 void pci_init_board(void) 229 { 230 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; 231 volatile ccsr_gur_t *gur = &immap->im_gur; 232 uint devdisr = gur->devdisr; 233 uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; 234 235 #ifdef CONFIG_PCI1 236 { 237 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; 238 extern void fsl_pci_init(struct pci_controller *hose); 239 struct pci_controller *hose = &pci1_hose; 240 #ifdef DEBUG 241 uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; 242 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); 243 #endif 244 if ((io_sel == 2 || io_sel == 3 || io_sel == 5 245 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) 246 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { 247 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); 248 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); 249 if (pci->pme_msg_det) { 250 pci->pme_msg_det = 0xffffffff; 251 debug(" with errors. Clearing. Now 0x%08x", 252 pci->pme_msg_det); 253 } 254 debug("\n"); 255 256 /* inbound */ 257 pci_set_region(hose->regions + 0, 258 CFG_PCI_MEMORY_BUS, 259 CFG_PCI_MEMORY_PHYS, 260 CFG_PCI_MEMORY_SIZE, 261 PCI_REGION_MEM | PCI_REGION_MEMORY); 262 263 /* outbound memory */ 264 pci_set_region(hose->regions + 1, 265 CFG_PCI1_MEM_BASE, 266 CFG_PCI1_MEM_PHYS, 267 CFG_PCI1_MEM_SIZE, 268 PCI_REGION_MEM); 269 270 /* outbound io */ 271 pci_set_region(hose->regions + 2, 272 CFG_PCI1_IO_BASE, 273 CFG_PCI1_IO_PHYS, 274 CFG_PCI1_IO_SIZE, 275 PCI_REGION_IO); 276 277 hose->region_count = 3; 278 279 hose->first_busno=first_free_busno; 280 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 281 282 fsl_pci_init(hose); 283 284 first_free_busno=hose->last_busno+1; 285 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", 286 hose->first_busno,hose->last_busno); 287 288 } else { 289 puts("PCI-EXPRESS 1: Disabled\n"); 290 } 291 } 292 #else 293 puts("PCI-EXPRESS1: Disabled\n"); 294 #endif /* CONFIG_PCI1 */ 295 296 #ifdef CONFIG_PCI2 297 { 298 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; 299 extern void fsl_pci_init(struct pci_controller *hose); 300 struct pci_controller *hose = &pci2_hose; 301 302 303 /* inbound */ 304 pci_set_region(hose->regions + 0, 305 CFG_PCI_MEMORY_BUS, 306 CFG_PCI_MEMORY_PHYS, 307 CFG_PCI_MEMORY_SIZE, 308 PCI_REGION_MEM | PCI_REGION_MEMORY); 309 310 /* outbound memory */ 311 pci_set_region(hose->regions + 1, 312 CFG_PCI2_MEM_BASE, 313 CFG_PCI2_MEM_PHYS, 314 CFG_PCI2_MEM_SIZE, 315 PCI_REGION_MEM); 316 317 /* outbound io */ 318 pci_set_region(hose->regions + 2, 319 CFG_PCI2_IO_BASE, 320 CFG_PCI2_IO_PHYS, 321 CFG_PCI2_IO_SIZE, 322 PCI_REGION_IO); 323 324 hose->region_count = 3; 325 326 hose->first_busno=first_free_busno; 327 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 328 329 fsl_pci_init(hose); 330 331 first_free_busno=hose->last_busno+1; 332 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", 333 hose->first_busno,hose->last_busno); 334 } 335 #else 336 puts("PCI-EXPRESS 2: Disabled\n"); 337 #endif /* CONFIG_PCI2 */ 338 339 } 340 341 342 #if defined(CONFIG_OF_BOARD_SETUP) 343 344 void 345 ft_board_setup (void *blob, bd_t *bd) 346 { 347 int node, tmp[2]; 348 const char *path; 349 350 ft_cpu_setup(blob, bd); 351 352 node = fdt_path_offset(blob, "/aliases"); 353 tmp[0] = 0; 354 if (node >= 0) { 355 #ifdef CONFIG_PCI1 356 path = fdt_getprop(blob, node, "pci0", NULL); 357 if (path) { 358 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 359 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 360 } 361 #endif 362 #ifdef CONFIG_PCI2 363 path = fdt_getprop(blob, node, "pci1", NULL); 364 if (path) { 365 tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; 366 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 367 } 368 #endif 369 } 370 } 371 #endif 372 373 void sbc8641d_reset_board (void) 374 { 375 puts ("Resetting board....\n"); 376 } 377 378 /* 379 * get_board_sys_clk 380 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ 381 */ 382 383 unsigned long get_board_sys_clk (ulong dummy) 384 { 385 int i; 386 ulong val = 0; 387 388 i = 5; 389 i &= 0x07; 390 391 switch (i) { 392 case 0: 393 val = 33000000; 394 break; 395 case 1: 396 val = 40000000; 397 break; 398 case 2: 399 val = 50000000; 400 break; 401 case 3: 402 val = 66000000; 403 break; 404 case 4: 405 val = 83000000; 406 break; 407 case 5: 408 val = 100000000; 409 break; 410 case 6: 411 val = 134000000; 412 break; 413 case 7: 414 val = 166000000; 415 break; 416 } 417 418 return val; 419 } 420