1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Dave Liu <daveliu@freescale.com>
4  *
5  * CREDITS: Kim Phillips contribute to LIBFDT code
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12 
13 #include <common.h>
14 #include <i2c.h>
15 #include <spd_sdram.h>
16 #if defined(CONFIG_OF_LIBFDT)
17 #include <libfdt.h>
18 #endif
19 #if defined(CONFIG_PQ_MDS_PIB)
20 #include "../common/pq-mds-pib.h"
21 #endif
22 
23 int board_early_init_f(void)
24 {
25 	u8 *bcsr = (u8 *)CFG_BCSR;
26 
27 	/* Enable flash write */
28 	bcsr[0x9] &= ~0x04;
29 	/* Clear all of the interrupt of BCSR */
30 	bcsr[0xe] = 0xff;
31 
32 	return 0;
33 }
34 
35 int board_early_init_r(void)
36 {
37 #ifdef CONFIG_PQ_MDS_PIB
38 	pib_init();
39 #endif
40 	return 0;
41 }
42 
43 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
44 extern void ddr_enable_ecc(unsigned int dram_size);
45 #endif
46 int fixed_sdram(void);
47 
48 long int initdram(int board_type)
49 {
50 	volatile immap_t *im = (immap_t *) CFG_IMMR;
51 	u32 msize = 0;
52 
53 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
54 		return -1;
55 
56 #if defined(CONFIG_SPD_EEPROM)
57 	msize = spd_sdram();
58 #else
59 	msize = fixed_sdram();
60 #endif
61 
62 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
63 	/* Initialize DDR ECC byte */
64 	ddr_enable_ecc(msize * 1024 * 1024);
65 #endif
66 
67 	/* return total bus DDR size(bytes) */
68 	return (msize * 1024 * 1024);
69 }
70 
71 #if !defined(CONFIG_SPD_EEPROM)
72 /*************************************************************************
73  *  fixed sdram init -- doesn't use serial presence detect.
74  ************************************************************************/
75 int fixed_sdram(void)
76 {
77 	volatile immap_t *im = (immap_t *) CFG_IMMR;
78 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
79 	u32 msize_log2 = __ilog2(msize);
80 
81 	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
82 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
83 
84 #if (CFG_DDR_SIZE != 512)
85 #warning Currenly any ddr size other than 512 is not supported
86 #endif
87 	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
88 	udelay(50000);
89 
90 	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
91 	udelay(1000);
92 
93 	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
94 	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
95 	udelay(1000);
96 
97 	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
98 	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
99 	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
100 	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
101 	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
102 	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
103 	im->ddr.sdram_mode = CFG_DDR_MODE;
104 	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
105 	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
106 	__asm__ __volatile__("sync");
107 	udelay(1000);
108 
109 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
110 	udelay(2000);
111 	return CFG_DDR_SIZE;
112 }
113 #endif /*!CFG_SPD_EEPROM */
114 
115 int checkboard(void)
116 {
117 	puts("Board: Freescale MPC837xEMDS\n");
118 	return 0;
119 }
120 
121 #if defined(CONFIG_OF_BOARD_SETUP)
122 void ft_board_setup(void *blob, bd_t *bd)
123 {
124 	ft_cpu_setup(blob, bd);
125 #ifdef CONFIG_PCI
126 	ft_pci_setup(blob, bd);
127 #endif
128 }
129 #endif /* CONFIG_OF_BOARD_SETUP */
130