1 /* 2 * (C) Copyright 2001 3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * This provides a bit-banged interface to the ethernet MII management 26 * channel. 27 */ 28 29 #include <common.h> 30 #include <miiphy.h> 31 32 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 33 #include <asm/types.h> 34 #include <linux/list.h> 35 #include <malloc.h> 36 #include <net.h> 37 38 /* local debug macro */ 39 #undef MII_DEBUG 40 41 #undef debug 42 #ifdef MII_DEBUG 43 #define debug(fmt,args...) printf (fmt ,##args) 44 #else 45 #define debug(fmt,args...) 46 #endif /* MII_DEBUG */ 47 48 struct mii_dev { 49 struct list_head link; 50 char *name; 51 int (*read) (char *devname, unsigned char addr, 52 unsigned char reg, unsigned short *value); 53 int (*write) (char *devname, unsigned char addr, 54 unsigned char reg, unsigned short value); 55 }; 56 57 static struct list_head mii_devs; 58 static struct mii_dev *current_mii; 59 60 /***************************************************************************** 61 * 62 * Initialize global data. Need to be called before any other miiphy routine. 63 */ 64 void miiphy_init () 65 { 66 INIT_LIST_HEAD (&mii_devs); 67 current_mii = NULL; 68 } 69 70 /***************************************************************************** 71 * 72 * Register read and write MII access routines for the device <name>. 73 */ 74 void miiphy_register (char *name, 75 int (*read) (char *devname, unsigned char addr, 76 unsigned char reg, unsigned short *value), 77 int (*write) (char *devname, unsigned char addr, 78 unsigned char reg, unsigned short value)) 79 { 80 struct list_head *entry; 81 struct mii_dev *new_dev; 82 struct mii_dev *miidev; 83 unsigned int name_len; 84 85 /* check if we have unique name */ 86 list_for_each (entry, &mii_devs) { 87 miidev = list_entry (entry, struct mii_dev, link); 88 if (strcmp (miidev->name, name) == 0) { 89 printf ("miiphy_register: non unique device name " 90 "'%s'\n", name); 91 return; 92 } 93 } 94 95 /* allocate memory */ 96 name_len = strlen (name); 97 new_dev = 98 (struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1); 99 100 if (new_dev == NULL) { 101 printf ("miiphy_register: cannot allocate memory for '%s'\n", 102 name); 103 return; 104 } 105 memset (new_dev, 0, sizeof (struct mii_dev) + name_len); 106 107 /* initalize mii_dev struct fields */ 108 INIT_LIST_HEAD (&new_dev->link); 109 new_dev->read = read; 110 new_dev->write = write; 111 new_dev->name = (char *)(new_dev + 1); 112 strncpy (new_dev->name, name, name_len); 113 new_dev->name[name_len] = '\0'; 114 115 debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n", 116 new_dev->name, new_dev->read, new_dev->write); 117 118 /* add it to the list */ 119 list_add_tail (&new_dev->link, &mii_devs); 120 121 if (!current_mii) 122 current_mii = new_dev; 123 } 124 125 int miiphy_set_current_dev (char *devname) 126 { 127 struct list_head *entry; 128 struct mii_dev *dev; 129 130 list_for_each (entry, &mii_devs) { 131 dev = list_entry (entry, struct mii_dev, link); 132 133 if (strcmp (devname, dev->name) == 0) { 134 current_mii = dev; 135 return 0; 136 } 137 } 138 139 printf ("No such device: %s\n", devname); 140 return 1; 141 } 142 143 char *miiphy_get_current_dev () 144 { 145 if (current_mii) 146 return current_mii->name; 147 148 return NULL; 149 } 150 151 /***************************************************************************** 152 * 153 * Read to variable <value> from the PHY attached to device <devname>, 154 * use PHY address <addr> and register <reg>. 155 * 156 * Returns: 157 * 0 on success 158 */ 159 int miiphy_read (char *devname, unsigned char addr, unsigned char reg, 160 unsigned short *value) 161 { 162 struct list_head *entry; 163 struct mii_dev *dev; 164 int found_dev = 0; 165 int read_ret = 0; 166 167 if (!devname) { 168 printf ("NULL device name!\n"); 169 return 1; 170 } 171 172 list_for_each (entry, &mii_devs) { 173 dev = list_entry (entry, struct mii_dev, link); 174 175 if (strcmp (devname, dev->name) == 0) { 176 found_dev = 1; 177 read_ret = dev->read (devname, addr, reg, value); 178 break; 179 } 180 } 181 182 if (found_dev == 0) 183 printf ("No such device: %s\n", devname); 184 185 return ((found_dev) ? read_ret : 1); 186 } 187 188 /***************************************************************************** 189 * 190 * Write <value> to the PHY attached to device <devname>, 191 * use PHY address <addr> and register <reg>. 192 * 193 * Returns: 194 * 0 on success 195 */ 196 int miiphy_write (char *devname, unsigned char addr, unsigned char reg, 197 unsigned short value) 198 { 199 struct list_head *entry; 200 struct mii_dev *dev; 201 int found_dev = 0; 202 int write_ret = 0; 203 204 if (!devname) { 205 printf ("NULL device name!\n"); 206 return 1; 207 } 208 209 list_for_each (entry, &mii_devs) { 210 dev = list_entry (entry, struct mii_dev, link); 211 212 if (strcmp (devname, dev->name) == 0) { 213 found_dev = 1; 214 write_ret = dev->write (devname, addr, reg, value); 215 break; 216 } 217 } 218 219 if (found_dev == 0) 220 printf ("No such device: %s\n", devname); 221 222 return ((found_dev) ? write_ret : 1); 223 } 224 225 /***************************************************************************** 226 * 227 * Print out list of registered MII capable devices. 228 */ 229 void miiphy_listdev (void) 230 { 231 struct list_head *entry; 232 struct mii_dev *dev; 233 234 puts ("MII devices: "); 235 list_for_each (entry, &mii_devs) { 236 dev = list_entry (entry, struct mii_dev, link); 237 printf ("'%s' ", dev->name); 238 } 239 puts ("\n"); 240 241 if (current_mii) 242 printf ("Current device: '%s'\n", current_mii->name); 243 } 244 245 /***************************************************************************** 246 * 247 * Read the OUI, manufacture's model number, and revision number. 248 * 249 * OUI: 22 bits (unsigned int) 250 * Model: 6 bits (unsigned char) 251 * Revision: 4 bits (unsigned char) 252 * 253 * Returns: 254 * 0 on success 255 */ 256 int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, 257 unsigned char *model, unsigned char *rev) 258 { 259 unsigned int reg = 0; 260 unsigned short tmp; 261 262 if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) { 263 debug ("PHY ID register 2 read failed\n"); 264 return (-1); 265 } 266 reg = tmp; 267 268 debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg); 269 270 if (reg == 0xFFFF) { 271 /* No physical device present at this address */ 272 return (-1); 273 } 274 275 if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) { 276 debug ("PHY ID register 1 read failed\n"); 277 return (-1); 278 } 279 reg |= tmp << 16; 280 debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); 281 282 *oui = (reg >> 10); 283 *model = (unsigned char)((reg >> 4) & 0x0000003F); 284 *rev = (unsigned char)(reg & 0x0000000F); 285 return (0); 286 } 287 288 /***************************************************************************** 289 * 290 * Reset the PHY. 291 * Returns: 292 * 0 on success 293 */ 294 int miiphy_reset (char *devname, unsigned char addr) 295 { 296 unsigned short reg; 297 int loop_cnt; 298 299 if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { 300 debug ("PHY status read failed\n"); 301 return (-1); 302 } 303 if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) { 304 debug ("PHY reset failed\n"); 305 return (-1); 306 } 307 #ifdef CONFIG_PHY_RESET_DELAY 308 udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ 309 #endif 310 /* 311 * Poll the control register for the reset bit to go to 0 (it is 312 * auto-clearing). This should happen within 0.5 seconds per the 313 * IEEE spec. 314 */ 315 loop_cnt = 0; 316 reg = 0x8000; 317 while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) { 318 if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { 319 debug ("PHY status read failed\n"); 320 return (-1); 321 } 322 } 323 if ((reg & 0x8000) == 0) { 324 return (0); 325 } else { 326 puts ("PHY reset timed out\n"); 327 return (-1); 328 } 329 return (0); 330 } 331 332 /***************************************************************************** 333 * 334 * Determine the ethernet speed (10/100/1000). Return 10 on error. 335 */ 336 int miiphy_speed (char *devname, unsigned char addr) 337 { 338 u16 bmcr, anlpar; 339 340 #if defined(CONFIG_PHY_GIGE) 341 u16 btsr; 342 343 /* 344 * Check for 1000BASE-X. If it is supported, then assume that the speed 345 * is 1000. 346 */ 347 if (miiphy_is_1000base_x (devname, addr)) { 348 return _1000BASET; 349 } 350 /* 351 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. 352 */ 353 /* Check for 1000BASE-T. */ 354 if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) { 355 printf ("PHY 1000BT status"); 356 goto miiphy_read_failed; 357 } 358 if (btsr != 0xFFFF && 359 (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) { 360 return _1000BASET; 361 } 362 #endif /* CONFIG_PHY_GIGE */ 363 364 /* Check Basic Management Control Register first. */ 365 if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) { 366 printf ("PHY speed"); 367 goto miiphy_read_failed; 368 } 369 /* Check if auto-negotiation is on. */ 370 if (bmcr & PHY_BMCR_AUTON) { 371 /* Get auto-negotiation results. */ 372 if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { 373 printf ("PHY AN speed"); 374 goto miiphy_read_failed; 375 } 376 return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET; 377 } 378 /* Get speed from basic control settings. */ 379 return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET; 380 381 miiphy_read_failed: 382 printf (" read failed, assuming 10BASE-T\n"); 383 return _10BASET; 384 } 385 386 /***************************************************************************** 387 * 388 * Determine full/half duplex. Return half on error. 389 */ 390 int miiphy_duplex (char *devname, unsigned char addr) 391 { 392 u16 bmcr, anlpar; 393 394 #if defined(CONFIG_PHY_GIGE) 395 u16 btsr; 396 397 /* Check for 1000BASE-X. */ 398 if (miiphy_is_1000base_x (devname, addr)) { 399 /* 1000BASE-X */ 400 if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { 401 printf ("1000BASE-X PHY AN duplex"); 402 goto miiphy_read_failed; 403 } 404 } 405 /* 406 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. 407 */ 408 /* Check for 1000BASE-T. */ 409 if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) { 410 printf ("PHY 1000BT status"); 411 goto miiphy_read_failed; 412 } 413 if (btsr != 0xFFFF) { 414 if (btsr & PHY_1000BTSR_1000FD) { 415 return FULL; 416 } else if (btsr & PHY_1000BTSR_1000HD) { 417 return HALF; 418 } 419 } 420 #endif /* CONFIG_PHY_GIGE */ 421 422 /* Check Basic Management Control Register first. */ 423 if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) { 424 puts ("PHY duplex"); 425 goto miiphy_read_failed; 426 } 427 /* Check if auto-negotiation is on. */ 428 if (bmcr & PHY_BMCR_AUTON) { 429 /* Get auto-negotiation results. */ 430 if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { 431 puts ("PHY AN duplex"); 432 goto miiphy_read_failed; 433 } 434 return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ? 435 FULL : HALF; 436 } 437 /* Get speed from basic control settings. */ 438 return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF; 439 440 miiphy_read_failed: 441 printf (" read failed, assuming half duplex\n"); 442 return HALF; 443 } 444 445 /***************************************************************************** 446 * 447 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/ 448 * 1000BASE-T, or on error. 449 */ 450 int miiphy_is_1000base_x (char *devname, unsigned char addr) 451 { 452 #if defined(CONFIG_PHY_GIGE) 453 u16 exsr; 454 455 if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) { 456 printf ("PHY extended status read failed, assuming no " 457 "1000BASE-X\n"); 458 return 0; 459 } 460 return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)); 461 #else 462 return 0; 463 #endif 464 } 465 466 #ifdef CFG_FAULT_ECHO_LINK_DOWN 467 /***************************************************************************** 468 * 469 * Determine link status 470 */ 471 int miiphy_link (char *devname, unsigned char addr) 472 { 473 unsigned short reg; 474 475 /* dummy read; needed to latch some phys */ 476 (void)miiphy_read (devname, addr, PHY_BMSR, ®); 477 if (miiphy_read (devname, addr, PHY_BMSR, ®)) { 478 puts ("PHY_BMSR read failed, assuming no link\n"); 479 return (0); 480 } 481 482 /* Determine if a link is active */ 483 if ((reg & PHY_BMSR_LS) != 0) { 484 return (1); 485 } else { 486 return (0); 487 } 488 } 489 #endif 490 #endif /* CONFIG_MII */ 491