829e8c73 | 21-Jan-2019 |
Michal Simek <michal.simek@xilinx.com> |
xilinx: common: Add support for DM_I2C zynq_board_read_rom_ethaddr()
It is much easier to point to eeprom which stores information like MAC address directly via DT. eeprom which contains this inform
xilinx: common: Add support for DM_I2C zynq_board_read_rom_ethaddr()
It is much easier to point to eeprom which stores information like MAC address directly via DT. eeprom which contains this information is pointed by /chosen/xlnx,eeprom parameter.
For example: chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; };
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|
e7c9de66 | 03-Jan-2019 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: zynqmp: Fix mmc node names to be in sync with kernel
This patches renames sd nodes in dts to be in line with kernel. This patch also modifies the references for the same in code. It checks mm
arm64: zynqmp: Fix mmc node names to be in sync with kernel
This patches renames sd nodes in dts to be in line with kernel. This patch also modifies the references for the same in code. It checks mmc first to have no time penalty for new DT node names based on left-to-right expression evaluation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|
ebcc1a22 | 30-Nov-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Wire mini-emmc1 configuration with zcu102
For testing purpose use zcu102 which has SD at controller 1 and this can be used for testing this mini configuration.
U-Boot 2018.11-00279-g
arm64: zynqmp: Wire mini-emmc1 configuration with zcu102
For testing purpose use zcu102 which has SD at controller 1 and this can be used for testing this mini configuration.
U-Boot 2018.11-00279-gdc482e7ee092 (Nov 30 2018 - 10:22:56 +0100)
Model: ZynqMP MINI EMMC1 Board: Xilinx ZynqMP DRAM: 512 MiB EL Level: EL3 MMC: sdhci@ff170000: 0 In: dcc Out: dcc Err: dcc ZynqMP>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|
f5ed777d | 30-Nov-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Wire mini-emmc0 configuration with zcu100
For testing purpose use zcu100 which has SD at controller 0 and this can be used for testing this mini configuration.
U-Boot 2018.11-00281-g
arm64: zynqmp: Wire mini-emmc0 configuration with zcu100
For testing purpose use zcu100 which has SD at controller 0 and this can be used for testing this mini configuration.
U-Boot 2018.11-00281-gc5d48466e76e (Nov 30 2018 - 10:41:05 +0100)
Model: ZynqMP MINI EMMC0 Board: Xilinx ZynqMP DRAM: 512 MiB EL Level: EL3 MMC: sdhci@ff160000: 0 In: dcc Out: dcc Err: dcc ZynqMP>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|
e615f39e | 05-Oct-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Start usb ethernet gadget automatically
If only usb ethernet gadget is enabled it can start automatically. If more gagdets are enabled usb ethernet gadget can be bind by "bind /amba/u
arm64: zynqmp: Start usb ethernet gadget automatically
If only usb ethernet gadget is enabled it can start automatically. If more gagdets are enabled usb ethernet gadget can be bind by "bind /amba/usb1@ff9e0000/dwc3@fe300000 usb_ether" (on zcu100)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|
ec48b6c9 | 22-Aug-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Sc
arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency.
The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
|