1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2014 - 2018 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <malloc.h> 10 #include <asm/io.h> 11 #include <asm/arch/hardware.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 int board_init(void) 16 { 17 printf("EL Level:\tEL%d\n", current_el()); 18 19 return 0; 20 } 21 22 int board_early_init_r(void) 23 { 24 u32 val; 25 26 if (current_el() != 3) 27 return 0; 28 29 writel(IOU_SWITCH_CTRL_CLKACT_BIT | 30 (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), 31 &crlapb_base->iou_switch_ctrl); 32 33 /* Global timer init - Program time stamp reference clk */ 34 val = readl(&crlapb_base->timestamp_ref_ctrl); 35 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; 36 writel(val, &crlapb_base->timestamp_ref_ctrl); 37 38 debug("ref ctrl 0x%x\n", 39 readl(&crlapb_base->timestamp_ref_ctrl)); 40 41 /* Clear reset of timestamp reg */ 42 writel(0, &crlapb_base->rst_timestamp); 43 44 /* 45 * Program freq register in System counter and 46 * enable system counter. 47 */ 48 writel(COUNTER_FREQUENCY, 49 &iou_scntr_secure->base_frequency_id_register); 50 51 debug("counter val 0x%x\n", 52 readl(&iou_scntr_secure->base_frequency_id_register)); 53 54 writel(IOU_SCNTRS_CONTROL_EN, 55 &iou_scntr_secure->counter_control_register); 56 57 debug("scntrs control 0x%x\n", 58 readl(&iou_scntr_secure->counter_control_register)); 59 debug("timer 0x%llx\n", get_ticks()); 60 debug("timer 0x%llx\n", get_ticks()); 61 62 return 0; 63 } 64 65 int dram_init_banksize(void) 66 { 67 fdtdec_setup_memory_banksize(); 68 69 return 0; 70 } 71 72 int dram_init(void) 73 { 74 if (fdtdec_setup_mem_size_base() != 0) 75 return -EINVAL; 76 77 return 0; 78 } 79 80 void reset_cpu(ulong addr) 81 { 82 } 83