xref: /openbmc/u-boot/board/logicpd/imx6/imx6logic.c (revision 9755e3db8b1223699954146dfb171df75ec89ab3)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2017 Logic PD, Inc.
4  *
5  * Author: Adam Ford <aford173@gmail.com>
6  *
7  * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
8  * and updates by Jagan Teki <jagan@amarulasolutions.com>
9  */
10 
11 #include <common.h>
12 #include <miiphy.h>
13 #include <input.h>
14 #include <mmc.h>
15 #include <fsl_esdhc.h>
16 #include <asm/io.h>
17 #include <asm/gpio.h>
18 #include <linux/sizes.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/arch/iomux.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/mx6-pins.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/mach-imx/boot_mode.h>
26 #include <asm/mach-imx/iomux-v3.h>
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
31 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
32 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
33 
34 #define NAND_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
35 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
36 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
37 
38 int dram_init(void)
39 {
40 	gd->ram_size = imx_ddr_size();
41 	return 0;
42 }
43 
44 static iomux_v3_cfg_t const uart1_pads[] = {
45 	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
46 	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
47 };
48 
49 static iomux_v3_cfg_t const uart2_pads[] = {
50 	MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51 	MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
52 	MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
53 	MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
54 };
55 
56 static iomux_v3_cfg_t const uart3_pads[] = {
57 	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
58 	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
59 	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
60 	MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
61 };
62 
63 #ifndef CONFIG_SPL_BUILD
64 static void fixup_enet_clock(void)
65 {
66 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
67 	struct gpio_desc nint;
68 	struct gpio_desc reset;
69 	int ret;
70 
71 	/* Set Ref Clock to 50 MHz */
72 	enable_fec_anatop_clock(0, ENET_50MHZ);
73 
74 	/* Set GPIO_16 as ENET_REF_CLK_OUT */
75 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
76 
77 	/* Request GPIO Pins to reset Ethernet with new clock */
78 	ret = dm_gpio_lookup_name("GPIO4_7", &nint);
79 	if (ret) {
80 		printf("Unable to lookup GPIO4_7\n");
81 		return;
82 	}
83 
84 	ret = dm_gpio_request(&nint, "eth0_nInt");
85 	if (ret) {
86 		printf("Unable to request eth0_nInt\n");
87 		return;
88 	}
89 
90 	/* Ensure nINT is input or PHY won't startup */
91 	dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
92 
93 	ret = dm_gpio_lookup_name("GPIO4_9", &reset);
94 	if (ret) {
95 		printf("Unable to lookup GPIO4_9\n");
96 		return;
97 	}
98 
99 	ret = dm_gpio_request(&reset, "eth0_reset");
100 	if (ret) {
101 		printf("Unable to request eth0_reset\n");
102 		return;
103 	}
104 
105 	/* Reset LAN8710A PHY */
106 	dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
107 	dm_gpio_set_value(&reset, 0);
108 	udelay(150);
109 	dm_gpio_set_value(&reset, 1);
110 	mdelay(50);
111 }
112 #endif
113 
114 static void setup_iomux_uart(void)
115 {
116 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
117 	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
118 	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
119 }
120 
121 static iomux_v3_cfg_t const nand_pads[] = {
122 	MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
123 	MX6_PAD_NANDF_ALE__NAND_ALE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
124 	MX6_PAD_NANDF_CLE__NAND_CLE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
125 	MX6_PAD_NANDF_WP_B__NAND_WP_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
126 	MX6_PAD_NANDF_RB0__NAND_READY_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
127 	MX6_PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL),
128 	MX6_PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL),
129 	MX6_PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL),
130 	MX6_PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL),
131 	MX6_PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL),
132 	MX6_PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL),
133 	MX6_PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL),
134 	MX6_PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL),
135 	MX6_PAD_SD4_CLK__NAND_WE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
136 	MX6_PAD_SD4_CMD__NAND_RE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
137 };
138 
139 static void setup_nand_pins(void)
140 {
141 	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
142 }
143 
144 int board_phy_config(struct phy_device *phydev)
145 {
146 	if (phydev->drv->config)
147 		phydev->drv->config(phydev);
148 
149 	return 0;
150 }
151 
152 /*
153  * Do not overwrite the console
154  * Use always serial for U-Boot console
155  */
156 int overwrite_console(void)
157 {
158 	return 1;
159 }
160 
161 int board_early_init_f(void)
162 {
163 #ifndef CONFIG_SPL_BUILD
164 	fixup_enet_clock();
165 #endif
166 	setup_iomux_uart();
167 	setup_nand_pins();
168 	return 0;
169 }
170 
171 int board_init(void)
172 {
173 	/* address of boot parameters */
174 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
175 	return 0;
176 }
177 
178 int board_late_init(void)
179 {
180 	env_set("board_name", "imx6logic");
181 
182 	if (is_mx6dq()) {
183 		env_set("board_rev", "MX6DQ");
184 		env_set("fdt_file", "imx6q-logicpd.dtb");
185 	}
186 
187 	return 0;
188 }
189 
190 #ifdef CONFIG_SPL_BUILD
191 #include <asm/arch/mx6-ddr.h>
192 #include <asm/arch/mx6q-ddr.h>
193 #include <spl.h>
194 #include <linux/libfdt.h>
195 
196 #ifdef CONFIG_SPL_OS_BOOT
197 int spl_start_uboot(void)
198 {
199 	/* break into full u-boot on 'c' */
200 	if (serial_tstc() && serial_getc() == 'c')
201 		return 1;
202 
203 	return 0;
204 }
205 #endif
206 
207 /* SD interface */
208 #define USDHC_PAD_CTRL							\
209 	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |	\
210 	 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
211 
212 static iomux_v3_cfg_t const usdhc1_pads[] = {
213 	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
214 	MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
215 	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
216 	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
217 	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
218 	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
219 };
220 
221 static iomux_v3_cfg_t const usdhc2_pads[] = {
222 	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
223 	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
224 	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
225 	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
226 	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
227 	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
228 	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
229 };
230 
231 #ifdef CONFIG_FSL_ESDHC
232 struct fsl_esdhc_cfg usdhc_cfg[] = {
233 	{USDHC1_BASE_ADDR}, /* SOM */
234 	{USDHC2_BASE_ADDR}  /* Baseboard */
235 };
236 
237 int board_mmc_init(bd_t *bis)
238 {
239 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
240 	unsigned int reg = readl(&psrc->sbmr1) >> 11;
241 	/*
242 	 * Upon reading BOOT_CFG register the following map is done:
243 	 * Bit 11 and 12 of BOOT_CFG register can determine the current
244 	 * mmc port
245 	 * 0x1                  SD1-SOM
246 	 * 0x2                  SD2-Baseboard
247 	 */
248 
249 	reg &= 0x3; /* Only care about bottom 2 bits */
250 
251 	switch (reg) {
252 	case 0:
253 		SETUP_IOMUX_PADS(usdhc1_pads);
254 		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
255 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
256 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
257 		break;
258 	case 1:
259 		SETUP_IOMUX_PADS(usdhc2_pads);
260 		usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
261 		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
262 		gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk;
263 		break;
264 	}
265 
266 	return fsl_esdhc_initialize(bis, &usdhc_cfg[reg]);
267 }
268 
269 int board_mmc_getcd(struct mmc *mmc)
270 {
271 	return 1;
272 }
273 #endif
274 
275 static void ccgr_init(void)
276 {
277 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
278 
279 	writel(0x00C03F3F, &ccm->CCGR0);
280 	writel(0x0030FC03, &ccm->CCGR1);
281 	writel(0x0FFFC000, &ccm->CCGR2);
282 	writel(0x3FF00000, &ccm->CCGR3);
283 	writel(0xFFFFF300, &ccm->CCGR4);
284 	writel(0x0F0000F3, &ccm->CCGR5);
285 	writel(0x00000FFF, &ccm->CCGR6);
286 }
287 
288 static int mx6q_dcd_table[] = {
289 	MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
290 	MX6_IOM_GRP_DDRPKE, 0x00000000,
291 	MX6_IOM_DRAM_SDCLK_0, 0x00000030,
292 	MX6_IOM_DRAM_SDCLK_1, 0x00000030,
293 	MX6_IOM_DRAM_CAS, 0x00000030,
294 	MX6_IOM_DRAM_RAS, 0x00000030,
295 	MX6_IOM_GRP_ADDDS, 0x00000030,
296 	MX6_IOM_DRAM_RESET, 0x00000030,
297 	MX6_IOM_DRAM_SDBA2, 0x00000000,
298 	MX6_IOM_DRAM_SDODT0, 0x00000030,
299 	MX6_IOM_DRAM_SDODT1, 0x00000030,
300 	MX6_IOM_GRP_CTLDS, 0x00000030,
301 	MX6_IOM_DDRMODE_CTL, 0x00020000,
302 	MX6_IOM_DRAM_SDQS0, 0x00000030,
303 	MX6_IOM_DRAM_SDQS1, 0x00000030,
304 	MX6_IOM_DRAM_SDQS2, 0x00000030,
305 	MX6_IOM_DRAM_SDQS3, 0x00000030,
306 	MX6_IOM_GRP_DDRMODE, 0x00020000,
307 	MX6_IOM_GRP_B0DS, 0x00000030,
308 	MX6_IOM_GRP_B1DS, 0x00000030,
309 	MX6_IOM_GRP_B2DS, 0x00000030,
310 	MX6_IOM_GRP_B3DS, 0x00000030,
311 	MX6_IOM_DRAM_DQM0, 0x00000030,
312 	MX6_IOM_DRAM_DQM1, 0x00000030,
313 	MX6_IOM_DRAM_DQM2, 0x00000030,
314 	MX6_IOM_DRAM_DQM3, 0x00000030,
315 	MX6_MMDC_P0_MDSCR, 0x00008000,
316 	MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
317 	MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
318 	MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
319 	MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
320 	MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
321 	MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
322 	MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
323 	MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
324 	MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
325 	MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
326 	MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
327 	MX6_MMDC_P0_MPMUR0, 0x00000800,
328 	MX6_MMDC_P0_MDPDC, 0x00020036,
329 	MX6_MMDC_P0_MDOTC, 0x09444040,
330 	MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
331 	MX6_MMDC_P0_MDCFG1, 0xFF328F64,
332 	MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
333 	MX6_MMDC_P0_MDMISC, 0x00011740,
334 	MX6_MMDC_P0_MDSCR, 0x00008000,
335 	MX6_MMDC_P0_MDRWD, 0x000026D2,
336 	MX6_MMDC_P0_MDOR, 0x00BE1023,
337 	MX6_MMDC_P0_MDASP, 0x00000047,
338 	MX6_MMDC_P0_MDCTL, 0x85190000,
339 	MX6_MMDC_P0_MDSCR, 0x00888032,
340 	MX6_MMDC_P0_MDSCR, 0x00008033,
341 	MX6_MMDC_P0_MDSCR, 0x00008031,
342 	MX6_MMDC_P0_MDSCR, 0x19408030,
343 	MX6_MMDC_P0_MDSCR, 0x04008040,
344 	MX6_MMDC_P0_MDREF, 0x00007800,
345 	MX6_MMDC_P0_MPODTCTRL, 0x00000007,
346 	MX6_MMDC_P0_MDPDC, 0x00025576,
347 	MX6_MMDC_P0_MAPSR, 0x00011006,
348 	MX6_MMDC_P0_MDSCR, 0x00000000,
349 	/* enable AXI cache for VDOA/VPU/IPU */
350 
351 	MX6_IOMUXC_GPR4, 0xF00000CF,
352 	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
353 	MX6_IOMUXC_GPR6, 0x007F007F,
354 	MX6_IOMUXC_GPR7, 0x007F007F,
355 };
356 
357 static void ddr_init(int *table, int size)
358 {
359 	int i;
360 
361 	for (i = 0; i < size / 2 ; i++)
362 		writel(table[2 * i + 1], table[2 * i]);
363 }
364 
365 static void spl_dram_init(void)
366 {
367 	if (is_mx6dq())
368 		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
369 }
370 
371 void board_init_f(ulong dummy)
372 {
373 	/* DDR initialization */
374 	spl_dram_init();
375 
376 	/* setup AIPS and disable watchdog */
377 	arch_cpu_init();
378 
379 	ccgr_init();
380 	gpr_init();
381 
382 	/* iomux and setup of uart and NAND pins */
383 	board_early_init_f();
384 
385 	/* setup GP timer */
386 	timer_init();
387 
388 	/* UART clocks enabled and gd valid - init serial console */
389 	preloader_console_init();
390 
391 	/* Clear the BSS. */
392 	memset(__bss_start, 0, __bss_end - __bss_start);
393 
394 	/* load/boot image from boot device */
395 	board_init_r(NULL, 0);
396 }
397 #endif
398