xref: /openbmc/u-boot/drivers/usb/host/ehci-fsl.c (revision 5473f245d0a884ffd1a7f353b86d5d11e01d3ebd)
1  // SPDX-License-Identifier: GPL-2.0+
2  /*
3   * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
4   *
5   * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6   *
7   * Author: Tor Krill tor@excito.com
8   */
9  
10  #include <common.h>
11  #include <pci.h>
12  #include <usb.h>
13  #include <asm/io.h>
14  #include <usb/ehci-ci.h>
15  #include <hwconfig.h>
16  #include <fsl_usb.h>
17  #include <fdt_support.h>
18  #include <dm.h>
19  
20  #include "ehci.h"
21  
22  DECLARE_GLOBAL_DATA_PTR;
23  
24  #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
25  #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
26  #endif
27  
28  #ifdef CONFIG_DM_USB
29  struct ehci_fsl_priv {
30  	struct ehci_ctrl ehci;
31  	fdt_addr_t hcd_base;
32  	char *phy_type;
33  };
34  #endif
35  
36  static void set_txfifothresh(struct usb_ehci *, u32);
37  #ifdef CONFIG_DM_USB
38  static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
39  		  struct ehci_hccr *hccr, struct ehci_hcor *hcor);
40  #else
41  static int ehci_fsl_init(int index, struct usb_ehci *ehci,
42  			 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
43  #endif
44  
45  /* Check USB PHY clock valid */
46  static int usb_phy_clk_valid(struct usb_ehci *ehci)
47  {
48  	if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
49  			in_be32(&ehci->prictrl))) {
50  		printf("USB PHY clock invalid!\n");
51  		return 0;
52  	} else {
53  		return 1;
54  	}
55  }
56  
57  #ifdef CONFIG_DM_USB
58  static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
59  {
60  	struct ehci_fsl_priv *priv = dev_get_priv(dev);
61  	const void *prop;
62  
63  	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
64  			   NULL);
65  	if (prop) {
66  		priv->phy_type = (char *)prop;
67  		debug("phy_type %s\n", priv->phy_type);
68  	}
69  
70  	return 0;
71  }
72  
73  static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
74  {
75  	struct usb_ehci *ehci = NULL;
76  	struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
77  						   ehci);
78  
79  	ehci = (struct usb_ehci *)priv->hcd_base;
80  	if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
81  		return -ENXIO;
82  
83  	return 0;
84  }
85  
86  static const struct ehci_ops fsl_ehci_ops = {
87  	.init_after_reset = ehci_fsl_init_after_reset,
88  };
89  
90  static int ehci_fsl_probe(struct udevice *dev)
91  {
92  	struct ehci_fsl_priv *priv = dev_get_priv(dev);
93  	struct usb_ehci *ehci = NULL;
94  	struct ehci_hccr *hccr;
95  	struct ehci_hcor *hcor;
96  	struct ehci_ctrl *ehci_ctrl = &priv->ehci;
97  
98  	/*
99  	 * Get the base address for EHCI controller from the device node
100  	 */
101  	priv->hcd_base = devfdt_get_addr(dev);
102  	if (priv->hcd_base == FDT_ADDR_T_NONE) {
103  		debug("Can't get the EHCI register base address\n");
104  		return -ENXIO;
105  	}
106  	ehci = (struct usb_ehci *)priv->hcd_base;
107  	hccr = (struct ehci_hccr *)(&ehci->caplength);
108  	hcor = (struct ehci_hcor *)
109  		((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
110  
111  	ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
112  
113  	if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
114  		return -ENXIO;
115  
116  	debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
117  	      (void *)hccr, (void *)hcor,
118  	      HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
119  
120  	return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
121  }
122  
123  static const struct udevice_id ehci_usb_ids[] = {
124  	{ .compatible = "fsl-usb2-mph", },
125  	{ .compatible = "fsl-usb2-dr", },
126  	{ }
127  };
128  
129  U_BOOT_DRIVER(ehci_fsl) = {
130  	.name	= "ehci_fsl",
131  	.id	= UCLASS_USB,
132  	.of_match = ehci_usb_ids,
133  	.ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
134  	.probe = ehci_fsl_probe,
135  	.remove = ehci_deregister,
136  	.ops	= &ehci_usb_ops,
137  	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
138  	.priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
139  	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
140  };
141  #else
142  /*
143   * Create the appropriate control structures to manage
144   * a new EHCI host controller.
145   *
146   * Excerpts from linux ehci fsl driver.
147   */
148  int ehci_hcd_init(int index, enum usb_init_type init,
149  		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
150  {
151  	struct ehci_ctrl *ehci_ctrl = container_of(hccr,
152  					struct ehci_ctrl, hccr);
153  	struct usb_ehci *ehci = NULL;
154  
155  	switch (index) {
156  	case 0:
157  		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
158  		break;
159  	case 1:
160  		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
161  		break;
162  	default:
163  		printf("ERROR: wrong controller index!!\n");
164  		return -EINVAL;
165  	};
166  
167  	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
168  	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
169  			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
170  
171  	ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
172  
173  	return ehci_fsl_init(index, ehci, *hccr, *hcor);
174  }
175  
176  /*
177   * Destroy the appropriate control structures corresponding
178   * the the EHCI host controller.
179   */
180  int ehci_hcd_stop(int index)
181  {
182  	return 0;
183  }
184  #endif
185  
186  #ifdef CONFIG_DM_USB
187  static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
188  		  struct ehci_hccr *hccr, struct ehci_hcor *hcor)
189  #else
190  static int ehci_fsl_init(int index, struct usb_ehci *ehci,
191  			 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
192  #endif
193  {
194  	const char *phy_type = NULL;
195  #ifndef CONFIG_DM_USB
196  	size_t len;
197  	char current_usb_controller[5];
198  #endif
199  #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
200  	char usb_phy[5];
201  
202  	usb_phy[0] = '\0';
203  #endif
204  	if (has_erratum_a007075()) {
205  		/*
206  		 * A 5ms delay is needed after applying soft-reset to the
207  		 * controller to let external ULPI phy come out of reset.
208  		 * This delay needs to be added before re-initializing
209  		 * the controller after soft-resetting completes
210  		 */
211  		mdelay(5);
212  	}
213  
214  	/* Set to Host mode */
215  	setbits_le32(&ehci->usbmode, CM_HOST);
216  
217  	out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
218  	out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
219  
220  	/* Init phy */
221  #ifdef CONFIG_DM_USB
222  	if (priv->phy_type)
223  		phy_type = priv->phy_type;
224  #else
225  	memset(current_usb_controller, '\0', 5);
226  	snprintf(current_usb_controller, sizeof(current_usb_controller),
227  		 "usb%d", index+1);
228  
229  	if (hwconfig_sub(current_usb_controller, "phy_type"))
230  		phy_type = hwconfig_subarg(current_usb_controller,
231  				"phy_type", &len);
232  #endif
233  	else
234  		phy_type = env_get("usb_phy_type");
235  
236  	if (!phy_type) {
237  #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
238  		/* if none specified assume internal UTMI */
239  		strcpy(usb_phy, "utmi");
240  		phy_type = usb_phy;
241  #else
242  		printf("WARNING: USB phy type not defined !!\n");
243  		return -1;
244  #endif
245  	}
246  
247  	if (!strncmp(phy_type, "utmi", 4)) {
248  #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
249  		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
250  				PHY_CLK_SEL_UTMI);
251  		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
252  				UTMI_PHY_EN);
253  		udelay(1000); /* delay required for PHY Clk to appear */
254  #endif
255  		out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
256  		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
257  				USB_EN);
258  	} else {
259  		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
260  				PHY_CLK_SEL_ULPI);
261  		clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
262  				CONTROL_REGISTER_W1C_MASK, USB_EN);
263  		udelay(1000); /* delay required for PHY Clk to appear */
264  		if (!usb_phy_clk_valid(ehci))
265  			return -EINVAL;
266  		out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
267  	}
268  
269  	out_be32(&ehci->prictrl, 0x0000000c);
270  	out_be32(&ehci->age_cnt_limit, 0x00000040);
271  	out_be32(&ehci->sictrl, 0x00000001);
272  
273  	in_le32(&ehci->usbmode);
274  
275  	if (has_erratum_a007798())
276  		set_txfifothresh(ehci, TXFIFOTHRESH);
277  
278  	if (has_erratum_a004477()) {
279  		/*
280  		 * When reset is issued while any ULPI transaction is ongoing
281  		 * then it may result to corruption of ULPI Function Control
282  		 * Register which eventually causes phy clock to enter low
283  		 * power mode which stops the clock. Thus delay is required
284  		 * before reset to let ongoing ULPI transaction complete.
285  		 */
286  		udelay(1);
287  	}
288  	return 0;
289  }
290  
291  /*
292   * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
293   * to counter DDR latencies in writing data into Tx buffer.
294   * This prevents Tx buffer from getting underrun
295   */
296  static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
297  {
298  	u32 cmd;
299  	cmd = ehci_readl(&ehci->txfilltuning);
300  	cmd &= ~TXFIFO_THRESH_MASK;
301  	cmd |= TXFIFO_THRESH(txfifo_thresh);
302  	ehci_writel(&ehci->txfilltuning, cmd);
303  }
304