arm64: tegra: Fix Tegra194 PCIe EP compatible string

[ Upstream commit bf2942a8b7c38e8cc2d5157b4f0323d7f4e5ec71 ]

The initialization sequence performed by the generic platform drive

arm64: tegra: Fix Tegra194 PCIe EP compatible string

[ Upstream commit bf2942a8b7c38e8cc2d5157b4f0323d7f4e5ec71 ]

The initialization sequence performed by the generic platform driver
pcie-designware-plat.c for a DWC based implementation doesn't work for
Tegra194. Tegra194 has a different initialization sequence requirement
which can only be satisfied by the Tegra194 specific platform driver
pcie-tegra194.c. So, remove the generic compatible string "snps,dw-pcie-ep"
from Tegra194's endpoint controller nodes.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: tegra: Fix DT binding for IO High Voltage entry

[ Upstream commit 6b26c1a034885923822f6c4d94f8644d32bc2481 ]

Fix the device-tree entry that represents I/O High Voltage proper

arm64: tegra: Fix DT binding for IO High Voltage entry

[ Upstream commit 6b26c1a034885923822f6c4d94f8644d32bc2481 ]

Fix the device-tree entry that represents I/O High Voltage property
by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former
entry is deprecated.

Fixes: dbb72e2c305b ("arm64: tegra: Add configuration for PCIe C5 sideband signals")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: tegra: Wrong AON HSP reg property size

The AON HSP node's "reg" property size 0xa0000 will overlap with other
resources. This patch fixes that wrong value with correct size 0x9000

arm64: tegra: Wrong AON HSP reg property size

The AON HSP node's "reg" property size 0xa0000 will overlap with other
resources. This patch fixes that wrong value with correct size 0x90000.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Fixes: a38570c22e9d ("arm64: tegra: Add nodes for TCU on Tegra194")
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Devicetree updates from Olof Johansson:
"As usual, most of the changes are to devicetrees.

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Devicetree updates from Olof Johansson:
"As usual, most of the changes are to devicetrees.

Besides smaller fixes, some refactorings and cleanups, some of the new
platforms and chips (or significant features) supported are below:

Broadcom boards:
- Cisco Meraki MR32 (BCM53016-based)
- BCM2711 (RPi4) display pipeline support

Actions Semi boards:
- Caninos Loucos Labrador SBC (S500-based)
- RoseapplePi SBC (S500-based)

Allwinner SoCs/boards:
- A100 SoC with Perf1 board
- Mali, DMA, Cetrus and IR support for R40 SoC

Amlogic boards:
- Libretch S905x CC V2 board
- Hardkernel ODROID-N2+ board

Aspeed boards/platforms:
- Wistron Mowgli (AST2500-based, Power9 OpenPower server)
- Facebook Wedge400 (AST2500-based, ToR switch)

Hisilicon SoC:
- SD5203 SoC

Nvidia boards:
- Tegra234 VDK, for pre-silicon Orin SoC

NXP i.MX boards:
- Librem 5 phone
- i.MX8MM DDR4 EVK
- Variscite VAR-SOM-MX8MN SoM
- Symphony board
- Tolino Shine 2 HD
- TQMa6 SoM
- Y Soft IOTA Orion

Rockchip boards:
- NanoPi R2S board
- A95X-Z2 board
- more Rock-Pi4 variants

STM32 boards:
- Odyssey SOM board (STM32MP157CAC-based)
- DH DRC02 board

Toshiba SoCs/boards:
- Visconti SoC and TPMV7708 board"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits)
ARM: dts: nspire: Fix SP804 users
arm64: dts: lg: Fix SP804 users
arm64: dts: lg: Fix SP805 clocks
ARM: mstar: Fix up the fallout from moving the dts/dtsi files
ARM: mstar: Add mstar prefix to all of the dtsi/dts files
ARM: mstar: Add interrupt to pm_uart
ARM: mstar: Add interrupt controller to base dtsi
ARM: dts: meson8: remove two invalid interrupt lines from the GPU node
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
arm64: dts: ti: k3-j7200-main: Add USB controller
arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
ARM: dts: hisilicon: add SD5203 dts
ARM: dts: hisilicon: fix the system controller compatible nodes
arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
arm64: dts: zynqmp: Remove undocumented u-boot properties
arm64: dts: zynqmp: Remove additional compatible string for i2c IPs
arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml
...

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arm64: tegra: Add DT binding for AHUB components

This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a ch

arm64: tegra: Add DT binding for AHUB components

This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a child node under ACONNECT
* AHUB includes many HW accelerators and below components are added
as its children.
* ADMAIF
* I2S
* DMIC
* DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does
not have this module)

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing timeout clock to Tegra194 SDMMC nodes

commit 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree")

Tegra194 uses separate SDMMC_LEGACY_TM clock for

arm64: tegra: Add missing timeout clock to Tegra194 SDMMC nodes

commit 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree")

Tegra194 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.

Tegra194 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register.

So, this clock should be kept enabled by SDMMC driver.

Fixes: 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree")
Cc: stable <stable@vger.kernel.org> # 5.4
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1598548861-32373-7-git-send-email-skomatineni@nvidia.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

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arm64: tegra: Properly size register regions for GPU on Tegra194

Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather
than 256 MiB.

Reported-by: Terje Bergström

arm64: tegra: Properly size register regions for GPU on Tegra194

Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather
than 256 MiB.

Reported-by: Terje Bergström <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-By: Terje Bergström <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Wire up pinctrl states for all DPAUX controllers

All four DPAUX controllers on Tegra194 control the pin configuration of
their companion I2C controllers. Wire up all the pi

arm64: tegra: Wire up pinctrl states for all DPAUX controllers

All four DPAUX controllers on Tegra194 control the pin configuration of
their companion I2C controllers. Wire up all the pinctrl states for the
I2C controllers so that their pins can be correctly muxed when needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add the GPU on Tegra194

The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called
GV11B.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off

arm64: tegra: Add the GPU on Tegra194

The GPU found on NVIDIA Tegra194 SoCs is a Volta generation GPU called
GV11B.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add compatible string for Tegra194 CPU complex

On Tegra194, data on valid operating points for the CPUs needs to be
queried from BPMP. However, there is no node representin

arm64: tegra: Add compatible string for Tegra194 CPU complex

On Tegra194, data on valid operating points for the CPUs needs to be
queried from BPMP. However, there is no node representing CPU complex.
So, add a compatible string to the 'cpus' node instead of using dummy
node to bind the cpufreq driver to. Also, add reference to the BPMP
instance for the CPU complex.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove spurious tabs

Remove tabs in places where they don't belong (i.e. where a single space
is sufficient).

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Re-order PCIe aperture mappings

Re-order Tegra194's PCIe aperture mappings to have IO window moved to
64-bit aperture and have the entire 32-bit aperture used for accessing

arm64: tegra: Re-order PCIe aperture mappings

Re-order Tegra194's PCIe aperture mappings to have IO window moved to
64-bit aperture and have the entire 32-bit aperture used for accessing
the configuration space. This makes it to use the entire 32MB of the 32-bit
aperture for ECAM purpose while booting through ACPI.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename cbb@0 to bus@0 on Tegra194

The control backbone is a simple-bus and hence its device tree node
should be named "bus@<unit-address>" according to the bindings.

arm64: tegra: Rename cbb@0 to bus@0 on Tegra194

The control backbone is a simple-bus and hence its device tree node
should be named "bus@<unit-address>" according to the bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix indentation in Tegra194 device tree

Properly indent subsequent lines so that they align with the first line.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Remove unused interrupts from Tegra194 AON GPIO

The AON GPIO controller on Tegra194 currently only uses a single
interrupt, so remove the extra ones.

Signed-off-by

arm64: tegra: Remove unused interrupts from Tegra194 AON GPIO

The AON GPIO controller on Tegra194 currently only uses a single
interrupt, so remove the extra ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Use standard names for SRAM nodes

SRAM nodes should be named sram@<unit-address> to match the bindings.

While at it, also remove the unneeded, custom compatible string

arm64: tegra: Use standard names for SRAM nodes

SRAM nodes should be named sram@<unit-address> to match the bindings.

While at it, also remove the unneeded, custom compatible string for
SRAM partition nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Do not mark display hub as simple bus

The display hub on Tegra186 and Tegra194 is not a simple bus, so drop
the corresponding compatible string.

Signed-off-by: Thi

arm64: tegra: Do not mark display hub as simple bus

The display hub on Tegra186 and Tegra194 is not a simple bus, so drop
the corresponding compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove XUSB pad controller interrupt from XUSB node

The XUSB controller doesn't need the XUSB pad controller's interrupt, so
remove it.

Signed-off-by: Thierry Redi

arm64: tegra: Remove XUSB pad controller interrupt from XUSB node

The XUSB controller doesn't need the XUSB pad controller's interrupt, so
remove it.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Do not mark host1x as simple bus

The host1x is not a simple bus, so drop the corresponding compatible
string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
va

arm64: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling to properly parse this data.

While at it, also remove the "immovable" bit from PCI addresses. All of
these addresses are in fact "movable".

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename sdhci nodes to mmc

The new json-schema based validation tools require SD/MMC controller
nodes to be named mmc. Rename all references to them.

Signed-off-by:

arm64: tegra: Rename sdhci nodes to mmc

The new json-schema based validation tools require SD/MMC controller
nodes to be named mmc. Rename all references to them.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add interrupt-names for host1x

Interrupt names are used to distinguish between the syncpoint and
general host1x interrupts. Make sure they are available in the DT so
th

arm64: tegra: Add interrupt-names for host1x

Interrupt names are used to distinguish between the syncpoint and
general host1x interrupts. Make sure they are available in the DT so
that drivers can use them if necessary.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add interrupt for Tegra194 memory controller

This interrupt can be used for the operating system to be interrupted
when certain events occur.

Signed-off-by: Thierr

arm64: tegra: Add interrupt for Tegra194 memory controller

This interrupt can be used for the operating system to be interrupted
when certain events occur.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Describe interconnect paths on Tegra194

On Tegra194, all clients of the memory subsystem can generally address
40 bits of system memory. However, bit 39 has special meaning

arm64: tegra: Describe interconnect paths on Tegra194

On Tegra194, all clients of the memory subsystem can generally address
40 bits of system memory. However, bit 39 has special meaning and will
cause the memory controller to reorder sectors for block-linear buffer
formats. This is primarily useful for graphics-related devices.

Use of bit 39 must be controlled on a case-by-case basis. Buffers that
are used with bit 39 set by one device may be used with bit 39 cleared
by other devices.

Care must be taken to allocate buffers at addresses that do not require
bit 39 to be set. This is normally not an issue for system memory since
there are no Tegra-based systems with enough RAM to exhaust the 39-bit
physical address space. However, when a device is behind an IOMMU, such
as the ARM SMMU on Tegra194, the IOMMUs input address space can cause
IOVA allocations to happen in this region. This is for example the case
when an operating system implements a top-down allocation policy for IO
virtual addresses.

To account for this, describe the path that memory accesses take through
the system. Memory clients will send requests to the memory controller,
which forwards bits [38:0] of the address either to the external memory
controller or the SMMU, depending on the stream ID of the access. A good
way to describe this is using the interconnects bindings, see:

Documentation/devicetree/bindings/interconnect/interconnect.txt

The standard "dma-mem" path is used to describe the path towards system
memory via the memory controller. A dma-ranges property in the memory
controller's device tree node limits the range of DMA addresses that the
memory clients can use to bits [38:0], ensuring that bit 39 is not used.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v4:
- add additional entries for interconnect-names to match interconnects
- add EMC as destination for interconnect paths

Changes in v3:
- add missing interconnect properties for VIC

Changes in v2:
- use memory client IDs instead of stream IDs (Mikko Perttunen)

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove extra compatible for Tegra194 SDHCI

The SDHCI on Tegra194 is in fact not compatible with the one found on
Tegra186. Remove the extra compatible string to reflect tha

arm64: tegra: Remove extra compatible for Tegra194 SDHCI

The SDHCI on Tegra194 is in fact not compatible with the one found on
Tegra186. Remove the extra compatible string to reflect that.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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