1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64 interconnect-names = "dma-mem", "write"; 65 status = "disabled"; 66 67 snps,write-requests = <1>; 68 snps,read-requests = <3>; 69 snps,burst-map = <0x7>; 70 snps,txpbl = <16>; 71 snps,rxpbl = <8>; 72 }; 73 74 aconnect@2900000 { 75 compatible = "nvidia,tegra194-aconnect", 76 "nvidia,tegra210-aconnect"; 77 clocks = <&bpmp TEGRA194_CLK_APE>, 78 <&bpmp TEGRA194_CLK_APB2APE>; 79 clock-names = "ape", "apb2ape"; 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x02900000 0x02900000 0x200000>; 84 status = "disabled"; 85 86 dma-controller@2930000 { 87 compatible = "nvidia,tegra194-adma", 88 "nvidia,tegra186-adma"; 89 reg = <0x02930000 0x20000>; 90 interrupt-parent = <&agic>; 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 123 #dma-cells = <1>; 124 clocks = <&bpmp TEGRA194_CLK_AHUB>; 125 clock-names = "d_audio"; 126 status = "disabled"; 127 }; 128 129 agic: interrupt-controller@2a40000 { 130 compatible = "nvidia,tegra194-agic", 131 "nvidia,tegra210-agic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x02a41000 0x1000>, 135 <0x02a42000 0x2000>; 136 interrupts = <GIC_SPI 145 137 (GIC_CPU_MASK_SIMPLE(4) | 138 IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA194_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 }; 144 145 pinmux: pinmux@2430000 { 146 compatible = "nvidia,tegra194-pinmux"; 147 reg = <0x2430000 0x17000>, 148 <0xc300000 0x4000>; 149 150 status = "okay"; 151 152 pex_rst_c5_out_state: pex_rst_c5_out { 153 pex_rst { 154 nvidia,pins = "pex_l5_rst_n_pgg1"; 155 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 156 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 157 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 158 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 159 nvidia,tristate = <TEGRA_PIN_DISABLE>; 160 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 161 }; 162 }; 163 164 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 165 clkreq { 166 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 167 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 168 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 169 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 170 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 171 nvidia,tristate = <TEGRA_PIN_DISABLE>; 172 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 173 }; 174 }; 175 }; 176 177 mc: memory-controller@2c00000 { 178 compatible = "nvidia,tegra194-mc"; 179 reg = <0x02c00000 0x100000>, 180 <0x02b80000 0x040000>, 181 <0x01700000 0x100000>; 182 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 183 #interconnect-cells = <1>; 184 status = "disabled"; 185 186 #address-cells = <2>; 187 #size-cells = <2>; 188 189 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 190 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 191 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 192 193 /* 194 * Bit 39 of addresses passing through the memory 195 * controller selects the XBAR format used when memory 196 * is accessed. This is used to transparently access 197 * memory in the XBAR format used by the discrete GPU 198 * (bit 39 set) or Tegra (bit 39 clear). 199 * 200 * As a consequence, the operating system must ensure 201 * that bit 39 is never used implicitly, for example 202 * via an I/O virtual address mapping of an IOMMU. If 203 * devices require access to the XBAR switch, their 204 * drivers must set this bit explicitly. 205 * 206 * Limit the DMA range for memory clients to [38:0]. 207 */ 208 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 209 210 emc: external-memory-controller@2c60000 { 211 compatible = "nvidia,tegra194-emc"; 212 reg = <0x0 0x02c60000 0x0 0x90000>, 213 <0x0 0x01780000 0x0 0x80000>; 214 clocks = <&bpmp TEGRA194_CLK_EMC>; 215 clock-names = "emc"; 216 217 #interconnect-cells = <0>; 218 219 nvidia,bpmp = <&bpmp>; 220 }; 221 }; 222 223 uarta: serial@3100000 { 224 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 225 reg = <0x03100000 0x40>; 226 reg-shift = <2>; 227 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&bpmp TEGRA194_CLK_UARTA>; 229 clock-names = "serial"; 230 resets = <&bpmp TEGRA194_RESET_UARTA>; 231 reset-names = "serial"; 232 status = "disabled"; 233 }; 234 235 uartb: serial@3110000 { 236 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 237 reg = <0x03110000 0x40>; 238 reg-shift = <2>; 239 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&bpmp TEGRA194_CLK_UARTB>; 241 clock-names = "serial"; 242 resets = <&bpmp TEGRA194_RESET_UARTB>; 243 reset-names = "serial"; 244 status = "disabled"; 245 }; 246 247 uartd: serial@3130000 { 248 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 249 reg = <0x03130000 0x40>; 250 reg-shift = <2>; 251 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&bpmp TEGRA194_CLK_UARTD>; 253 clock-names = "serial"; 254 resets = <&bpmp TEGRA194_RESET_UARTD>; 255 reset-names = "serial"; 256 status = "disabled"; 257 }; 258 259 uarte: serial@3140000 { 260 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 261 reg = <0x03140000 0x40>; 262 reg-shift = <2>; 263 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&bpmp TEGRA194_CLK_UARTE>; 265 clock-names = "serial"; 266 resets = <&bpmp TEGRA194_RESET_UARTE>; 267 reset-names = "serial"; 268 status = "disabled"; 269 }; 270 271 uartf: serial@3150000 { 272 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 273 reg = <0x03150000 0x40>; 274 reg-shift = <2>; 275 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&bpmp TEGRA194_CLK_UARTF>; 277 clock-names = "serial"; 278 resets = <&bpmp TEGRA194_RESET_UARTF>; 279 reset-names = "serial"; 280 status = "disabled"; 281 }; 282 283 gen1_i2c: i2c@3160000 { 284 compatible = "nvidia,tegra194-i2c"; 285 reg = <0x03160000 0x10000>; 286 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 clocks = <&bpmp TEGRA194_CLK_I2C1>; 290 clock-names = "div-clk"; 291 resets = <&bpmp TEGRA194_RESET_I2C1>; 292 reset-names = "i2c"; 293 status = "disabled"; 294 }; 295 296 uarth: serial@3170000 { 297 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 298 reg = <0x03170000 0x40>; 299 reg-shift = <2>; 300 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&bpmp TEGRA194_CLK_UARTH>; 302 clock-names = "serial"; 303 resets = <&bpmp TEGRA194_RESET_UARTH>; 304 reset-names = "serial"; 305 status = "disabled"; 306 }; 307 308 cam_i2c: i2c@3180000 { 309 compatible = "nvidia,tegra194-i2c"; 310 reg = <0x03180000 0x10000>; 311 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clocks = <&bpmp TEGRA194_CLK_I2C3>; 315 clock-names = "div-clk"; 316 resets = <&bpmp TEGRA194_RESET_I2C3>; 317 reset-names = "i2c"; 318 status = "disabled"; 319 }; 320 321 /* shares pads with dpaux1 */ 322 dp_aux_ch1_i2c: i2c@3190000 { 323 compatible = "nvidia,tegra194-i2c"; 324 reg = <0x03190000 0x10000>; 325 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clocks = <&bpmp TEGRA194_CLK_I2C4>; 329 clock-names = "div-clk"; 330 resets = <&bpmp TEGRA194_RESET_I2C4>; 331 reset-names = "i2c"; 332 pinctrl-0 = <&state_dpaux1_i2c>; 333 pinctrl-1 = <&state_dpaux1_off>; 334 pinctrl-names = "default", "idle"; 335 status = "disabled"; 336 }; 337 338 /* shares pads with dpaux0 */ 339 dp_aux_ch0_i2c: i2c@31b0000 { 340 compatible = "nvidia,tegra194-i2c"; 341 reg = <0x031b0000 0x10000>; 342 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 clocks = <&bpmp TEGRA194_CLK_I2C6>; 346 clock-names = "div-clk"; 347 resets = <&bpmp TEGRA194_RESET_I2C6>; 348 reset-names = "i2c"; 349 pinctrl-0 = <&state_dpaux0_i2c>; 350 pinctrl-1 = <&state_dpaux0_off>; 351 pinctrl-names = "default", "idle"; 352 status = "disabled"; 353 }; 354 355 /* shares pads with dpaux2 */ 356 dp_aux_ch2_i2c: i2c@31c0000 { 357 compatible = "nvidia,tegra194-i2c"; 358 reg = <0x031c0000 0x10000>; 359 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 clocks = <&bpmp TEGRA194_CLK_I2C7>; 363 clock-names = "div-clk"; 364 resets = <&bpmp TEGRA194_RESET_I2C7>; 365 reset-names = "i2c"; 366 pinctrl-0 = <&state_dpaux2_i2c>; 367 pinctrl-1 = <&state_dpaux2_off>; 368 pinctrl-names = "default", "idle"; 369 status = "disabled"; 370 }; 371 372 /* shares pads with dpaux3 */ 373 dp_aux_ch3_i2c: i2c@31e0000 { 374 compatible = "nvidia,tegra194-i2c"; 375 reg = <0x031e0000 0x10000>; 376 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&bpmp TEGRA194_CLK_I2C9>; 380 clock-names = "div-clk"; 381 resets = <&bpmp TEGRA194_RESET_I2C9>; 382 reset-names = "i2c"; 383 pinctrl-0 = <&state_dpaux3_i2c>; 384 pinctrl-1 = <&state_dpaux3_off>; 385 pinctrl-names = "default", "idle"; 386 status = "disabled"; 387 }; 388 389 pwm1: pwm@3280000 { 390 compatible = "nvidia,tegra194-pwm", 391 "nvidia,tegra186-pwm"; 392 reg = <0x3280000 0x10000>; 393 clocks = <&bpmp TEGRA194_CLK_PWM1>; 394 clock-names = "pwm"; 395 resets = <&bpmp TEGRA194_RESET_PWM1>; 396 reset-names = "pwm"; 397 status = "disabled"; 398 #pwm-cells = <2>; 399 }; 400 401 pwm2: pwm@3290000 { 402 compatible = "nvidia,tegra194-pwm", 403 "nvidia,tegra186-pwm"; 404 reg = <0x3290000 0x10000>; 405 clocks = <&bpmp TEGRA194_CLK_PWM2>; 406 clock-names = "pwm"; 407 resets = <&bpmp TEGRA194_RESET_PWM2>; 408 reset-names = "pwm"; 409 status = "disabled"; 410 #pwm-cells = <2>; 411 }; 412 413 pwm3: pwm@32a0000 { 414 compatible = "nvidia,tegra194-pwm", 415 "nvidia,tegra186-pwm"; 416 reg = <0x32a0000 0x10000>; 417 clocks = <&bpmp TEGRA194_CLK_PWM3>; 418 clock-names = "pwm"; 419 resets = <&bpmp TEGRA194_RESET_PWM3>; 420 reset-names = "pwm"; 421 status = "disabled"; 422 #pwm-cells = <2>; 423 }; 424 425 pwm5: pwm@32c0000 { 426 compatible = "nvidia,tegra194-pwm", 427 "nvidia,tegra186-pwm"; 428 reg = <0x32c0000 0x10000>; 429 clocks = <&bpmp TEGRA194_CLK_PWM5>; 430 clock-names = "pwm"; 431 resets = <&bpmp TEGRA194_RESET_PWM5>; 432 reset-names = "pwm"; 433 status = "disabled"; 434 #pwm-cells = <2>; 435 }; 436 437 pwm6: pwm@32d0000 { 438 compatible = "nvidia,tegra194-pwm", 439 "nvidia,tegra186-pwm"; 440 reg = <0x32d0000 0x10000>; 441 clocks = <&bpmp TEGRA194_CLK_PWM6>; 442 clock-names = "pwm"; 443 resets = <&bpmp TEGRA194_RESET_PWM6>; 444 reset-names = "pwm"; 445 status = "disabled"; 446 #pwm-cells = <2>; 447 }; 448 449 pwm7: pwm@32e0000 { 450 compatible = "nvidia,tegra194-pwm", 451 "nvidia,tegra186-pwm"; 452 reg = <0x32e0000 0x10000>; 453 clocks = <&bpmp TEGRA194_CLK_PWM7>; 454 clock-names = "pwm"; 455 resets = <&bpmp TEGRA194_RESET_PWM7>; 456 reset-names = "pwm"; 457 status = "disabled"; 458 #pwm-cells = <2>; 459 }; 460 461 pwm8: pwm@32f0000 { 462 compatible = "nvidia,tegra194-pwm", 463 "nvidia,tegra186-pwm"; 464 reg = <0x32f0000 0x10000>; 465 clocks = <&bpmp TEGRA194_CLK_PWM8>; 466 clock-names = "pwm"; 467 resets = <&bpmp TEGRA194_RESET_PWM8>; 468 reset-names = "pwm"; 469 status = "disabled"; 470 #pwm-cells = <2>; 471 }; 472 473 sdmmc1: mmc@3400000 { 474 compatible = "nvidia,tegra194-sdhci"; 475 reg = <0x03400000 0x10000>; 476 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 478 clock-names = "sdhci"; 479 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 480 reset-names = "sdhci"; 481 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 482 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 483 interconnect-names = "dma-mem", "write"; 484 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 485 <0x07>; 486 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 487 <0x07>; 488 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 489 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 490 <0x07>; 491 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 492 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 493 nvidia,default-tap = <0x9>; 494 nvidia,default-trim = <0x5>; 495 status = "disabled"; 496 }; 497 498 sdmmc3: mmc@3440000 { 499 compatible = "nvidia,tegra194-sdhci"; 500 reg = <0x03440000 0x10000>; 501 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 503 clock-names = "sdhci"; 504 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 505 reset-names = "sdhci"; 506 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 507 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 508 interconnect-names = "dma-mem", "write"; 509 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 510 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 511 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 512 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 513 <0x07>; 514 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 515 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 516 <0x07>; 517 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 518 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 519 nvidia,default-tap = <0x9>; 520 nvidia,default-trim = <0x5>; 521 status = "disabled"; 522 }; 523 524 sdmmc4: mmc@3460000 { 525 compatible = "nvidia,tegra194-sdhci"; 526 reg = <0x03460000 0x10000>; 527 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 529 clock-names = "sdhci"; 530 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 531 <&bpmp TEGRA194_CLK_PLLC4>; 532 assigned-clock-parents = 533 <&bpmp TEGRA194_CLK_PLLC4>; 534 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 535 reset-names = "sdhci"; 536 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 537 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 538 interconnect-names = "dma-mem", "write"; 539 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 540 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 541 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 542 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 543 <0x0a>; 544 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 545 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 546 <0x0a>; 547 nvidia,default-tap = <0x8>; 548 nvidia,default-trim = <0x14>; 549 nvidia,dqs-trim = <40>; 550 supports-cqe; 551 status = "disabled"; 552 }; 553 554 hda@3510000 { 555 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 556 reg = <0x3510000 0x10000>; 557 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&bpmp TEGRA194_CLK_HDA>, 559 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 560 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 561 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 562 resets = <&bpmp TEGRA194_RESET_HDA>, 563 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 564 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 565 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 566 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 567 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 568 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 569 interconnect-names = "dma-mem", "write"; 570 status = "disabled"; 571 }; 572 573 xusb_padctl: padctl@3520000 { 574 compatible = "nvidia,tegra194-xusb-padctl"; 575 reg = <0x03520000 0x1000>, 576 <0x03540000 0x1000>; 577 reg-names = "padctl", "ao"; 578 579 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 580 reset-names = "padctl"; 581 582 status = "disabled"; 583 584 pads { 585 usb2 { 586 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 587 clock-names = "trk"; 588 589 lanes { 590 usb2-0 { 591 nvidia,function = "xusb"; 592 status = "disabled"; 593 #phy-cells = <0>; 594 }; 595 596 usb2-1 { 597 nvidia,function = "xusb"; 598 status = "disabled"; 599 #phy-cells = <0>; 600 }; 601 602 usb2-2 { 603 nvidia,function = "xusb"; 604 status = "disabled"; 605 #phy-cells = <0>; 606 }; 607 608 usb2-3 { 609 nvidia,function = "xusb"; 610 status = "disabled"; 611 #phy-cells = <0>; 612 }; 613 }; 614 }; 615 616 usb3 { 617 lanes { 618 usb3-0 { 619 nvidia,function = "xusb"; 620 status = "disabled"; 621 #phy-cells = <0>; 622 }; 623 624 usb3-1 { 625 nvidia,function = "xusb"; 626 status = "disabled"; 627 #phy-cells = <0>; 628 }; 629 630 usb3-2 { 631 nvidia,function = "xusb"; 632 status = "disabled"; 633 #phy-cells = <0>; 634 }; 635 636 usb3-3 { 637 nvidia,function = "xusb"; 638 status = "disabled"; 639 #phy-cells = <0>; 640 }; 641 }; 642 }; 643 }; 644 645 ports { 646 usb2-0 { 647 status = "disabled"; 648 }; 649 650 usb2-1 { 651 status = "disabled"; 652 }; 653 654 usb2-2 { 655 status = "disabled"; 656 }; 657 658 usb2-3 { 659 status = "disabled"; 660 }; 661 662 usb3-0 { 663 status = "disabled"; 664 }; 665 666 usb3-1 { 667 status = "disabled"; 668 }; 669 670 usb3-2 { 671 status = "disabled"; 672 }; 673 674 usb3-3 { 675 status = "disabled"; 676 }; 677 }; 678 }; 679 680 usb@3550000 { 681 compatible = "nvidia,tegra194-xudc"; 682 reg = <0x03550000 0x8000>, 683 <0x03558000 0x1000>; 684 reg-names = "base", "fpci"; 685 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 687 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 688 <&bpmp TEGRA194_CLK_XUSB_SS>, 689 <&bpmp TEGRA194_CLK_XUSB_FS>; 690 clock-names = "dev", "ss", "ss_src", "fs_src"; 691 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 692 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 693 power-domain-names = "dev", "ss"; 694 nvidia,xusb-padctl = <&xusb_padctl>; 695 status = "disabled"; 696 }; 697 698 usb@3610000 { 699 compatible = "nvidia,tegra194-xusb"; 700 reg = <0x03610000 0x40000>, 701 <0x03600000 0x10000>; 702 reg-names = "hcd", "fpci"; 703 704 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 706 707 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 708 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 709 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 710 <&bpmp TEGRA194_CLK_XUSB_SS>, 711 <&bpmp TEGRA194_CLK_CLK_M>, 712 <&bpmp TEGRA194_CLK_XUSB_FS>, 713 <&bpmp TEGRA194_CLK_UTMIPLL>, 714 <&bpmp TEGRA194_CLK_CLK_M>, 715 <&bpmp TEGRA194_CLK_PLLE>; 716 clock-names = "xusb_host", "xusb_falcon_src", 717 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 718 "xusb_fs_src", "pll_u_480m", "clk_m", 719 "pll_e"; 720 721 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 722 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 723 power-domain-names = "xusb_host", "xusb_ss"; 724 725 nvidia,xusb-padctl = <&xusb_padctl>; 726 status = "disabled"; 727 }; 728 729 fuse@3820000 { 730 compatible = "nvidia,tegra194-efuse"; 731 reg = <0x03820000 0x10000>; 732 clocks = <&bpmp TEGRA194_CLK_FUSE>; 733 clock-names = "fuse"; 734 }; 735 736 gic: interrupt-controller@3881000 { 737 compatible = "arm,gic-400"; 738 #interrupt-cells = <3>; 739 interrupt-controller; 740 reg = <0x03881000 0x1000>, 741 <0x03882000 0x2000>, 742 <0x03884000 0x2000>, 743 <0x03886000 0x2000>; 744 interrupts = <GIC_PPI 9 745 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 746 interrupt-parent = <&gic>; 747 }; 748 749 cec@3960000 { 750 compatible = "nvidia,tegra194-cec"; 751 reg = <0x03960000 0x10000>; 752 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&bpmp TEGRA194_CLK_CEC>; 754 clock-names = "cec"; 755 status = "disabled"; 756 }; 757 758 hsp_top0: hsp@3c00000 { 759 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 760 reg = <0x03c00000 0xa0000>; 761 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 770 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 771 "shared3", "shared4", "shared5", "shared6", 772 "shared7"; 773 #mbox-cells = <2>; 774 }; 775 776 p2u_hsio_0: phy@3e10000 { 777 compatible = "nvidia,tegra194-p2u"; 778 reg = <0x03e10000 0x10000>; 779 reg-names = "ctl"; 780 781 #phy-cells = <0>; 782 }; 783 784 p2u_hsio_1: phy@3e20000 { 785 compatible = "nvidia,tegra194-p2u"; 786 reg = <0x03e20000 0x10000>; 787 reg-names = "ctl"; 788 789 #phy-cells = <0>; 790 }; 791 792 p2u_hsio_2: phy@3e30000 { 793 compatible = "nvidia,tegra194-p2u"; 794 reg = <0x03e30000 0x10000>; 795 reg-names = "ctl"; 796 797 #phy-cells = <0>; 798 }; 799 800 p2u_hsio_3: phy@3e40000 { 801 compatible = "nvidia,tegra194-p2u"; 802 reg = <0x03e40000 0x10000>; 803 reg-names = "ctl"; 804 805 #phy-cells = <0>; 806 }; 807 808 p2u_hsio_4: phy@3e50000 { 809 compatible = "nvidia,tegra194-p2u"; 810 reg = <0x03e50000 0x10000>; 811 reg-names = "ctl"; 812 813 #phy-cells = <0>; 814 }; 815 816 p2u_hsio_5: phy@3e60000 { 817 compatible = "nvidia,tegra194-p2u"; 818 reg = <0x03e60000 0x10000>; 819 reg-names = "ctl"; 820 821 #phy-cells = <0>; 822 }; 823 824 p2u_hsio_6: phy@3e70000 { 825 compatible = "nvidia,tegra194-p2u"; 826 reg = <0x03e70000 0x10000>; 827 reg-names = "ctl"; 828 829 #phy-cells = <0>; 830 }; 831 832 p2u_hsio_7: phy@3e80000 { 833 compatible = "nvidia,tegra194-p2u"; 834 reg = <0x03e80000 0x10000>; 835 reg-names = "ctl"; 836 837 #phy-cells = <0>; 838 }; 839 840 p2u_hsio_8: phy@3e90000 { 841 compatible = "nvidia,tegra194-p2u"; 842 reg = <0x03e90000 0x10000>; 843 reg-names = "ctl"; 844 845 #phy-cells = <0>; 846 }; 847 848 p2u_hsio_9: phy@3ea0000 { 849 compatible = "nvidia,tegra194-p2u"; 850 reg = <0x03ea0000 0x10000>; 851 reg-names = "ctl"; 852 853 #phy-cells = <0>; 854 }; 855 856 p2u_nvhs_0: phy@3eb0000 { 857 compatible = "nvidia,tegra194-p2u"; 858 reg = <0x03eb0000 0x10000>; 859 reg-names = "ctl"; 860 861 #phy-cells = <0>; 862 }; 863 864 p2u_nvhs_1: phy@3ec0000 { 865 compatible = "nvidia,tegra194-p2u"; 866 reg = <0x03ec0000 0x10000>; 867 reg-names = "ctl"; 868 869 #phy-cells = <0>; 870 }; 871 872 p2u_nvhs_2: phy@3ed0000 { 873 compatible = "nvidia,tegra194-p2u"; 874 reg = <0x03ed0000 0x10000>; 875 reg-names = "ctl"; 876 877 #phy-cells = <0>; 878 }; 879 880 p2u_nvhs_3: phy@3ee0000 { 881 compatible = "nvidia,tegra194-p2u"; 882 reg = <0x03ee0000 0x10000>; 883 reg-names = "ctl"; 884 885 #phy-cells = <0>; 886 }; 887 888 p2u_nvhs_4: phy@3ef0000 { 889 compatible = "nvidia,tegra194-p2u"; 890 reg = <0x03ef0000 0x10000>; 891 reg-names = "ctl"; 892 893 #phy-cells = <0>; 894 }; 895 896 p2u_nvhs_5: phy@3f00000 { 897 compatible = "nvidia,tegra194-p2u"; 898 reg = <0x03f00000 0x10000>; 899 reg-names = "ctl"; 900 901 #phy-cells = <0>; 902 }; 903 904 p2u_nvhs_6: phy@3f10000 { 905 compatible = "nvidia,tegra194-p2u"; 906 reg = <0x03f10000 0x10000>; 907 reg-names = "ctl"; 908 909 #phy-cells = <0>; 910 }; 911 912 p2u_nvhs_7: phy@3f20000 { 913 compatible = "nvidia,tegra194-p2u"; 914 reg = <0x03f20000 0x10000>; 915 reg-names = "ctl"; 916 917 #phy-cells = <0>; 918 }; 919 920 p2u_hsio_10: phy@3f30000 { 921 compatible = "nvidia,tegra194-p2u"; 922 reg = <0x03f30000 0x10000>; 923 reg-names = "ctl"; 924 925 #phy-cells = <0>; 926 }; 927 928 p2u_hsio_11: phy@3f40000 { 929 compatible = "nvidia,tegra194-p2u"; 930 reg = <0x03f40000 0x10000>; 931 reg-names = "ctl"; 932 933 #phy-cells = <0>; 934 }; 935 936 hsp_aon: hsp@c150000 { 937 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 938 reg = <0x0c150000 0xa0000>; 939 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 943 /* 944 * Shared interrupt 0 is routed only to AON/SPE, so 945 * we only have 4 shared interrupts for the CCPLEX. 946 */ 947 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 948 #mbox-cells = <2>; 949 }; 950 951 gen2_i2c: i2c@c240000 { 952 compatible = "nvidia,tegra194-i2c"; 953 reg = <0x0c240000 0x10000>; 954 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 clocks = <&bpmp TEGRA194_CLK_I2C2>; 958 clock-names = "div-clk"; 959 resets = <&bpmp TEGRA194_RESET_I2C2>; 960 reset-names = "i2c"; 961 status = "disabled"; 962 }; 963 964 gen8_i2c: i2c@c250000 { 965 compatible = "nvidia,tegra194-i2c"; 966 reg = <0x0c250000 0x10000>; 967 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 clocks = <&bpmp TEGRA194_CLK_I2C8>; 971 clock-names = "div-clk"; 972 resets = <&bpmp TEGRA194_RESET_I2C8>; 973 reset-names = "i2c"; 974 status = "disabled"; 975 }; 976 977 uartc: serial@c280000 { 978 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 979 reg = <0x0c280000 0x40>; 980 reg-shift = <2>; 981 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&bpmp TEGRA194_CLK_UARTC>; 983 clock-names = "serial"; 984 resets = <&bpmp TEGRA194_RESET_UARTC>; 985 reset-names = "serial"; 986 status = "disabled"; 987 }; 988 989 uartg: serial@c290000 { 990 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 991 reg = <0x0c290000 0x40>; 992 reg-shift = <2>; 993 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&bpmp TEGRA194_CLK_UARTG>; 995 clock-names = "serial"; 996 resets = <&bpmp TEGRA194_RESET_UARTG>; 997 reset-names = "serial"; 998 status = "disabled"; 999 }; 1000 1001 rtc: rtc@c2a0000 { 1002 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1003 reg = <0x0c2a0000 0x10000>; 1004 interrupt-parent = <&pmc>; 1005 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1007 clock-names = "rtc"; 1008 status = "disabled"; 1009 }; 1010 1011 gpio_aon: gpio@c2f0000 { 1012 compatible = "nvidia,tegra194-gpio-aon"; 1013 reg-names = "security", "gpio"; 1014 reg = <0xc2f0000 0x1000>, 1015 <0xc2f1000 0x1000>; 1016 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1017 gpio-controller; 1018 #gpio-cells = <2>; 1019 interrupt-controller; 1020 #interrupt-cells = <2>; 1021 }; 1022 1023 pwm4: pwm@c340000 { 1024 compatible = "nvidia,tegra194-pwm", 1025 "nvidia,tegra186-pwm"; 1026 reg = <0xc340000 0x10000>; 1027 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1028 clock-names = "pwm"; 1029 resets = <&bpmp TEGRA194_RESET_PWM4>; 1030 reset-names = "pwm"; 1031 status = "disabled"; 1032 #pwm-cells = <2>; 1033 }; 1034 1035 pmc: pmc@c360000 { 1036 compatible = "nvidia,tegra194-pmc"; 1037 reg = <0x0c360000 0x10000>, 1038 <0x0c370000 0x10000>, 1039 <0x0c380000 0x10000>, 1040 <0x0c390000 0x10000>, 1041 <0x0c3a0000 0x10000>; 1042 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1043 1044 #interrupt-cells = <2>; 1045 interrupt-controller; 1046 }; 1047 1048 host1x@13e00000 { 1049 compatible = "nvidia,tegra194-host1x"; 1050 reg = <0x13e00000 0x10000>, 1051 <0x13e10000 0x10000>; 1052 reg-names = "hypervisor", "vm"; 1053 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1055 interrupt-names = "syncpt", "host1x"; 1056 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1057 clock-names = "host1x"; 1058 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1059 reset-names = "host1x"; 1060 1061 #address-cells = <1>; 1062 #size-cells = <1>; 1063 1064 ranges = <0x15000000 0x15000000 0x01000000>; 1065 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1066 interconnect-names = "dma-mem"; 1067 1068 display-hub@15200000 { 1069 compatible = "nvidia,tegra194-display"; 1070 reg = <0x15200000 0x00040000>; 1071 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1072 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1073 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1074 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1075 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1076 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1077 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1078 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1079 "wgrp3", "wgrp4", "wgrp5"; 1080 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1081 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1082 clock-names = "disp", "hub"; 1083 status = "disabled"; 1084 1085 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1086 1087 #address-cells = <1>; 1088 #size-cells = <1>; 1089 1090 ranges = <0x15200000 0x15200000 0x40000>; 1091 1092 display@15200000 { 1093 compatible = "nvidia,tegra194-dc"; 1094 reg = <0x15200000 0x10000>; 1095 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1097 clock-names = "dc"; 1098 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1099 reset-names = "dc"; 1100 1101 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1102 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1103 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1104 interconnect-names = "dma-mem", "read-1"; 1105 1106 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1107 nvidia,head = <0>; 1108 }; 1109 1110 display@15210000 { 1111 compatible = "nvidia,tegra194-dc"; 1112 reg = <0x15210000 0x10000>; 1113 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1115 clock-names = "dc"; 1116 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1117 reset-names = "dc"; 1118 1119 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1120 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1121 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1122 interconnect-names = "dma-mem", "read-1"; 1123 1124 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1125 nvidia,head = <1>; 1126 }; 1127 1128 display@15220000 { 1129 compatible = "nvidia,tegra194-dc"; 1130 reg = <0x15220000 0x10000>; 1131 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1133 clock-names = "dc"; 1134 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1135 reset-names = "dc"; 1136 1137 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1138 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1139 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1140 interconnect-names = "dma-mem", "read-1"; 1141 1142 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1143 nvidia,head = <2>; 1144 }; 1145 1146 display@15230000 { 1147 compatible = "nvidia,tegra194-dc"; 1148 reg = <0x15230000 0x10000>; 1149 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1151 clock-names = "dc"; 1152 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1153 reset-names = "dc"; 1154 1155 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1156 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1157 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1158 interconnect-names = "dma-mem", "read-1"; 1159 1160 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1161 nvidia,head = <3>; 1162 }; 1163 }; 1164 1165 vic@15340000 { 1166 compatible = "nvidia,tegra194-vic"; 1167 reg = <0x15340000 0x00040000>; 1168 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1169 clocks = <&bpmp TEGRA194_CLK_VIC>; 1170 clock-names = "vic"; 1171 resets = <&bpmp TEGRA194_RESET_VIC>; 1172 reset-names = "vic"; 1173 1174 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1175 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1176 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1177 interconnect-names = "dma-mem", "write"; 1178 }; 1179 1180 dpaux0: dpaux@155c0000 { 1181 compatible = "nvidia,tegra194-dpaux"; 1182 reg = <0x155c0000 0x10000>; 1183 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1185 <&bpmp TEGRA194_CLK_PLLDP>; 1186 clock-names = "dpaux", "parent"; 1187 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1188 reset-names = "dpaux"; 1189 status = "disabled"; 1190 1191 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1192 1193 state_dpaux0_aux: pinmux-aux { 1194 groups = "dpaux-io"; 1195 function = "aux"; 1196 }; 1197 1198 state_dpaux0_i2c: pinmux-i2c { 1199 groups = "dpaux-io"; 1200 function = "i2c"; 1201 }; 1202 1203 state_dpaux0_off: pinmux-off { 1204 groups = "dpaux-io"; 1205 function = "off"; 1206 }; 1207 1208 i2c-bus { 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 }; 1212 }; 1213 1214 dpaux1: dpaux@155d0000 { 1215 compatible = "nvidia,tegra194-dpaux"; 1216 reg = <0x155d0000 0x10000>; 1217 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1219 <&bpmp TEGRA194_CLK_PLLDP>; 1220 clock-names = "dpaux", "parent"; 1221 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1222 reset-names = "dpaux"; 1223 status = "disabled"; 1224 1225 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1226 1227 state_dpaux1_aux: pinmux-aux { 1228 groups = "dpaux-io"; 1229 function = "aux"; 1230 }; 1231 1232 state_dpaux1_i2c: pinmux-i2c { 1233 groups = "dpaux-io"; 1234 function = "i2c"; 1235 }; 1236 1237 state_dpaux1_off: pinmux-off { 1238 groups = "dpaux-io"; 1239 function = "off"; 1240 }; 1241 1242 i2c-bus { 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 }; 1246 }; 1247 1248 dpaux2: dpaux@155e0000 { 1249 compatible = "nvidia,tegra194-dpaux"; 1250 reg = <0x155e0000 0x10000>; 1251 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1253 <&bpmp TEGRA194_CLK_PLLDP>; 1254 clock-names = "dpaux", "parent"; 1255 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1256 reset-names = "dpaux"; 1257 status = "disabled"; 1258 1259 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1260 1261 state_dpaux2_aux: pinmux-aux { 1262 groups = "dpaux-io"; 1263 function = "aux"; 1264 }; 1265 1266 state_dpaux2_i2c: pinmux-i2c { 1267 groups = "dpaux-io"; 1268 function = "i2c"; 1269 }; 1270 1271 state_dpaux2_off: pinmux-off { 1272 groups = "dpaux-io"; 1273 function = "off"; 1274 }; 1275 1276 i2c-bus { 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 }; 1280 }; 1281 1282 dpaux3: dpaux@155f0000 { 1283 compatible = "nvidia,tegra194-dpaux"; 1284 reg = <0x155f0000 0x10000>; 1285 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1286 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1287 <&bpmp TEGRA194_CLK_PLLDP>; 1288 clock-names = "dpaux", "parent"; 1289 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1290 reset-names = "dpaux"; 1291 status = "disabled"; 1292 1293 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1294 1295 state_dpaux3_aux: pinmux-aux { 1296 groups = "dpaux-io"; 1297 function = "aux"; 1298 }; 1299 1300 state_dpaux3_i2c: pinmux-i2c { 1301 groups = "dpaux-io"; 1302 function = "i2c"; 1303 }; 1304 1305 state_dpaux3_off: pinmux-off { 1306 groups = "dpaux-io"; 1307 function = "off"; 1308 }; 1309 1310 i2c-bus { 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 }; 1314 }; 1315 1316 sor0: sor@15b00000 { 1317 compatible = "nvidia,tegra194-sor"; 1318 reg = <0x15b00000 0x40000>; 1319 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1320 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1321 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1322 <&bpmp TEGRA194_CLK_PLLD>, 1323 <&bpmp TEGRA194_CLK_PLLDP>, 1324 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1325 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1326 clock-names = "sor", "out", "parent", "dp", "safe", 1327 "pad"; 1328 resets = <&bpmp TEGRA194_RESET_SOR0>; 1329 reset-names = "sor"; 1330 pinctrl-0 = <&state_dpaux0_aux>; 1331 pinctrl-1 = <&state_dpaux0_i2c>; 1332 pinctrl-2 = <&state_dpaux0_off>; 1333 pinctrl-names = "aux", "i2c", "off"; 1334 status = "disabled"; 1335 1336 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1337 nvidia,interface = <0>; 1338 }; 1339 1340 sor1: sor@15b40000 { 1341 compatible = "nvidia,tegra194-sor"; 1342 reg = <0x15b40000 0x40000>; 1343 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1344 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1345 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1346 <&bpmp TEGRA194_CLK_PLLD2>, 1347 <&bpmp TEGRA194_CLK_PLLDP>, 1348 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1349 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1350 clock-names = "sor", "out", "parent", "dp", "safe", 1351 "pad"; 1352 resets = <&bpmp TEGRA194_RESET_SOR1>; 1353 reset-names = "sor"; 1354 pinctrl-0 = <&state_dpaux1_aux>; 1355 pinctrl-1 = <&state_dpaux1_i2c>; 1356 pinctrl-2 = <&state_dpaux1_off>; 1357 pinctrl-names = "aux", "i2c", "off"; 1358 status = "disabled"; 1359 1360 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1361 nvidia,interface = <1>; 1362 }; 1363 1364 sor2: sor@15b80000 { 1365 compatible = "nvidia,tegra194-sor"; 1366 reg = <0x15b80000 0x40000>; 1367 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1368 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1369 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1370 <&bpmp TEGRA194_CLK_PLLD3>, 1371 <&bpmp TEGRA194_CLK_PLLDP>, 1372 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1373 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1374 clock-names = "sor", "out", "parent", "dp", "safe", 1375 "pad"; 1376 resets = <&bpmp TEGRA194_RESET_SOR2>; 1377 reset-names = "sor"; 1378 pinctrl-0 = <&state_dpaux2_aux>; 1379 pinctrl-1 = <&state_dpaux2_i2c>; 1380 pinctrl-2 = <&state_dpaux2_off>; 1381 pinctrl-names = "aux", "i2c", "off"; 1382 status = "disabled"; 1383 1384 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1385 nvidia,interface = <2>; 1386 }; 1387 1388 sor3: sor@15bc0000 { 1389 compatible = "nvidia,tegra194-sor"; 1390 reg = <0x15bc0000 0x40000>; 1391 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1393 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1394 <&bpmp TEGRA194_CLK_PLLD4>, 1395 <&bpmp TEGRA194_CLK_PLLDP>, 1396 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1397 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1398 clock-names = "sor", "out", "parent", "dp", "safe", 1399 "pad"; 1400 resets = <&bpmp TEGRA194_RESET_SOR3>; 1401 reset-names = "sor"; 1402 pinctrl-0 = <&state_dpaux3_aux>; 1403 pinctrl-1 = <&state_dpaux3_i2c>; 1404 pinctrl-2 = <&state_dpaux3_off>; 1405 pinctrl-names = "aux", "i2c", "off"; 1406 status = "disabled"; 1407 1408 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1409 nvidia,interface = <3>; 1410 }; 1411 }; 1412 1413 gpu@17000000 { 1414 compatible = "nvidia,gv11b"; 1415 reg = <0x17000000 0x1000000>, 1416 <0x18000000 0x1000000>; 1417 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1419 interrupt-names = "stall", "nonstall"; 1420 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1421 <&bpmp TEGRA194_CLK_GPU_PWR>, 1422 <&bpmp TEGRA194_CLK_FUSE>; 1423 clock-names = "gpu", "pwr", "fuse"; 1424 resets = <&bpmp TEGRA194_RESET_GPU>; 1425 reset-names = "gpu"; 1426 dma-coherent; 1427 1428 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1429 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1430 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1431 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1432 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1433 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1434 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1435 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1436 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1437 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1438 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1439 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1440 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1441 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1442 "read-1", "read-1-hp", "write-1", 1443 "read-2", "read-2-hp", "write-2", 1444 "read-3", "read-3-hp", "write-3"; 1445 }; 1446 }; 1447 1448 pcie@14100000 { 1449 compatible = "nvidia,tegra194-pcie"; 1450 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1451 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1452 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1453 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1454 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1455 reg-names = "appl", "config", "atu_dma", "dbi"; 1456 1457 status = "disabled"; 1458 1459 #address-cells = <3>; 1460 #size-cells = <2>; 1461 device_type = "pci"; 1462 num-lanes = <1>; 1463 num-viewport = <8>; 1464 linux,pci-domain = <1>; 1465 1466 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1467 clock-names = "core"; 1468 1469 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1470 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1471 reset-names = "apb", "core"; 1472 1473 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1474 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1475 interrupt-names = "intr", "msi"; 1476 1477 #interrupt-cells = <1>; 1478 interrupt-map-mask = <0 0 0 0>; 1479 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1480 1481 nvidia,bpmp = <&bpmp 1>; 1482 1483 nvidia,aspm-cmrt-us = <60>; 1484 nvidia,aspm-pwr-on-t-us = <20>; 1485 nvidia,aspm-l0s-entrance-latency-us = <3>; 1486 1487 bus-range = <0x0 0xff>; 1488 1489 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1490 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1491 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1492 1493 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1494 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1495 interconnect-names = "read", "write"; 1496 }; 1497 1498 pcie@14120000 { 1499 compatible = "nvidia,tegra194-pcie"; 1500 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1501 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1502 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1503 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1504 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1505 reg-names = "appl", "config", "atu_dma", "dbi"; 1506 1507 status = "disabled"; 1508 1509 #address-cells = <3>; 1510 #size-cells = <2>; 1511 device_type = "pci"; 1512 num-lanes = <1>; 1513 num-viewport = <8>; 1514 linux,pci-domain = <2>; 1515 1516 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1517 clock-names = "core"; 1518 1519 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1520 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1521 reset-names = "apb", "core"; 1522 1523 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1524 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1525 interrupt-names = "intr", "msi"; 1526 1527 #interrupt-cells = <1>; 1528 interrupt-map-mask = <0 0 0 0>; 1529 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1530 1531 nvidia,bpmp = <&bpmp 2>; 1532 1533 nvidia,aspm-cmrt-us = <60>; 1534 nvidia,aspm-pwr-on-t-us = <20>; 1535 nvidia,aspm-l0s-entrance-latency-us = <3>; 1536 1537 bus-range = <0x0 0xff>; 1538 1539 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1540 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1541 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1542 1543 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1544 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1545 interconnect-names = "read", "write"; 1546 }; 1547 1548 pcie@14140000 { 1549 compatible = "nvidia,tegra194-pcie"; 1550 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1551 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1552 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1553 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1554 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1555 reg-names = "appl", "config", "atu_dma", "dbi"; 1556 1557 status = "disabled"; 1558 1559 #address-cells = <3>; 1560 #size-cells = <2>; 1561 device_type = "pci"; 1562 num-lanes = <1>; 1563 num-viewport = <8>; 1564 linux,pci-domain = <3>; 1565 1566 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1567 clock-names = "core"; 1568 1569 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1570 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1571 reset-names = "apb", "core"; 1572 1573 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1574 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1575 interrupt-names = "intr", "msi"; 1576 1577 #interrupt-cells = <1>; 1578 interrupt-map-mask = <0 0 0 0>; 1579 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1580 1581 nvidia,bpmp = <&bpmp 3>; 1582 1583 nvidia,aspm-cmrt-us = <60>; 1584 nvidia,aspm-pwr-on-t-us = <20>; 1585 nvidia,aspm-l0s-entrance-latency-us = <3>; 1586 1587 bus-range = <0x0 0xff>; 1588 1589 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1590 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 1591 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1592 1593 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1594 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1595 interconnect-names = "read", "write"; 1596 }; 1597 1598 pcie@14160000 { 1599 compatible = "nvidia,tegra194-pcie"; 1600 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1601 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1602 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1603 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1604 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1605 reg-names = "appl", "config", "atu_dma", "dbi"; 1606 1607 status = "disabled"; 1608 1609 #address-cells = <3>; 1610 #size-cells = <2>; 1611 device_type = "pci"; 1612 num-lanes = <4>; 1613 num-viewport = <8>; 1614 linux,pci-domain = <4>; 1615 1616 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1617 clock-names = "core"; 1618 1619 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1620 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1621 reset-names = "apb", "core"; 1622 1623 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1624 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1625 interrupt-names = "intr", "msi"; 1626 1627 #interrupt-cells = <1>; 1628 interrupt-map-mask = <0 0 0 0>; 1629 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1630 1631 nvidia,bpmp = <&bpmp 4>; 1632 1633 nvidia,aspm-cmrt-us = <60>; 1634 nvidia,aspm-pwr-on-t-us = <20>; 1635 nvidia,aspm-l0s-entrance-latency-us = <3>; 1636 1637 bus-range = <0x0 0xff>; 1638 1639 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1640 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1641 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1642 1643 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1644 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1645 interconnect-names = "read", "write"; 1646 }; 1647 1648 pcie@14180000 { 1649 compatible = "nvidia,tegra194-pcie"; 1650 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1651 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1652 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1653 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1654 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1655 reg-names = "appl", "config", "atu_dma", "dbi"; 1656 1657 status = "disabled"; 1658 1659 #address-cells = <3>; 1660 #size-cells = <2>; 1661 device_type = "pci"; 1662 num-lanes = <8>; 1663 num-viewport = <8>; 1664 linux,pci-domain = <0>; 1665 1666 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1667 clock-names = "core"; 1668 1669 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1670 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1671 reset-names = "apb", "core"; 1672 1673 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1674 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1675 interrupt-names = "intr", "msi"; 1676 1677 #interrupt-cells = <1>; 1678 interrupt-map-mask = <0 0 0 0>; 1679 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1680 1681 nvidia,bpmp = <&bpmp 0>; 1682 1683 nvidia,aspm-cmrt-us = <60>; 1684 nvidia,aspm-pwr-on-t-us = <20>; 1685 nvidia,aspm-l0s-entrance-latency-us = <3>; 1686 1687 bus-range = <0x0 0xff>; 1688 1689 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1690 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1691 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1692 1693 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1694 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1695 interconnect-names = "read", "write"; 1696 }; 1697 1698 pcie@141a0000 { 1699 compatible = "nvidia,tegra194-pcie"; 1700 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1701 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1702 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1703 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1704 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1705 reg-names = "appl", "config", "atu_dma", "dbi"; 1706 1707 status = "disabled"; 1708 1709 #address-cells = <3>; 1710 #size-cells = <2>; 1711 device_type = "pci"; 1712 num-lanes = <8>; 1713 num-viewport = <8>; 1714 linux,pci-domain = <5>; 1715 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1718 1719 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1720 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1721 clock-names = "core", "core_m"; 1722 1723 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1724 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1725 reset-names = "apb", "core"; 1726 1727 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1728 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1729 interrupt-names = "intr", "msi"; 1730 1731 nvidia,bpmp = <&bpmp 5>; 1732 1733 #interrupt-cells = <1>; 1734 interrupt-map-mask = <0 0 0 0>; 1735 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1736 1737 nvidia,aspm-cmrt-us = <60>; 1738 nvidia,aspm-pwr-on-t-us = <20>; 1739 nvidia,aspm-l0s-entrance-latency-us = <3>; 1740 1741 bus-range = <0x0 0xff>; 1742 1743 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1744 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1745 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1746 1747 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1748 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1749 interconnect-names = "read", "write"; 1750 }; 1751 1752 pcie_ep@14160000 { 1753 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1754 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1755 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1756 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1757 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1758 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1759 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1760 1761 status = "disabled"; 1762 1763 num-lanes = <4>; 1764 num-ib-windows = <2>; 1765 num-ob-windows = <8>; 1766 1767 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1768 clock-names = "core"; 1769 1770 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1771 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1772 reset-names = "apb", "core"; 1773 1774 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1775 interrupt-names = "intr"; 1776 1777 nvidia,bpmp = <&bpmp 4>; 1778 1779 nvidia,aspm-cmrt-us = <60>; 1780 nvidia,aspm-pwr-on-t-us = <20>; 1781 nvidia,aspm-l0s-entrance-latency-us = <3>; 1782 }; 1783 1784 pcie_ep@14180000 { 1785 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1786 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1787 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1788 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1789 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1790 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1791 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1792 1793 status = "disabled"; 1794 1795 num-lanes = <8>; 1796 num-ib-windows = <2>; 1797 num-ob-windows = <8>; 1798 1799 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1800 clock-names = "core"; 1801 1802 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1803 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1804 reset-names = "apb", "core"; 1805 1806 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1807 interrupt-names = "intr"; 1808 1809 nvidia,bpmp = <&bpmp 0>; 1810 1811 nvidia,aspm-cmrt-us = <60>; 1812 nvidia,aspm-pwr-on-t-us = <20>; 1813 nvidia,aspm-l0s-entrance-latency-us = <3>; 1814 }; 1815 1816 pcie_ep@141a0000 { 1817 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1818 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1819 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1820 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1821 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1822 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1823 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1824 1825 status = "disabled"; 1826 1827 num-lanes = <8>; 1828 num-ib-windows = <2>; 1829 num-ob-windows = <8>; 1830 1831 pinctrl-names = "default"; 1832 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 1833 1834 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 1835 clock-names = "core"; 1836 1837 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1838 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1839 reset-names = "apb", "core"; 1840 1841 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1842 interrupt-names = "intr"; 1843 1844 nvidia,bpmp = <&bpmp 5>; 1845 1846 nvidia,aspm-cmrt-us = <60>; 1847 nvidia,aspm-pwr-on-t-us = <20>; 1848 nvidia,aspm-l0s-entrance-latency-us = <3>; 1849 }; 1850 1851 sram@40000000 { 1852 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 1853 reg = <0x0 0x40000000 0x0 0x50000>; 1854 #address-cells = <1>; 1855 #size-cells = <1>; 1856 ranges = <0x0 0x0 0x40000000 0x50000>; 1857 1858 cpu_bpmp_tx: sram@4e000 { 1859 reg = <0x4e000 0x1000>; 1860 label = "cpu-bpmp-tx"; 1861 pool; 1862 }; 1863 1864 cpu_bpmp_rx: sram@4f000 { 1865 reg = <0x4f000 0x1000>; 1866 label = "cpu-bpmp-rx"; 1867 pool; 1868 }; 1869 }; 1870 1871 bpmp: bpmp { 1872 compatible = "nvidia,tegra186-bpmp"; 1873 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1874 TEGRA_HSP_DB_MASTER_BPMP>; 1875 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1876 #clock-cells = <1>; 1877 #reset-cells = <1>; 1878 #power-domain-cells = <1>; 1879 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 1880 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 1881 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 1882 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 1883 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1884 1885 bpmp_i2c: i2c { 1886 compatible = "nvidia,tegra186-bpmp-i2c"; 1887 nvidia,bpmp-bus-id = <5>; 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 }; 1891 1892 bpmp_thermal: thermal { 1893 compatible = "nvidia,tegra186-bpmp-thermal"; 1894 #thermal-sensor-cells = <1>; 1895 }; 1896 }; 1897 1898 cpus { 1899 compatible = "nvidia,tegra194-ccplex"; 1900 nvidia,bpmp = <&bpmp>; 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 1904 cpu0_0: cpu@0 { 1905 compatible = "nvidia,tegra194-carmel"; 1906 device_type = "cpu"; 1907 reg = <0x000>; 1908 enable-method = "psci"; 1909 i-cache-size = <131072>; 1910 i-cache-line-size = <64>; 1911 i-cache-sets = <512>; 1912 d-cache-size = <65536>; 1913 d-cache-line-size = <64>; 1914 d-cache-sets = <256>; 1915 next-level-cache = <&l2c_0>; 1916 }; 1917 1918 cpu0_1: cpu@1 { 1919 compatible = "nvidia,tegra194-carmel"; 1920 device_type = "cpu"; 1921 reg = <0x001>; 1922 enable-method = "psci"; 1923 i-cache-size = <131072>; 1924 i-cache-line-size = <64>; 1925 i-cache-sets = <512>; 1926 d-cache-size = <65536>; 1927 d-cache-line-size = <64>; 1928 d-cache-sets = <256>; 1929 next-level-cache = <&l2c_0>; 1930 }; 1931 1932 cpu1_0: cpu@100 { 1933 compatible = "nvidia,tegra194-carmel"; 1934 device_type = "cpu"; 1935 reg = <0x100>; 1936 enable-method = "psci"; 1937 i-cache-size = <131072>; 1938 i-cache-line-size = <64>; 1939 i-cache-sets = <512>; 1940 d-cache-size = <65536>; 1941 d-cache-line-size = <64>; 1942 d-cache-sets = <256>; 1943 next-level-cache = <&l2c_1>; 1944 }; 1945 1946 cpu1_1: cpu@101 { 1947 compatible = "nvidia,tegra194-carmel"; 1948 device_type = "cpu"; 1949 reg = <0x101>; 1950 enable-method = "psci"; 1951 i-cache-size = <131072>; 1952 i-cache-line-size = <64>; 1953 i-cache-sets = <512>; 1954 d-cache-size = <65536>; 1955 d-cache-line-size = <64>; 1956 d-cache-sets = <256>; 1957 next-level-cache = <&l2c_1>; 1958 }; 1959 1960 cpu2_0: cpu@200 { 1961 compatible = "nvidia,tegra194-carmel"; 1962 device_type = "cpu"; 1963 reg = <0x200>; 1964 enable-method = "psci"; 1965 i-cache-size = <131072>; 1966 i-cache-line-size = <64>; 1967 i-cache-sets = <512>; 1968 d-cache-size = <65536>; 1969 d-cache-line-size = <64>; 1970 d-cache-sets = <256>; 1971 next-level-cache = <&l2c_2>; 1972 }; 1973 1974 cpu2_1: cpu@201 { 1975 compatible = "nvidia,tegra194-carmel"; 1976 device_type = "cpu"; 1977 reg = <0x201>; 1978 enable-method = "psci"; 1979 i-cache-size = <131072>; 1980 i-cache-line-size = <64>; 1981 i-cache-sets = <512>; 1982 d-cache-size = <65536>; 1983 d-cache-line-size = <64>; 1984 d-cache-sets = <256>; 1985 next-level-cache = <&l2c_2>; 1986 }; 1987 1988 cpu3_0: cpu@300 { 1989 compatible = "nvidia,tegra194-carmel"; 1990 device_type = "cpu"; 1991 reg = <0x300>; 1992 enable-method = "psci"; 1993 i-cache-size = <131072>; 1994 i-cache-line-size = <64>; 1995 i-cache-sets = <512>; 1996 d-cache-size = <65536>; 1997 d-cache-line-size = <64>; 1998 d-cache-sets = <256>; 1999 next-level-cache = <&l2c_3>; 2000 }; 2001 2002 cpu3_1: cpu@301 { 2003 compatible = "nvidia,tegra194-carmel"; 2004 device_type = "cpu"; 2005 reg = <0x301>; 2006 enable-method = "psci"; 2007 i-cache-size = <131072>; 2008 i-cache-line-size = <64>; 2009 i-cache-sets = <512>; 2010 d-cache-size = <65536>; 2011 d-cache-line-size = <64>; 2012 d-cache-sets = <256>; 2013 next-level-cache = <&l2c_3>; 2014 }; 2015 2016 cpu-map { 2017 cluster0 { 2018 core0 { 2019 cpu = <&cpu0_0>; 2020 }; 2021 2022 core1 { 2023 cpu = <&cpu0_1>; 2024 }; 2025 }; 2026 2027 cluster1 { 2028 core0 { 2029 cpu = <&cpu1_0>; 2030 }; 2031 2032 core1 { 2033 cpu = <&cpu1_1>; 2034 }; 2035 }; 2036 2037 cluster2 { 2038 core0 { 2039 cpu = <&cpu2_0>; 2040 }; 2041 2042 core1 { 2043 cpu = <&cpu2_1>; 2044 }; 2045 }; 2046 2047 cluster3 { 2048 core0 { 2049 cpu = <&cpu3_0>; 2050 }; 2051 2052 core1 { 2053 cpu = <&cpu3_1>; 2054 }; 2055 }; 2056 }; 2057 2058 l2c_0: l2-cache0 { 2059 cache-size = <2097152>; 2060 cache-line-size = <64>; 2061 cache-sets = <2048>; 2062 next-level-cache = <&l3c>; 2063 }; 2064 2065 l2c_1: l2-cache1 { 2066 cache-size = <2097152>; 2067 cache-line-size = <64>; 2068 cache-sets = <2048>; 2069 next-level-cache = <&l3c>; 2070 }; 2071 2072 l2c_2: l2-cache2 { 2073 cache-size = <2097152>; 2074 cache-line-size = <64>; 2075 cache-sets = <2048>; 2076 next-level-cache = <&l3c>; 2077 }; 2078 2079 l2c_3: l2-cache3 { 2080 cache-size = <2097152>; 2081 cache-line-size = <64>; 2082 cache-sets = <2048>; 2083 next-level-cache = <&l3c>; 2084 }; 2085 2086 l3c: l3-cache { 2087 cache-size = <4194304>; 2088 cache-line-size = <64>; 2089 cache-sets = <4096>; 2090 }; 2091 }; 2092 2093 psci { 2094 compatible = "arm,psci-1.0"; 2095 status = "okay"; 2096 method = "smc"; 2097 }; 2098 2099 tcu: tcu { 2100 compatible = "nvidia,tegra194-tcu"; 2101 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2102 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2103 mbox-names = "rx", "tx"; 2104 }; 2105 2106 thermal-zones { 2107 cpu { 2108 thermal-sensors = <&{/bpmp/thermal} 2109 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2110 status = "disabled"; 2111 }; 2112 2113 gpu { 2114 thermal-sensors = <&{/bpmp/thermal} 2115 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2116 status = "disabled"; 2117 }; 2118 2119 aux { 2120 thermal-sensors = <&{/bpmp/thermal} 2121 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2122 status = "disabled"; 2123 }; 2124 2125 pllx { 2126 thermal-sensors = <&{/bpmp/thermal} 2127 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2128 status = "disabled"; 2129 }; 2130 2131 ao { 2132 thermal-sensors = <&{/bpmp/thermal} 2133 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2134 status = "disabled"; 2135 }; 2136 2137 tj { 2138 thermal-sensors = <&{/bpmp/thermal} 2139 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2140 status = "disabled"; 2141 }; 2142 }; 2143 2144 timer { 2145 compatible = "arm,armv8-timer"; 2146 interrupts = <GIC_PPI 13 2147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2148 <GIC_PPI 14 2149 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2150 <GIC_PPI 11 2151 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2152 <GIC_PPI 10 2153 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2154 interrupt-parent = <&gic>; 2155 always-on; 2156 }; 2157}; 2158