1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64 interconnect-names = "dma-mem", "write"; 65 status = "disabled"; 66 67 snps,write-requests = <1>; 68 snps,read-requests = <3>; 69 snps,burst-map = <0x7>; 70 snps,txpbl = <16>; 71 snps,rxpbl = <8>; 72 }; 73 74 aconnect@2900000 { 75 compatible = "nvidia,tegra194-aconnect", 76 "nvidia,tegra210-aconnect"; 77 clocks = <&bpmp TEGRA194_CLK_APE>, 78 <&bpmp TEGRA194_CLK_APB2APE>; 79 clock-names = "ape", "apb2ape"; 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x02900000 0x02900000 0x200000>; 84 status = "disabled"; 85 86 dma-controller@2930000 { 87 compatible = "nvidia,tegra194-adma", 88 "nvidia,tegra186-adma"; 89 reg = <0x02930000 0x20000>; 90 interrupt-parent = <&agic>; 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 123 #dma-cells = <1>; 124 clocks = <&bpmp TEGRA194_CLK_AHUB>; 125 clock-names = "d_audio"; 126 status = "disabled"; 127 }; 128 129 agic: interrupt-controller@2a40000 { 130 compatible = "nvidia,tegra194-agic", 131 "nvidia,tegra210-agic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x02a41000 0x1000>, 135 <0x02a42000 0x2000>; 136 interrupts = <GIC_SPI 145 137 (GIC_CPU_MASK_SIMPLE(4) | 138 IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA194_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 }; 144 145 pinmux: pinmux@2430000 { 146 compatible = "nvidia,tegra194-pinmux"; 147 reg = <0x2430000 0x17000>, 148 <0xc300000 0x4000>; 149 150 status = "okay"; 151 152 pex_rst_c5_out_state: pex_rst_c5_out { 153 pex_rst { 154 nvidia,pins = "pex_l5_rst_n_pgg1"; 155 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 156 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 157 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 158 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 159 nvidia,tristate = <TEGRA_PIN_DISABLE>; 160 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 161 }; 162 }; 163 164 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 165 clkreq { 166 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 167 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 168 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 169 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 170 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 171 nvidia,tristate = <TEGRA_PIN_DISABLE>; 172 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 173 }; 174 }; 175 }; 176 177 mc: memory-controller@2c00000 { 178 compatible = "nvidia,tegra194-mc"; 179 reg = <0x02c00000 0x100000>, 180 <0x02b80000 0x040000>, 181 <0x01700000 0x100000>; 182 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 183 #interconnect-cells = <1>; 184 status = "disabled"; 185 186 #address-cells = <2>; 187 #size-cells = <2>; 188 189 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 190 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 191 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 192 193 /* 194 * Bit 39 of addresses passing through the memory 195 * controller selects the XBAR format used when memory 196 * is accessed. This is used to transparently access 197 * memory in the XBAR format used by the discrete GPU 198 * (bit 39 set) or Tegra (bit 39 clear). 199 * 200 * As a consequence, the operating system must ensure 201 * that bit 39 is never used implicitly, for example 202 * via an I/O virtual address mapping of an IOMMU. If 203 * devices require access to the XBAR switch, their 204 * drivers must set this bit explicitly. 205 * 206 * Limit the DMA range for memory clients to [38:0]. 207 */ 208 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 209 210 emc: external-memory-controller@2c60000 { 211 compatible = "nvidia,tegra194-emc"; 212 reg = <0x0 0x02c60000 0x0 0x90000>, 213 <0x0 0x01780000 0x0 0x80000>; 214 clocks = <&bpmp TEGRA194_CLK_EMC>; 215 clock-names = "emc"; 216 217 #interconnect-cells = <0>; 218 219 nvidia,bpmp = <&bpmp>; 220 }; 221 }; 222 223 uarta: serial@3100000 { 224 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 225 reg = <0x03100000 0x40>; 226 reg-shift = <2>; 227 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&bpmp TEGRA194_CLK_UARTA>; 229 clock-names = "serial"; 230 resets = <&bpmp TEGRA194_RESET_UARTA>; 231 reset-names = "serial"; 232 status = "disabled"; 233 }; 234 235 uartb: serial@3110000 { 236 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 237 reg = <0x03110000 0x40>; 238 reg-shift = <2>; 239 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&bpmp TEGRA194_CLK_UARTB>; 241 clock-names = "serial"; 242 resets = <&bpmp TEGRA194_RESET_UARTB>; 243 reset-names = "serial"; 244 status = "disabled"; 245 }; 246 247 uartd: serial@3130000 { 248 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 249 reg = <0x03130000 0x40>; 250 reg-shift = <2>; 251 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&bpmp TEGRA194_CLK_UARTD>; 253 clock-names = "serial"; 254 resets = <&bpmp TEGRA194_RESET_UARTD>; 255 reset-names = "serial"; 256 status = "disabled"; 257 }; 258 259 uarte: serial@3140000 { 260 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 261 reg = <0x03140000 0x40>; 262 reg-shift = <2>; 263 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&bpmp TEGRA194_CLK_UARTE>; 265 clock-names = "serial"; 266 resets = <&bpmp TEGRA194_RESET_UARTE>; 267 reset-names = "serial"; 268 status = "disabled"; 269 }; 270 271 uartf: serial@3150000 { 272 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 273 reg = <0x03150000 0x40>; 274 reg-shift = <2>; 275 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&bpmp TEGRA194_CLK_UARTF>; 277 clock-names = "serial"; 278 resets = <&bpmp TEGRA194_RESET_UARTF>; 279 reset-names = "serial"; 280 status = "disabled"; 281 }; 282 283 gen1_i2c: i2c@3160000 { 284 compatible = "nvidia,tegra194-i2c"; 285 reg = <0x03160000 0x10000>; 286 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 clocks = <&bpmp TEGRA194_CLK_I2C1>; 290 clock-names = "div-clk"; 291 resets = <&bpmp TEGRA194_RESET_I2C1>; 292 reset-names = "i2c"; 293 status = "disabled"; 294 }; 295 296 uarth: serial@3170000 { 297 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 298 reg = <0x03170000 0x40>; 299 reg-shift = <2>; 300 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&bpmp TEGRA194_CLK_UARTH>; 302 clock-names = "serial"; 303 resets = <&bpmp TEGRA194_RESET_UARTH>; 304 reset-names = "serial"; 305 status = "disabled"; 306 }; 307 308 cam_i2c: i2c@3180000 { 309 compatible = "nvidia,tegra194-i2c"; 310 reg = <0x03180000 0x10000>; 311 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clocks = <&bpmp TEGRA194_CLK_I2C3>; 315 clock-names = "div-clk"; 316 resets = <&bpmp TEGRA194_RESET_I2C3>; 317 reset-names = "i2c"; 318 status = "disabled"; 319 }; 320 321 /* shares pads with dpaux1 */ 322 dp_aux_ch1_i2c: i2c@3190000 { 323 compatible = "nvidia,tegra194-i2c"; 324 reg = <0x03190000 0x10000>; 325 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clocks = <&bpmp TEGRA194_CLK_I2C4>; 329 clock-names = "div-clk"; 330 resets = <&bpmp TEGRA194_RESET_I2C4>; 331 reset-names = "i2c"; 332 status = "disabled"; 333 }; 334 335 /* shares pads with dpaux0 */ 336 dp_aux_ch0_i2c: i2c@31b0000 { 337 compatible = "nvidia,tegra194-i2c"; 338 reg = <0x031b0000 0x10000>; 339 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 clocks = <&bpmp TEGRA194_CLK_I2C6>; 343 clock-names = "div-clk"; 344 resets = <&bpmp TEGRA194_RESET_I2C6>; 345 reset-names = "i2c"; 346 status = "disabled"; 347 }; 348 349 gen7_i2c: i2c@31c0000 { 350 compatible = "nvidia,tegra194-i2c"; 351 reg = <0x031c0000 0x10000>; 352 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 clocks = <&bpmp TEGRA194_CLK_I2C7>; 356 clock-names = "div-clk"; 357 resets = <&bpmp TEGRA194_RESET_I2C7>; 358 reset-names = "i2c"; 359 status = "disabled"; 360 }; 361 362 gen9_i2c: i2c@31e0000 { 363 compatible = "nvidia,tegra194-i2c"; 364 reg = <0x031e0000 0x10000>; 365 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clocks = <&bpmp TEGRA194_CLK_I2C9>; 369 clock-names = "div-clk"; 370 resets = <&bpmp TEGRA194_RESET_I2C9>; 371 reset-names = "i2c"; 372 status = "disabled"; 373 }; 374 375 pwm1: pwm@3280000 { 376 compatible = "nvidia,tegra194-pwm", 377 "nvidia,tegra186-pwm"; 378 reg = <0x3280000 0x10000>; 379 clocks = <&bpmp TEGRA194_CLK_PWM1>; 380 clock-names = "pwm"; 381 resets = <&bpmp TEGRA194_RESET_PWM1>; 382 reset-names = "pwm"; 383 status = "disabled"; 384 #pwm-cells = <2>; 385 }; 386 387 pwm2: pwm@3290000 { 388 compatible = "nvidia,tegra194-pwm", 389 "nvidia,tegra186-pwm"; 390 reg = <0x3290000 0x10000>; 391 clocks = <&bpmp TEGRA194_CLK_PWM2>; 392 clock-names = "pwm"; 393 resets = <&bpmp TEGRA194_RESET_PWM2>; 394 reset-names = "pwm"; 395 status = "disabled"; 396 #pwm-cells = <2>; 397 }; 398 399 pwm3: pwm@32a0000 { 400 compatible = "nvidia,tegra194-pwm", 401 "nvidia,tegra186-pwm"; 402 reg = <0x32a0000 0x10000>; 403 clocks = <&bpmp TEGRA194_CLK_PWM3>; 404 clock-names = "pwm"; 405 resets = <&bpmp TEGRA194_RESET_PWM3>; 406 reset-names = "pwm"; 407 status = "disabled"; 408 #pwm-cells = <2>; 409 }; 410 411 pwm5: pwm@32c0000 { 412 compatible = "nvidia,tegra194-pwm", 413 "nvidia,tegra186-pwm"; 414 reg = <0x32c0000 0x10000>; 415 clocks = <&bpmp TEGRA194_CLK_PWM5>; 416 clock-names = "pwm"; 417 resets = <&bpmp TEGRA194_RESET_PWM5>; 418 reset-names = "pwm"; 419 status = "disabled"; 420 #pwm-cells = <2>; 421 }; 422 423 pwm6: pwm@32d0000 { 424 compatible = "nvidia,tegra194-pwm", 425 "nvidia,tegra186-pwm"; 426 reg = <0x32d0000 0x10000>; 427 clocks = <&bpmp TEGRA194_CLK_PWM6>; 428 clock-names = "pwm"; 429 resets = <&bpmp TEGRA194_RESET_PWM6>; 430 reset-names = "pwm"; 431 status = "disabled"; 432 #pwm-cells = <2>; 433 }; 434 435 pwm7: pwm@32e0000 { 436 compatible = "nvidia,tegra194-pwm", 437 "nvidia,tegra186-pwm"; 438 reg = <0x32e0000 0x10000>; 439 clocks = <&bpmp TEGRA194_CLK_PWM7>; 440 clock-names = "pwm"; 441 resets = <&bpmp TEGRA194_RESET_PWM7>; 442 reset-names = "pwm"; 443 status = "disabled"; 444 #pwm-cells = <2>; 445 }; 446 447 pwm8: pwm@32f0000 { 448 compatible = "nvidia,tegra194-pwm", 449 "nvidia,tegra186-pwm"; 450 reg = <0x32f0000 0x10000>; 451 clocks = <&bpmp TEGRA194_CLK_PWM8>; 452 clock-names = "pwm"; 453 resets = <&bpmp TEGRA194_RESET_PWM8>; 454 reset-names = "pwm"; 455 status = "disabled"; 456 #pwm-cells = <2>; 457 }; 458 459 sdmmc1: mmc@3400000 { 460 compatible = "nvidia,tegra194-sdhci"; 461 reg = <0x03400000 0x10000>; 462 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 464 clock-names = "sdhci"; 465 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 466 reset-names = "sdhci"; 467 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 468 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 469 interconnect-names = "dma-mem", "write"; 470 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 471 <0x07>; 472 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 473 <0x07>; 474 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 475 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 476 <0x07>; 477 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 478 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 479 nvidia,default-tap = <0x9>; 480 nvidia,default-trim = <0x5>; 481 status = "disabled"; 482 }; 483 484 sdmmc3: mmc@3440000 { 485 compatible = "nvidia,tegra194-sdhci"; 486 reg = <0x03440000 0x10000>; 487 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 489 clock-names = "sdhci"; 490 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 491 reset-names = "sdhci"; 492 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 493 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 494 interconnect-names = "dma-mem", "write"; 495 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 496 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 497 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 498 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 499 <0x07>; 500 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 501 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 502 <0x07>; 503 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 504 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 505 nvidia,default-tap = <0x9>; 506 nvidia,default-trim = <0x5>; 507 status = "disabled"; 508 }; 509 510 sdmmc4: mmc@3460000 { 511 compatible = "nvidia,tegra194-sdhci"; 512 reg = <0x03460000 0x10000>; 513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 515 clock-names = "sdhci"; 516 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 517 <&bpmp TEGRA194_CLK_PLLC4>; 518 assigned-clock-parents = 519 <&bpmp TEGRA194_CLK_PLLC4>; 520 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 521 reset-names = "sdhci"; 522 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 523 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 524 interconnect-names = "dma-mem", "write"; 525 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 526 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 527 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 528 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 529 <0x0a>; 530 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 531 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 532 <0x0a>; 533 nvidia,default-tap = <0x8>; 534 nvidia,default-trim = <0x14>; 535 nvidia,dqs-trim = <40>; 536 supports-cqe; 537 status = "disabled"; 538 }; 539 540 hda@3510000 { 541 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 542 reg = <0x3510000 0x10000>; 543 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&bpmp TEGRA194_CLK_HDA>, 545 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 546 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 547 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 548 resets = <&bpmp TEGRA194_RESET_HDA>, 549 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 550 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 551 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 552 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 553 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 554 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 555 interconnect-names = "dma-mem", "write"; 556 status = "disabled"; 557 }; 558 559 xusb_padctl: padctl@3520000 { 560 compatible = "nvidia,tegra194-xusb-padctl"; 561 reg = <0x03520000 0x1000>, 562 <0x03540000 0x1000>; 563 reg-names = "padctl", "ao"; 564 565 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 566 reset-names = "padctl"; 567 568 status = "disabled"; 569 570 pads { 571 usb2 { 572 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 573 clock-names = "trk"; 574 575 lanes { 576 usb2-0 { 577 nvidia,function = "xusb"; 578 status = "disabled"; 579 #phy-cells = <0>; 580 }; 581 582 usb2-1 { 583 nvidia,function = "xusb"; 584 status = "disabled"; 585 #phy-cells = <0>; 586 }; 587 588 usb2-2 { 589 nvidia,function = "xusb"; 590 status = "disabled"; 591 #phy-cells = <0>; 592 }; 593 594 usb2-3 { 595 nvidia,function = "xusb"; 596 status = "disabled"; 597 #phy-cells = <0>; 598 }; 599 }; 600 }; 601 602 usb3 { 603 lanes { 604 usb3-0 { 605 nvidia,function = "xusb"; 606 status = "disabled"; 607 #phy-cells = <0>; 608 }; 609 610 usb3-1 { 611 nvidia,function = "xusb"; 612 status = "disabled"; 613 #phy-cells = <0>; 614 }; 615 616 usb3-2 { 617 nvidia,function = "xusb"; 618 status = "disabled"; 619 #phy-cells = <0>; 620 }; 621 622 usb3-3 { 623 nvidia,function = "xusb"; 624 status = "disabled"; 625 #phy-cells = <0>; 626 }; 627 }; 628 }; 629 }; 630 631 ports { 632 usb2-0 { 633 status = "disabled"; 634 }; 635 636 usb2-1 { 637 status = "disabled"; 638 }; 639 640 usb2-2 { 641 status = "disabled"; 642 }; 643 644 usb2-3 { 645 status = "disabled"; 646 }; 647 648 usb3-0 { 649 status = "disabled"; 650 }; 651 652 usb3-1 { 653 status = "disabled"; 654 }; 655 656 usb3-2 { 657 status = "disabled"; 658 }; 659 660 usb3-3 { 661 status = "disabled"; 662 }; 663 }; 664 }; 665 666 usb@3550000 { 667 compatible = "nvidia,tegra194-xudc"; 668 reg = <0x03550000 0x8000>, 669 <0x03558000 0x1000>; 670 reg-names = "base", "fpci"; 671 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 673 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 674 <&bpmp TEGRA194_CLK_XUSB_SS>, 675 <&bpmp TEGRA194_CLK_XUSB_FS>; 676 clock-names = "dev", "ss", "ss_src", "fs_src"; 677 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 678 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 679 power-domain-names = "dev", "ss"; 680 nvidia,xusb-padctl = <&xusb_padctl>; 681 status = "disabled"; 682 }; 683 684 usb@3610000 { 685 compatible = "nvidia,tegra194-xusb"; 686 reg = <0x03610000 0x40000>, 687 <0x03600000 0x10000>; 688 reg-names = "hcd", "fpci"; 689 690 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 692 693 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 694 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 695 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 696 <&bpmp TEGRA194_CLK_XUSB_SS>, 697 <&bpmp TEGRA194_CLK_CLK_M>, 698 <&bpmp TEGRA194_CLK_XUSB_FS>, 699 <&bpmp TEGRA194_CLK_UTMIPLL>, 700 <&bpmp TEGRA194_CLK_CLK_M>, 701 <&bpmp TEGRA194_CLK_PLLE>; 702 clock-names = "xusb_host", "xusb_falcon_src", 703 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 704 "xusb_fs_src", "pll_u_480m", "clk_m", 705 "pll_e"; 706 707 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 708 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 709 power-domain-names = "xusb_host", "xusb_ss"; 710 711 nvidia,xusb-padctl = <&xusb_padctl>; 712 status = "disabled"; 713 }; 714 715 fuse@3820000 { 716 compatible = "nvidia,tegra194-efuse"; 717 reg = <0x03820000 0x10000>; 718 clocks = <&bpmp TEGRA194_CLK_FUSE>; 719 clock-names = "fuse"; 720 }; 721 722 gic: interrupt-controller@3881000 { 723 compatible = "arm,gic-400"; 724 #interrupt-cells = <3>; 725 interrupt-controller; 726 reg = <0x03881000 0x1000>, 727 <0x03882000 0x2000>, 728 <0x03884000 0x2000>, 729 <0x03886000 0x2000>; 730 interrupts = <GIC_PPI 9 731 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 732 interrupt-parent = <&gic>; 733 }; 734 735 cec@3960000 { 736 compatible = "nvidia,tegra194-cec"; 737 reg = <0x03960000 0x10000>; 738 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&bpmp TEGRA194_CLK_CEC>; 740 clock-names = "cec"; 741 status = "disabled"; 742 }; 743 744 hsp_top0: hsp@3c00000 { 745 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 746 reg = <0x03c00000 0xa0000>; 747 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 756 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 757 "shared3", "shared4", "shared5", "shared6", 758 "shared7"; 759 #mbox-cells = <2>; 760 }; 761 762 p2u_hsio_0: phy@3e10000 { 763 compatible = "nvidia,tegra194-p2u"; 764 reg = <0x03e10000 0x10000>; 765 reg-names = "ctl"; 766 767 #phy-cells = <0>; 768 }; 769 770 p2u_hsio_1: phy@3e20000 { 771 compatible = "nvidia,tegra194-p2u"; 772 reg = <0x03e20000 0x10000>; 773 reg-names = "ctl"; 774 775 #phy-cells = <0>; 776 }; 777 778 p2u_hsio_2: phy@3e30000 { 779 compatible = "nvidia,tegra194-p2u"; 780 reg = <0x03e30000 0x10000>; 781 reg-names = "ctl"; 782 783 #phy-cells = <0>; 784 }; 785 786 p2u_hsio_3: phy@3e40000 { 787 compatible = "nvidia,tegra194-p2u"; 788 reg = <0x03e40000 0x10000>; 789 reg-names = "ctl"; 790 791 #phy-cells = <0>; 792 }; 793 794 p2u_hsio_4: phy@3e50000 { 795 compatible = "nvidia,tegra194-p2u"; 796 reg = <0x03e50000 0x10000>; 797 reg-names = "ctl"; 798 799 #phy-cells = <0>; 800 }; 801 802 p2u_hsio_5: phy@3e60000 { 803 compatible = "nvidia,tegra194-p2u"; 804 reg = <0x03e60000 0x10000>; 805 reg-names = "ctl"; 806 807 #phy-cells = <0>; 808 }; 809 810 p2u_hsio_6: phy@3e70000 { 811 compatible = "nvidia,tegra194-p2u"; 812 reg = <0x03e70000 0x10000>; 813 reg-names = "ctl"; 814 815 #phy-cells = <0>; 816 }; 817 818 p2u_hsio_7: phy@3e80000 { 819 compatible = "nvidia,tegra194-p2u"; 820 reg = <0x03e80000 0x10000>; 821 reg-names = "ctl"; 822 823 #phy-cells = <0>; 824 }; 825 826 p2u_hsio_8: phy@3e90000 { 827 compatible = "nvidia,tegra194-p2u"; 828 reg = <0x03e90000 0x10000>; 829 reg-names = "ctl"; 830 831 #phy-cells = <0>; 832 }; 833 834 p2u_hsio_9: phy@3ea0000 { 835 compatible = "nvidia,tegra194-p2u"; 836 reg = <0x03ea0000 0x10000>; 837 reg-names = "ctl"; 838 839 #phy-cells = <0>; 840 }; 841 842 p2u_nvhs_0: phy@3eb0000 { 843 compatible = "nvidia,tegra194-p2u"; 844 reg = <0x03eb0000 0x10000>; 845 reg-names = "ctl"; 846 847 #phy-cells = <0>; 848 }; 849 850 p2u_nvhs_1: phy@3ec0000 { 851 compatible = "nvidia,tegra194-p2u"; 852 reg = <0x03ec0000 0x10000>; 853 reg-names = "ctl"; 854 855 #phy-cells = <0>; 856 }; 857 858 p2u_nvhs_2: phy@3ed0000 { 859 compatible = "nvidia,tegra194-p2u"; 860 reg = <0x03ed0000 0x10000>; 861 reg-names = "ctl"; 862 863 #phy-cells = <0>; 864 }; 865 866 p2u_nvhs_3: phy@3ee0000 { 867 compatible = "nvidia,tegra194-p2u"; 868 reg = <0x03ee0000 0x10000>; 869 reg-names = "ctl"; 870 871 #phy-cells = <0>; 872 }; 873 874 p2u_nvhs_4: phy@3ef0000 { 875 compatible = "nvidia,tegra194-p2u"; 876 reg = <0x03ef0000 0x10000>; 877 reg-names = "ctl"; 878 879 #phy-cells = <0>; 880 }; 881 882 p2u_nvhs_5: phy@3f00000 { 883 compatible = "nvidia,tegra194-p2u"; 884 reg = <0x03f00000 0x10000>; 885 reg-names = "ctl"; 886 887 #phy-cells = <0>; 888 }; 889 890 p2u_nvhs_6: phy@3f10000 { 891 compatible = "nvidia,tegra194-p2u"; 892 reg = <0x03f10000 0x10000>; 893 reg-names = "ctl"; 894 895 #phy-cells = <0>; 896 }; 897 898 p2u_nvhs_7: phy@3f20000 { 899 compatible = "nvidia,tegra194-p2u"; 900 reg = <0x03f20000 0x10000>; 901 reg-names = "ctl"; 902 903 #phy-cells = <0>; 904 }; 905 906 p2u_hsio_10: phy@3f30000 { 907 compatible = "nvidia,tegra194-p2u"; 908 reg = <0x03f30000 0x10000>; 909 reg-names = "ctl"; 910 911 #phy-cells = <0>; 912 }; 913 914 p2u_hsio_11: phy@3f40000 { 915 compatible = "nvidia,tegra194-p2u"; 916 reg = <0x03f40000 0x10000>; 917 reg-names = "ctl"; 918 919 #phy-cells = <0>; 920 }; 921 922 hsp_aon: hsp@c150000 { 923 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 924 reg = <0x0c150000 0xa0000>; 925 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 929 /* 930 * Shared interrupt 0 is routed only to AON/SPE, so 931 * we only have 4 shared interrupts for the CCPLEX. 932 */ 933 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 934 #mbox-cells = <2>; 935 }; 936 937 gen2_i2c: i2c@c240000 { 938 compatible = "nvidia,tegra194-i2c"; 939 reg = <0x0c240000 0x10000>; 940 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 clocks = <&bpmp TEGRA194_CLK_I2C2>; 944 clock-names = "div-clk"; 945 resets = <&bpmp TEGRA194_RESET_I2C2>; 946 reset-names = "i2c"; 947 status = "disabled"; 948 }; 949 950 gen8_i2c: i2c@c250000 { 951 compatible = "nvidia,tegra194-i2c"; 952 reg = <0x0c250000 0x10000>; 953 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 clocks = <&bpmp TEGRA194_CLK_I2C8>; 957 clock-names = "div-clk"; 958 resets = <&bpmp TEGRA194_RESET_I2C8>; 959 reset-names = "i2c"; 960 status = "disabled"; 961 }; 962 963 uartc: serial@c280000 { 964 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 965 reg = <0x0c280000 0x40>; 966 reg-shift = <2>; 967 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&bpmp TEGRA194_CLK_UARTC>; 969 clock-names = "serial"; 970 resets = <&bpmp TEGRA194_RESET_UARTC>; 971 reset-names = "serial"; 972 status = "disabled"; 973 }; 974 975 uartg: serial@c290000 { 976 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 977 reg = <0x0c290000 0x40>; 978 reg-shift = <2>; 979 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&bpmp TEGRA194_CLK_UARTG>; 981 clock-names = "serial"; 982 resets = <&bpmp TEGRA194_RESET_UARTG>; 983 reset-names = "serial"; 984 status = "disabled"; 985 }; 986 987 rtc: rtc@c2a0000 { 988 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 989 reg = <0x0c2a0000 0x10000>; 990 interrupt-parent = <&pmc>; 991 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 993 clock-names = "rtc"; 994 status = "disabled"; 995 }; 996 997 gpio_aon: gpio@c2f0000 { 998 compatible = "nvidia,tegra194-gpio-aon"; 999 reg-names = "security", "gpio"; 1000 reg = <0xc2f0000 0x1000>, 1001 <0xc2f1000 0x1000>; 1002 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1003 gpio-controller; 1004 #gpio-cells = <2>; 1005 interrupt-controller; 1006 #interrupt-cells = <2>; 1007 }; 1008 1009 pwm4: pwm@c340000 { 1010 compatible = "nvidia,tegra194-pwm", 1011 "nvidia,tegra186-pwm"; 1012 reg = <0xc340000 0x10000>; 1013 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1014 clock-names = "pwm"; 1015 resets = <&bpmp TEGRA194_RESET_PWM4>; 1016 reset-names = "pwm"; 1017 status = "disabled"; 1018 #pwm-cells = <2>; 1019 }; 1020 1021 pmc: pmc@c360000 { 1022 compatible = "nvidia,tegra194-pmc"; 1023 reg = <0x0c360000 0x10000>, 1024 <0x0c370000 0x10000>, 1025 <0x0c380000 0x10000>, 1026 <0x0c390000 0x10000>, 1027 <0x0c3a0000 0x10000>; 1028 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1029 1030 #interrupt-cells = <2>; 1031 interrupt-controller; 1032 }; 1033 1034 host1x@13e00000 { 1035 compatible = "nvidia,tegra194-host1x"; 1036 reg = <0x13e00000 0x10000>, 1037 <0x13e10000 0x10000>; 1038 reg-names = "hypervisor", "vm"; 1039 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1041 interrupt-names = "syncpt", "host1x"; 1042 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1043 clock-names = "host1x"; 1044 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1045 reset-names = "host1x"; 1046 1047 #address-cells = <1>; 1048 #size-cells = <1>; 1049 1050 ranges = <0x15000000 0x15000000 0x01000000>; 1051 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1052 interconnect-names = "dma-mem"; 1053 1054 display-hub@15200000 { 1055 compatible = "nvidia,tegra194-display"; 1056 reg = <0x15200000 0x00040000>; 1057 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1058 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1059 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1060 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1061 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1062 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1063 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1064 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1065 "wgrp3", "wgrp4", "wgrp5"; 1066 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1067 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1068 clock-names = "disp", "hub"; 1069 status = "disabled"; 1070 1071 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1072 1073 #address-cells = <1>; 1074 #size-cells = <1>; 1075 1076 ranges = <0x15200000 0x15200000 0x40000>; 1077 1078 display@15200000 { 1079 compatible = "nvidia,tegra194-dc"; 1080 reg = <0x15200000 0x10000>; 1081 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1083 clock-names = "dc"; 1084 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1085 reset-names = "dc"; 1086 1087 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1088 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1089 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1090 interconnect-names = "dma-mem", "read-1"; 1091 1092 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1093 nvidia,head = <0>; 1094 }; 1095 1096 display@15210000 { 1097 compatible = "nvidia,tegra194-dc"; 1098 reg = <0x15210000 0x10000>; 1099 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1101 clock-names = "dc"; 1102 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1103 reset-names = "dc"; 1104 1105 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1106 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1107 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1108 interconnect-names = "dma-mem", "read-1"; 1109 1110 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1111 nvidia,head = <1>; 1112 }; 1113 1114 display@15220000 { 1115 compatible = "nvidia,tegra194-dc"; 1116 reg = <0x15220000 0x10000>; 1117 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1119 clock-names = "dc"; 1120 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1121 reset-names = "dc"; 1122 1123 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1124 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1125 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1126 interconnect-names = "dma-mem", "read-1"; 1127 1128 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1129 nvidia,head = <2>; 1130 }; 1131 1132 display@15230000 { 1133 compatible = "nvidia,tegra194-dc"; 1134 reg = <0x15230000 0x10000>; 1135 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1137 clock-names = "dc"; 1138 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1139 reset-names = "dc"; 1140 1141 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1142 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1143 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1144 interconnect-names = "dma-mem", "read-1"; 1145 1146 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1147 nvidia,head = <3>; 1148 }; 1149 }; 1150 1151 vic@15340000 { 1152 compatible = "nvidia,tegra194-vic"; 1153 reg = <0x15340000 0x00040000>; 1154 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&bpmp TEGRA194_CLK_VIC>; 1156 clock-names = "vic"; 1157 resets = <&bpmp TEGRA194_RESET_VIC>; 1158 reset-names = "vic"; 1159 1160 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1161 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1162 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1163 interconnect-names = "dma-mem", "write"; 1164 }; 1165 1166 dpaux0: dpaux@155c0000 { 1167 compatible = "nvidia,tegra194-dpaux"; 1168 reg = <0x155c0000 0x10000>; 1169 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1171 <&bpmp TEGRA194_CLK_PLLDP>; 1172 clock-names = "dpaux", "parent"; 1173 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1174 reset-names = "dpaux"; 1175 status = "disabled"; 1176 1177 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1178 1179 state_dpaux0_aux: pinmux-aux { 1180 groups = "dpaux-io"; 1181 function = "aux"; 1182 }; 1183 1184 state_dpaux0_i2c: pinmux-i2c { 1185 groups = "dpaux-io"; 1186 function = "i2c"; 1187 }; 1188 1189 state_dpaux0_off: pinmux-off { 1190 groups = "dpaux-io"; 1191 function = "off"; 1192 }; 1193 1194 i2c-bus { 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 }; 1198 }; 1199 1200 dpaux1: dpaux@155d0000 { 1201 compatible = "nvidia,tegra194-dpaux"; 1202 reg = <0x155d0000 0x10000>; 1203 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1205 <&bpmp TEGRA194_CLK_PLLDP>; 1206 clock-names = "dpaux", "parent"; 1207 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1208 reset-names = "dpaux"; 1209 status = "disabled"; 1210 1211 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1212 1213 state_dpaux1_aux: pinmux-aux { 1214 groups = "dpaux-io"; 1215 function = "aux"; 1216 }; 1217 1218 state_dpaux1_i2c: pinmux-i2c { 1219 groups = "dpaux-io"; 1220 function = "i2c"; 1221 }; 1222 1223 state_dpaux1_off: pinmux-off { 1224 groups = "dpaux-io"; 1225 function = "off"; 1226 }; 1227 1228 i2c-bus { 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 }; 1232 }; 1233 1234 dpaux2: dpaux@155e0000 { 1235 compatible = "nvidia,tegra194-dpaux"; 1236 reg = <0x155e0000 0x10000>; 1237 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1239 <&bpmp TEGRA194_CLK_PLLDP>; 1240 clock-names = "dpaux", "parent"; 1241 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1242 reset-names = "dpaux"; 1243 status = "disabled"; 1244 1245 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1246 1247 state_dpaux2_aux: pinmux-aux { 1248 groups = "dpaux-io"; 1249 function = "aux"; 1250 }; 1251 1252 state_dpaux2_i2c: pinmux-i2c { 1253 groups = "dpaux-io"; 1254 function = "i2c"; 1255 }; 1256 1257 state_dpaux2_off: pinmux-off { 1258 groups = "dpaux-io"; 1259 function = "off"; 1260 }; 1261 1262 i2c-bus { 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 }; 1266 }; 1267 1268 dpaux3: dpaux@155f0000 { 1269 compatible = "nvidia,tegra194-dpaux"; 1270 reg = <0x155f0000 0x10000>; 1271 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1272 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1273 <&bpmp TEGRA194_CLK_PLLDP>; 1274 clock-names = "dpaux", "parent"; 1275 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1276 reset-names = "dpaux"; 1277 status = "disabled"; 1278 1279 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1280 1281 state_dpaux3_aux: pinmux-aux { 1282 groups = "dpaux-io"; 1283 function = "aux"; 1284 }; 1285 1286 state_dpaux3_i2c: pinmux-i2c { 1287 groups = "dpaux-io"; 1288 function = "i2c"; 1289 }; 1290 1291 state_dpaux3_off: pinmux-off { 1292 groups = "dpaux-io"; 1293 function = "off"; 1294 }; 1295 1296 i2c-bus { 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 }; 1300 }; 1301 1302 sor0: sor@15b00000 { 1303 compatible = "nvidia,tegra194-sor"; 1304 reg = <0x15b00000 0x40000>; 1305 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1307 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1308 <&bpmp TEGRA194_CLK_PLLD>, 1309 <&bpmp TEGRA194_CLK_PLLDP>, 1310 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1311 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1312 clock-names = "sor", "out", "parent", "dp", "safe", 1313 "pad"; 1314 resets = <&bpmp TEGRA194_RESET_SOR0>; 1315 reset-names = "sor"; 1316 pinctrl-0 = <&state_dpaux0_aux>; 1317 pinctrl-1 = <&state_dpaux0_i2c>; 1318 pinctrl-2 = <&state_dpaux0_off>; 1319 pinctrl-names = "aux", "i2c", "off"; 1320 status = "disabled"; 1321 1322 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1323 nvidia,interface = <0>; 1324 }; 1325 1326 sor1: sor@15b40000 { 1327 compatible = "nvidia,tegra194-sor"; 1328 reg = <0x15b40000 0x40000>; 1329 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1331 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1332 <&bpmp TEGRA194_CLK_PLLD2>, 1333 <&bpmp TEGRA194_CLK_PLLDP>, 1334 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1335 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1336 clock-names = "sor", "out", "parent", "dp", "safe", 1337 "pad"; 1338 resets = <&bpmp TEGRA194_RESET_SOR1>; 1339 reset-names = "sor"; 1340 pinctrl-0 = <&state_dpaux1_aux>; 1341 pinctrl-1 = <&state_dpaux1_i2c>; 1342 pinctrl-2 = <&state_dpaux1_off>; 1343 pinctrl-names = "aux", "i2c", "off"; 1344 status = "disabled"; 1345 1346 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1347 nvidia,interface = <1>; 1348 }; 1349 1350 sor2: sor@15b80000 { 1351 compatible = "nvidia,tegra194-sor"; 1352 reg = <0x15b80000 0x40000>; 1353 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1355 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1356 <&bpmp TEGRA194_CLK_PLLD3>, 1357 <&bpmp TEGRA194_CLK_PLLDP>, 1358 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1359 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1360 clock-names = "sor", "out", "parent", "dp", "safe", 1361 "pad"; 1362 resets = <&bpmp TEGRA194_RESET_SOR2>; 1363 reset-names = "sor"; 1364 pinctrl-0 = <&state_dpaux2_aux>; 1365 pinctrl-1 = <&state_dpaux2_i2c>; 1366 pinctrl-2 = <&state_dpaux2_off>; 1367 pinctrl-names = "aux", "i2c", "off"; 1368 status = "disabled"; 1369 1370 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1371 nvidia,interface = <2>; 1372 }; 1373 1374 sor3: sor@15bc0000 { 1375 compatible = "nvidia,tegra194-sor"; 1376 reg = <0x15bc0000 0x40000>; 1377 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1379 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1380 <&bpmp TEGRA194_CLK_PLLD4>, 1381 <&bpmp TEGRA194_CLK_PLLDP>, 1382 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1383 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1384 clock-names = "sor", "out", "parent", "dp", "safe", 1385 "pad"; 1386 resets = <&bpmp TEGRA194_RESET_SOR3>; 1387 reset-names = "sor"; 1388 pinctrl-0 = <&state_dpaux3_aux>; 1389 pinctrl-1 = <&state_dpaux3_i2c>; 1390 pinctrl-2 = <&state_dpaux3_off>; 1391 pinctrl-names = "aux", "i2c", "off"; 1392 status = "disabled"; 1393 1394 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1395 nvidia,interface = <3>; 1396 }; 1397 }; 1398 1399 gpu@17000000 { 1400 compatible = "nvidia,gv11b"; 1401 reg = <0x17000000 0x10000000>, 1402 <0x18000000 0x10000000>; 1403 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1405 interrupt-names = "stall", "nonstall"; 1406 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1407 <&bpmp TEGRA194_CLK_GPU_PWR>, 1408 <&bpmp TEGRA194_CLK_FUSE>; 1409 clock-names = "gpu", "pwr", "fuse"; 1410 resets = <&bpmp TEGRA194_RESET_GPU>; 1411 reset-names = "gpu"; 1412 dma-coherent; 1413 1414 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1415 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1416 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1417 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1418 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1419 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1420 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1421 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1422 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1423 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1424 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1425 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1426 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1427 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1428 "read-1", "read-1-hp", "write-1", 1429 "read-2", "read-2-hp", "write-2", 1430 "read-3", "read-3-hp", "write-3"; 1431 }; 1432 }; 1433 1434 pcie@14100000 { 1435 compatible = "nvidia,tegra194-pcie"; 1436 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1437 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1438 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1439 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1440 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1441 reg-names = "appl", "config", "atu_dma", "dbi"; 1442 1443 status = "disabled"; 1444 1445 #address-cells = <3>; 1446 #size-cells = <2>; 1447 device_type = "pci"; 1448 num-lanes = <1>; 1449 num-viewport = <8>; 1450 linux,pci-domain = <1>; 1451 1452 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1453 clock-names = "core"; 1454 1455 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1456 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1457 reset-names = "apb", "core"; 1458 1459 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1460 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1461 interrupt-names = "intr", "msi"; 1462 1463 #interrupt-cells = <1>; 1464 interrupt-map-mask = <0 0 0 0>; 1465 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1466 1467 nvidia,bpmp = <&bpmp 1>; 1468 1469 nvidia,aspm-cmrt-us = <60>; 1470 nvidia,aspm-pwr-on-t-us = <20>; 1471 nvidia,aspm-l0s-entrance-latency-us = <3>; 1472 1473 bus-range = <0x0 0xff>; 1474 1475 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1476 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1477 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1478 1479 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1480 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1481 interconnect-names = "read", "write"; 1482 }; 1483 1484 pcie@14120000 { 1485 compatible = "nvidia,tegra194-pcie"; 1486 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1487 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1488 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1489 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1490 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1491 reg-names = "appl", "config", "atu_dma", "dbi"; 1492 1493 status = "disabled"; 1494 1495 #address-cells = <3>; 1496 #size-cells = <2>; 1497 device_type = "pci"; 1498 num-lanes = <1>; 1499 num-viewport = <8>; 1500 linux,pci-domain = <2>; 1501 1502 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1503 clock-names = "core"; 1504 1505 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1506 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1507 reset-names = "apb", "core"; 1508 1509 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1510 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1511 interrupt-names = "intr", "msi"; 1512 1513 #interrupt-cells = <1>; 1514 interrupt-map-mask = <0 0 0 0>; 1515 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1516 1517 nvidia,bpmp = <&bpmp 2>; 1518 1519 nvidia,aspm-cmrt-us = <60>; 1520 nvidia,aspm-pwr-on-t-us = <20>; 1521 nvidia,aspm-l0s-entrance-latency-us = <3>; 1522 1523 bus-range = <0x0 0xff>; 1524 1525 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1526 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1527 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1528 1529 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1530 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1531 interconnect-names = "read", "write"; 1532 }; 1533 1534 pcie@14140000 { 1535 compatible = "nvidia,tegra194-pcie"; 1536 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1537 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1538 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1539 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1540 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1541 reg-names = "appl", "config", "atu_dma", "dbi"; 1542 1543 status = "disabled"; 1544 1545 #address-cells = <3>; 1546 #size-cells = <2>; 1547 device_type = "pci"; 1548 num-lanes = <1>; 1549 num-viewport = <8>; 1550 linux,pci-domain = <3>; 1551 1552 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1553 clock-names = "core"; 1554 1555 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1556 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1557 reset-names = "apb", "core"; 1558 1559 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1560 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1561 interrupt-names = "intr", "msi"; 1562 1563 #interrupt-cells = <1>; 1564 interrupt-map-mask = <0 0 0 0>; 1565 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1566 1567 nvidia,bpmp = <&bpmp 3>; 1568 1569 nvidia,aspm-cmrt-us = <60>; 1570 nvidia,aspm-pwr-on-t-us = <20>; 1571 nvidia,aspm-l0s-entrance-latency-us = <3>; 1572 1573 bus-range = <0x0 0xff>; 1574 1575 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1576 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 1577 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1578 1579 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1580 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1581 interconnect-names = "read", "write"; 1582 }; 1583 1584 pcie@14160000 { 1585 compatible = "nvidia,tegra194-pcie"; 1586 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1587 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1588 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1589 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1590 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1591 reg-names = "appl", "config", "atu_dma", "dbi"; 1592 1593 status = "disabled"; 1594 1595 #address-cells = <3>; 1596 #size-cells = <2>; 1597 device_type = "pci"; 1598 num-lanes = <4>; 1599 num-viewport = <8>; 1600 linux,pci-domain = <4>; 1601 1602 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1603 clock-names = "core"; 1604 1605 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1606 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1607 reset-names = "apb", "core"; 1608 1609 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1610 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1611 interrupt-names = "intr", "msi"; 1612 1613 #interrupt-cells = <1>; 1614 interrupt-map-mask = <0 0 0 0>; 1615 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1616 1617 nvidia,bpmp = <&bpmp 4>; 1618 1619 nvidia,aspm-cmrt-us = <60>; 1620 nvidia,aspm-pwr-on-t-us = <20>; 1621 nvidia,aspm-l0s-entrance-latency-us = <3>; 1622 1623 bus-range = <0x0 0xff>; 1624 1625 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1626 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1627 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1628 1629 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1630 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1631 interconnect-names = "read", "write"; 1632 }; 1633 1634 pcie@14180000 { 1635 compatible = "nvidia,tegra194-pcie"; 1636 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1637 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1638 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1639 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1640 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1641 reg-names = "appl", "config", "atu_dma", "dbi"; 1642 1643 status = "disabled"; 1644 1645 #address-cells = <3>; 1646 #size-cells = <2>; 1647 device_type = "pci"; 1648 num-lanes = <8>; 1649 num-viewport = <8>; 1650 linux,pci-domain = <0>; 1651 1652 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1653 clock-names = "core"; 1654 1655 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1656 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1657 reset-names = "apb", "core"; 1658 1659 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1660 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1661 interrupt-names = "intr", "msi"; 1662 1663 #interrupt-cells = <1>; 1664 interrupt-map-mask = <0 0 0 0>; 1665 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1666 1667 nvidia,bpmp = <&bpmp 0>; 1668 1669 nvidia,aspm-cmrt-us = <60>; 1670 nvidia,aspm-pwr-on-t-us = <20>; 1671 nvidia,aspm-l0s-entrance-latency-us = <3>; 1672 1673 bus-range = <0x0 0xff>; 1674 1675 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1676 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1677 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1678 1679 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1680 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1681 interconnect-names = "read", "write"; 1682 }; 1683 1684 pcie@141a0000 { 1685 compatible = "nvidia,tegra194-pcie"; 1686 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1687 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1688 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1689 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1690 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1691 reg-names = "appl", "config", "atu_dma", "dbi"; 1692 1693 status = "disabled"; 1694 1695 #address-cells = <3>; 1696 #size-cells = <2>; 1697 device_type = "pci"; 1698 num-lanes = <8>; 1699 num-viewport = <8>; 1700 linux,pci-domain = <5>; 1701 1702 pinctrl-names = "default"; 1703 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1704 1705 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1706 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1707 clock-names = "core", "core_m"; 1708 1709 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1710 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1711 reset-names = "apb", "core"; 1712 1713 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1714 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1715 interrupt-names = "intr", "msi"; 1716 1717 nvidia,bpmp = <&bpmp 5>; 1718 1719 #interrupt-cells = <1>; 1720 interrupt-map-mask = <0 0 0 0>; 1721 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1722 1723 nvidia,aspm-cmrt-us = <60>; 1724 nvidia,aspm-pwr-on-t-us = <20>; 1725 nvidia,aspm-l0s-entrance-latency-us = <3>; 1726 1727 bus-range = <0x0 0xff>; 1728 1729 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1730 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1731 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1732 1733 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1734 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1735 interconnect-names = "read", "write"; 1736 }; 1737 1738 pcie_ep@14160000 { 1739 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1740 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1741 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1742 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1743 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1744 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1745 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1746 1747 status = "disabled"; 1748 1749 num-lanes = <4>; 1750 num-ib-windows = <2>; 1751 num-ob-windows = <8>; 1752 1753 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1754 clock-names = "core"; 1755 1756 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1757 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1758 reset-names = "apb", "core"; 1759 1760 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1761 interrupt-names = "intr"; 1762 1763 nvidia,bpmp = <&bpmp 4>; 1764 1765 nvidia,aspm-cmrt-us = <60>; 1766 nvidia,aspm-pwr-on-t-us = <20>; 1767 nvidia,aspm-l0s-entrance-latency-us = <3>; 1768 }; 1769 1770 pcie_ep@14180000 { 1771 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1772 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1773 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1774 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1775 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1776 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1777 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1778 1779 status = "disabled"; 1780 1781 num-lanes = <8>; 1782 num-ib-windows = <2>; 1783 num-ob-windows = <8>; 1784 1785 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1786 clock-names = "core"; 1787 1788 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1789 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1790 reset-names = "apb", "core"; 1791 1792 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1793 interrupt-names = "intr"; 1794 1795 nvidia,bpmp = <&bpmp 0>; 1796 1797 nvidia,aspm-cmrt-us = <60>; 1798 nvidia,aspm-pwr-on-t-us = <20>; 1799 nvidia,aspm-l0s-entrance-latency-us = <3>; 1800 }; 1801 1802 pcie_ep@141a0000 { 1803 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1804 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1805 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1806 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1807 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1808 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1809 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1810 1811 status = "disabled"; 1812 1813 num-lanes = <8>; 1814 num-ib-windows = <2>; 1815 num-ob-windows = <8>; 1816 1817 pinctrl-names = "default"; 1818 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 1819 1820 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 1821 clock-names = "core"; 1822 1823 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1824 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1825 reset-names = "apb", "core"; 1826 1827 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1828 interrupt-names = "intr"; 1829 1830 nvidia,bpmp = <&bpmp 5>; 1831 1832 nvidia,aspm-cmrt-us = <60>; 1833 nvidia,aspm-pwr-on-t-us = <20>; 1834 nvidia,aspm-l0s-entrance-latency-us = <3>; 1835 }; 1836 1837 sram@40000000 { 1838 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 1839 reg = <0x0 0x40000000 0x0 0x50000>; 1840 #address-cells = <1>; 1841 #size-cells = <1>; 1842 ranges = <0x0 0x0 0x40000000 0x50000>; 1843 1844 cpu_bpmp_tx: sram@4e000 { 1845 reg = <0x4e000 0x1000>; 1846 label = "cpu-bpmp-tx"; 1847 pool; 1848 }; 1849 1850 cpu_bpmp_rx: sram@4f000 { 1851 reg = <0x4f000 0x1000>; 1852 label = "cpu-bpmp-rx"; 1853 pool; 1854 }; 1855 }; 1856 1857 bpmp: bpmp { 1858 compatible = "nvidia,tegra186-bpmp"; 1859 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1860 TEGRA_HSP_DB_MASTER_BPMP>; 1861 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1862 #clock-cells = <1>; 1863 #reset-cells = <1>; 1864 #power-domain-cells = <1>; 1865 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 1866 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 1867 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 1868 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 1869 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1870 1871 bpmp_i2c: i2c { 1872 compatible = "nvidia,tegra186-bpmp-i2c"; 1873 nvidia,bpmp-bus-id = <5>; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 }; 1877 1878 bpmp_thermal: thermal { 1879 compatible = "nvidia,tegra186-bpmp-thermal"; 1880 #thermal-sensor-cells = <1>; 1881 }; 1882 }; 1883 1884 cpus { 1885 compatible = "nvidia,tegra194-ccplex"; 1886 nvidia,bpmp = <&bpmp>; 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 1890 cpu0_0: cpu@0 { 1891 compatible = "nvidia,tegra194-carmel"; 1892 device_type = "cpu"; 1893 reg = <0x000>; 1894 enable-method = "psci"; 1895 i-cache-size = <131072>; 1896 i-cache-line-size = <64>; 1897 i-cache-sets = <512>; 1898 d-cache-size = <65536>; 1899 d-cache-line-size = <64>; 1900 d-cache-sets = <256>; 1901 next-level-cache = <&l2c_0>; 1902 }; 1903 1904 cpu0_1: cpu@1 { 1905 compatible = "nvidia,tegra194-carmel"; 1906 device_type = "cpu"; 1907 reg = <0x001>; 1908 enable-method = "psci"; 1909 i-cache-size = <131072>; 1910 i-cache-line-size = <64>; 1911 i-cache-sets = <512>; 1912 d-cache-size = <65536>; 1913 d-cache-line-size = <64>; 1914 d-cache-sets = <256>; 1915 next-level-cache = <&l2c_0>; 1916 }; 1917 1918 cpu1_0: cpu@100 { 1919 compatible = "nvidia,tegra194-carmel"; 1920 device_type = "cpu"; 1921 reg = <0x100>; 1922 enable-method = "psci"; 1923 i-cache-size = <131072>; 1924 i-cache-line-size = <64>; 1925 i-cache-sets = <512>; 1926 d-cache-size = <65536>; 1927 d-cache-line-size = <64>; 1928 d-cache-sets = <256>; 1929 next-level-cache = <&l2c_1>; 1930 }; 1931 1932 cpu1_1: cpu@101 { 1933 compatible = "nvidia,tegra194-carmel"; 1934 device_type = "cpu"; 1935 reg = <0x101>; 1936 enable-method = "psci"; 1937 i-cache-size = <131072>; 1938 i-cache-line-size = <64>; 1939 i-cache-sets = <512>; 1940 d-cache-size = <65536>; 1941 d-cache-line-size = <64>; 1942 d-cache-sets = <256>; 1943 next-level-cache = <&l2c_1>; 1944 }; 1945 1946 cpu2_0: cpu@200 { 1947 compatible = "nvidia,tegra194-carmel"; 1948 device_type = "cpu"; 1949 reg = <0x200>; 1950 enable-method = "psci"; 1951 i-cache-size = <131072>; 1952 i-cache-line-size = <64>; 1953 i-cache-sets = <512>; 1954 d-cache-size = <65536>; 1955 d-cache-line-size = <64>; 1956 d-cache-sets = <256>; 1957 next-level-cache = <&l2c_2>; 1958 }; 1959 1960 cpu2_1: cpu@201 { 1961 compatible = "nvidia,tegra194-carmel"; 1962 device_type = "cpu"; 1963 reg = <0x201>; 1964 enable-method = "psci"; 1965 i-cache-size = <131072>; 1966 i-cache-line-size = <64>; 1967 i-cache-sets = <512>; 1968 d-cache-size = <65536>; 1969 d-cache-line-size = <64>; 1970 d-cache-sets = <256>; 1971 next-level-cache = <&l2c_2>; 1972 }; 1973 1974 cpu3_0: cpu@300 { 1975 compatible = "nvidia,tegra194-carmel"; 1976 device_type = "cpu"; 1977 reg = <0x300>; 1978 enable-method = "psci"; 1979 i-cache-size = <131072>; 1980 i-cache-line-size = <64>; 1981 i-cache-sets = <512>; 1982 d-cache-size = <65536>; 1983 d-cache-line-size = <64>; 1984 d-cache-sets = <256>; 1985 next-level-cache = <&l2c_3>; 1986 }; 1987 1988 cpu3_1: cpu@301 { 1989 compatible = "nvidia,tegra194-carmel"; 1990 device_type = "cpu"; 1991 reg = <0x301>; 1992 enable-method = "psci"; 1993 i-cache-size = <131072>; 1994 i-cache-line-size = <64>; 1995 i-cache-sets = <512>; 1996 d-cache-size = <65536>; 1997 d-cache-line-size = <64>; 1998 d-cache-sets = <256>; 1999 next-level-cache = <&l2c_3>; 2000 }; 2001 2002 cpu-map { 2003 cluster0 { 2004 core0 { 2005 cpu = <&cpu0_0>; 2006 }; 2007 2008 core1 { 2009 cpu = <&cpu0_1>; 2010 }; 2011 }; 2012 2013 cluster1 { 2014 core0 { 2015 cpu = <&cpu1_0>; 2016 }; 2017 2018 core1 { 2019 cpu = <&cpu1_1>; 2020 }; 2021 }; 2022 2023 cluster2 { 2024 core0 { 2025 cpu = <&cpu2_0>; 2026 }; 2027 2028 core1 { 2029 cpu = <&cpu2_1>; 2030 }; 2031 }; 2032 2033 cluster3 { 2034 core0 { 2035 cpu = <&cpu3_0>; 2036 }; 2037 2038 core1 { 2039 cpu = <&cpu3_1>; 2040 }; 2041 }; 2042 }; 2043 2044 l2c_0: l2-cache0 { 2045 cache-size = <2097152>; 2046 cache-line-size = <64>; 2047 cache-sets = <2048>; 2048 next-level-cache = <&l3c>; 2049 }; 2050 2051 l2c_1: l2-cache1 { 2052 cache-size = <2097152>; 2053 cache-line-size = <64>; 2054 cache-sets = <2048>; 2055 next-level-cache = <&l3c>; 2056 }; 2057 2058 l2c_2: l2-cache2 { 2059 cache-size = <2097152>; 2060 cache-line-size = <64>; 2061 cache-sets = <2048>; 2062 next-level-cache = <&l3c>; 2063 }; 2064 2065 l2c_3: l2-cache3 { 2066 cache-size = <2097152>; 2067 cache-line-size = <64>; 2068 cache-sets = <2048>; 2069 next-level-cache = <&l3c>; 2070 }; 2071 2072 l3c: l3-cache { 2073 cache-size = <4194304>; 2074 cache-line-size = <64>; 2075 cache-sets = <4096>; 2076 }; 2077 }; 2078 2079 psci { 2080 compatible = "arm,psci-1.0"; 2081 status = "okay"; 2082 method = "smc"; 2083 }; 2084 2085 tcu: tcu { 2086 compatible = "nvidia,tegra194-tcu"; 2087 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2088 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2089 mbox-names = "rx", "tx"; 2090 }; 2091 2092 thermal-zones { 2093 cpu { 2094 thermal-sensors = <&{/bpmp/thermal} 2095 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2096 status = "disabled"; 2097 }; 2098 2099 gpu { 2100 thermal-sensors = <&{/bpmp/thermal} 2101 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2102 status = "disabled"; 2103 }; 2104 2105 aux { 2106 thermal-sensors = <&{/bpmp/thermal} 2107 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2108 status = "disabled"; 2109 }; 2110 2111 pllx { 2112 thermal-sensors = <&{/bpmp/thermal} 2113 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2114 status = "disabled"; 2115 }; 2116 2117 ao { 2118 thermal-sensors = <&{/bpmp/thermal} 2119 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2120 status = "disabled"; 2121 }; 2122 2123 tj { 2124 thermal-sensors = <&{/bpmp/thermal} 2125 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2126 status = "disabled"; 2127 }; 2128 }; 2129 2130 timer { 2131 compatible = "arm,armv8-timer"; 2132 interrupts = <GIC_PPI 13 2133 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2134 <GIC_PPI 14 2135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2136 <GIC_PPI 11 2137 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2138 <GIC_PPI 10 2139 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2140 interrupt-parent = <&gic>; 2141 always-on; 2142 }; 2143}; 2144