1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 cbb@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64 interconnect-names = "dma-mem", "write"; 65 status = "disabled"; 66 67 snps,write-requests = <1>; 68 snps,read-requests = <3>; 69 snps,burst-map = <0x7>; 70 snps,txpbl = <16>; 71 snps,rxpbl = <8>; 72 }; 73 74 aconnect@2900000 { 75 compatible = "nvidia,tegra194-aconnect", 76 "nvidia,tegra210-aconnect"; 77 clocks = <&bpmp TEGRA194_CLK_APE>, 78 <&bpmp TEGRA194_CLK_APB2APE>; 79 clock-names = "ape", "apb2ape"; 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x02900000 0x02900000 0x200000>; 84 status = "disabled"; 85 86 dma-controller@2930000 { 87 compatible = "nvidia,tegra194-adma", 88 "nvidia,tegra186-adma"; 89 reg = <0x02930000 0x20000>; 90 interrupt-parent = <&agic>; 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 123 #dma-cells = <1>; 124 clocks = <&bpmp TEGRA194_CLK_AHUB>; 125 clock-names = "d_audio"; 126 status = "disabled"; 127 }; 128 129 agic: interrupt-controller@2a40000 { 130 compatible = "nvidia,tegra194-agic", 131 "nvidia,tegra210-agic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x02a41000 0x1000>, 135 <0x02a42000 0x2000>; 136 interrupts = <GIC_SPI 145 137 (GIC_CPU_MASK_SIMPLE(4) | 138 IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA194_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 }; 144 145 pinmux: pinmux@2430000 { 146 compatible = "nvidia,tegra194-pinmux"; 147 reg = <0x2430000 0x17000>, 148 <0xc300000 0x4000>; 149 150 status = "okay"; 151 152 pex_rst_c5_out_state: pex_rst_c5_out { 153 pex_rst { 154 nvidia,pins = "pex_l5_rst_n_pgg1"; 155 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 156 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 157 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 158 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 159 nvidia,tristate = <TEGRA_PIN_DISABLE>; 160 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 161 }; 162 }; 163 164 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 165 clkreq { 166 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 167 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 168 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 169 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 170 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 171 nvidia,tristate = <TEGRA_PIN_DISABLE>; 172 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 173 }; 174 }; 175 }; 176 177 mc: memory-controller@2c00000 { 178 compatible = "nvidia,tegra194-mc"; 179 reg = <0x02c00000 0x100000>, 180 <0x02b80000 0x040000>, 181 <0x01700000 0x100000>; 182 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 183 #interconnect-cells = <1>; 184 status = "disabled"; 185 186 #address-cells = <2>; 187 #size-cells = <2>; 188 189 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 190 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 191 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 192 193 /* 194 * Bit 39 of addresses passing through the memory 195 * controller selects the XBAR format used when memory 196 * is accessed. This is used to transparently access 197 * memory in the XBAR format used by the discrete GPU 198 * (bit 39 set) or Tegra (bit 39 clear). 199 * 200 * As a consequence, the operating system must ensure 201 * that bit 39 is never used implicitly, for example 202 * via an I/O virtual address mapping of an IOMMU. If 203 * devices require access to the XBAR switch, their 204 * drivers must set this bit explicitly. 205 * 206 * Limit the DMA range for memory clients to [38:0]. 207 */ 208 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 209 210 emc: external-memory-controller@2c60000 { 211 compatible = "nvidia,tegra194-emc"; 212 reg = <0x0 0x02c60000 0x0 0x90000>, 213 <0x0 0x01780000 0x0 0x80000>; 214 clocks = <&bpmp TEGRA194_CLK_EMC>; 215 clock-names = "emc"; 216 217 #interconnect-cells = <0>; 218 219 nvidia,bpmp = <&bpmp>; 220 }; 221 }; 222 223 uarta: serial@3100000 { 224 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 225 reg = <0x03100000 0x40>; 226 reg-shift = <2>; 227 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&bpmp TEGRA194_CLK_UARTA>; 229 clock-names = "serial"; 230 resets = <&bpmp TEGRA194_RESET_UARTA>; 231 reset-names = "serial"; 232 status = "disabled"; 233 }; 234 235 uartb: serial@3110000 { 236 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 237 reg = <0x03110000 0x40>; 238 reg-shift = <2>; 239 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&bpmp TEGRA194_CLK_UARTB>; 241 clock-names = "serial"; 242 resets = <&bpmp TEGRA194_RESET_UARTB>; 243 reset-names = "serial"; 244 status = "disabled"; 245 }; 246 247 uartd: serial@3130000 { 248 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 249 reg = <0x03130000 0x40>; 250 reg-shift = <2>; 251 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&bpmp TEGRA194_CLK_UARTD>; 253 clock-names = "serial"; 254 resets = <&bpmp TEGRA194_RESET_UARTD>; 255 reset-names = "serial"; 256 status = "disabled"; 257 }; 258 259 uarte: serial@3140000 { 260 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 261 reg = <0x03140000 0x40>; 262 reg-shift = <2>; 263 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&bpmp TEGRA194_CLK_UARTE>; 265 clock-names = "serial"; 266 resets = <&bpmp TEGRA194_RESET_UARTE>; 267 reset-names = "serial"; 268 status = "disabled"; 269 }; 270 271 uartf: serial@3150000 { 272 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 273 reg = <0x03150000 0x40>; 274 reg-shift = <2>; 275 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&bpmp TEGRA194_CLK_UARTF>; 277 clock-names = "serial"; 278 resets = <&bpmp TEGRA194_RESET_UARTF>; 279 reset-names = "serial"; 280 status = "disabled"; 281 }; 282 283 gen1_i2c: i2c@3160000 { 284 compatible = "nvidia,tegra194-i2c"; 285 reg = <0x03160000 0x10000>; 286 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 clocks = <&bpmp TEGRA194_CLK_I2C1>; 290 clock-names = "div-clk"; 291 resets = <&bpmp TEGRA194_RESET_I2C1>; 292 reset-names = "i2c"; 293 status = "disabled"; 294 }; 295 296 uarth: serial@3170000 { 297 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 298 reg = <0x03170000 0x40>; 299 reg-shift = <2>; 300 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&bpmp TEGRA194_CLK_UARTH>; 302 clock-names = "serial"; 303 resets = <&bpmp TEGRA194_RESET_UARTH>; 304 reset-names = "serial"; 305 status = "disabled"; 306 }; 307 308 cam_i2c: i2c@3180000 { 309 compatible = "nvidia,tegra194-i2c"; 310 reg = <0x03180000 0x10000>; 311 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 clocks = <&bpmp TEGRA194_CLK_I2C3>; 315 clock-names = "div-clk"; 316 resets = <&bpmp TEGRA194_RESET_I2C3>; 317 reset-names = "i2c"; 318 status = "disabled"; 319 }; 320 321 /* shares pads with dpaux1 */ 322 dp_aux_ch1_i2c: i2c@3190000 { 323 compatible = "nvidia,tegra194-i2c"; 324 reg = <0x03190000 0x10000>; 325 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clocks = <&bpmp TEGRA194_CLK_I2C4>; 329 clock-names = "div-clk"; 330 resets = <&bpmp TEGRA194_RESET_I2C4>; 331 reset-names = "i2c"; 332 status = "disabled"; 333 }; 334 335 /* shares pads with dpaux0 */ 336 dp_aux_ch0_i2c: i2c@31b0000 { 337 compatible = "nvidia,tegra194-i2c"; 338 reg = <0x031b0000 0x10000>; 339 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 clocks = <&bpmp TEGRA194_CLK_I2C6>; 343 clock-names = "div-clk"; 344 resets = <&bpmp TEGRA194_RESET_I2C6>; 345 reset-names = "i2c"; 346 status = "disabled"; 347 }; 348 349 gen7_i2c: i2c@31c0000 { 350 compatible = "nvidia,tegra194-i2c"; 351 reg = <0x031c0000 0x10000>; 352 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 clocks = <&bpmp TEGRA194_CLK_I2C7>; 356 clock-names = "div-clk"; 357 resets = <&bpmp TEGRA194_RESET_I2C7>; 358 reset-names = "i2c"; 359 status = "disabled"; 360 }; 361 362 gen9_i2c: i2c@31e0000 { 363 compatible = "nvidia,tegra194-i2c"; 364 reg = <0x031e0000 0x10000>; 365 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clocks = <&bpmp TEGRA194_CLK_I2C9>; 369 clock-names = "div-clk"; 370 resets = <&bpmp TEGRA194_RESET_I2C9>; 371 reset-names = "i2c"; 372 status = "disabled"; 373 }; 374 375 pwm1: pwm@3280000 { 376 compatible = "nvidia,tegra194-pwm", 377 "nvidia,tegra186-pwm"; 378 reg = <0x3280000 0x10000>; 379 clocks = <&bpmp TEGRA194_CLK_PWM1>; 380 clock-names = "pwm"; 381 resets = <&bpmp TEGRA194_RESET_PWM1>; 382 reset-names = "pwm"; 383 status = "disabled"; 384 #pwm-cells = <2>; 385 }; 386 387 pwm2: pwm@3290000 { 388 compatible = "nvidia,tegra194-pwm", 389 "nvidia,tegra186-pwm"; 390 reg = <0x3290000 0x10000>; 391 clocks = <&bpmp TEGRA194_CLK_PWM2>; 392 clock-names = "pwm"; 393 resets = <&bpmp TEGRA194_RESET_PWM2>; 394 reset-names = "pwm"; 395 status = "disabled"; 396 #pwm-cells = <2>; 397 }; 398 399 pwm3: pwm@32a0000 { 400 compatible = "nvidia,tegra194-pwm", 401 "nvidia,tegra186-pwm"; 402 reg = <0x32a0000 0x10000>; 403 clocks = <&bpmp TEGRA194_CLK_PWM3>; 404 clock-names = "pwm"; 405 resets = <&bpmp TEGRA194_RESET_PWM3>; 406 reset-names = "pwm"; 407 status = "disabled"; 408 #pwm-cells = <2>; 409 }; 410 411 pwm5: pwm@32c0000 { 412 compatible = "nvidia,tegra194-pwm", 413 "nvidia,tegra186-pwm"; 414 reg = <0x32c0000 0x10000>; 415 clocks = <&bpmp TEGRA194_CLK_PWM5>; 416 clock-names = "pwm"; 417 resets = <&bpmp TEGRA194_RESET_PWM5>; 418 reset-names = "pwm"; 419 status = "disabled"; 420 #pwm-cells = <2>; 421 }; 422 423 pwm6: pwm@32d0000 { 424 compatible = "nvidia,tegra194-pwm", 425 "nvidia,tegra186-pwm"; 426 reg = <0x32d0000 0x10000>; 427 clocks = <&bpmp TEGRA194_CLK_PWM6>; 428 clock-names = "pwm"; 429 resets = <&bpmp TEGRA194_RESET_PWM6>; 430 reset-names = "pwm"; 431 status = "disabled"; 432 #pwm-cells = <2>; 433 }; 434 435 pwm7: pwm@32e0000 { 436 compatible = "nvidia,tegra194-pwm", 437 "nvidia,tegra186-pwm"; 438 reg = <0x32e0000 0x10000>; 439 clocks = <&bpmp TEGRA194_CLK_PWM7>; 440 clock-names = "pwm"; 441 resets = <&bpmp TEGRA194_RESET_PWM7>; 442 reset-names = "pwm"; 443 status = "disabled"; 444 #pwm-cells = <2>; 445 }; 446 447 pwm8: pwm@32f0000 { 448 compatible = "nvidia,tegra194-pwm", 449 "nvidia,tegra186-pwm"; 450 reg = <0x32f0000 0x10000>; 451 clocks = <&bpmp TEGRA194_CLK_PWM8>; 452 clock-names = "pwm"; 453 resets = <&bpmp TEGRA194_RESET_PWM8>; 454 reset-names = "pwm"; 455 status = "disabled"; 456 #pwm-cells = <2>; 457 }; 458 459 sdmmc1: mmc@3400000 { 460 compatible = "nvidia,tegra194-sdhci"; 461 reg = <0x03400000 0x10000>; 462 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 464 clock-names = "sdhci"; 465 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 466 reset-names = "sdhci"; 467 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 468 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 469 interconnect-names = "dma-mem", "write"; 470 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 471 <0x07>; 472 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 473 <0x07>; 474 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 475 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 476 <0x07>; 477 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 478 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 479 nvidia,default-tap = <0x9>; 480 nvidia,default-trim = <0x5>; 481 status = "disabled"; 482 }; 483 484 sdmmc3: mmc@3440000 { 485 compatible = "nvidia,tegra194-sdhci"; 486 reg = <0x03440000 0x10000>; 487 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 489 clock-names = "sdhci"; 490 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 491 reset-names = "sdhci"; 492 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 493 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 494 interconnect-names = "dma-mem", "write"; 495 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 496 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 497 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 498 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 499 <0x07>; 500 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 501 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 502 <0x07>; 503 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 504 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 505 nvidia,default-tap = <0x9>; 506 nvidia,default-trim = <0x5>; 507 status = "disabled"; 508 }; 509 510 sdmmc4: mmc@3460000 { 511 compatible = "nvidia,tegra194-sdhci"; 512 reg = <0x03460000 0x10000>; 513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 515 clock-names = "sdhci"; 516 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 517 <&bpmp TEGRA194_CLK_PLLC4>; 518 assigned-clock-parents = 519 <&bpmp TEGRA194_CLK_PLLC4>; 520 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 521 reset-names = "sdhci"; 522 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 523 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 524 interconnect-names = "dma-mem", "write"; 525 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 526 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 527 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 528 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 529 <0x0a>; 530 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 531 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 532 <0x0a>; 533 nvidia,default-tap = <0x8>; 534 nvidia,default-trim = <0x14>; 535 nvidia,dqs-trim = <40>; 536 supports-cqe; 537 status = "disabled"; 538 }; 539 540 hda@3510000 { 541 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 542 reg = <0x3510000 0x10000>; 543 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&bpmp TEGRA194_CLK_HDA>, 545 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 546 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 547 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 548 resets = <&bpmp TEGRA194_RESET_HDA>, 549 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 550 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 551 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 552 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 553 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 554 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 555 interconnect-names = "dma-mem", "write"; 556 status = "disabled"; 557 }; 558 559 xusb_padctl: padctl@3520000 { 560 compatible = "nvidia,tegra194-xusb-padctl"; 561 reg = <0x03520000 0x1000>, 562 <0x03540000 0x1000>; 563 reg-names = "padctl", "ao"; 564 565 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 566 reset-names = "padctl"; 567 568 status = "disabled"; 569 570 pads { 571 usb2 { 572 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 573 clock-names = "trk"; 574 575 lanes { 576 usb2-0 { 577 nvidia,function = "xusb"; 578 status = "disabled"; 579 #phy-cells = <0>; 580 }; 581 582 usb2-1 { 583 nvidia,function = "xusb"; 584 status = "disabled"; 585 #phy-cells = <0>; 586 }; 587 588 usb2-2 { 589 nvidia,function = "xusb"; 590 status = "disabled"; 591 #phy-cells = <0>; 592 }; 593 594 usb2-3 { 595 nvidia,function = "xusb"; 596 status = "disabled"; 597 #phy-cells = <0>; 598 }; 599 }; 600 }; 601 602 usb3 { 603 lanes { 604 usb3-0 { 605 nvidia,function = "xusb"; 606 status = "disabled"; 607 #phy-cells = <0>; 608 }; 609 610 usb3-1 { 611 nvidia,function = "xusb"; 612 status = "disabled"; 613 #phy-cells = <0>; 614 }; 615 616 usb3-2 { 617 nvidia,function = "xusb"; 618 status = "disabled"; 619 #phy-cells = <0>; 620 }; 621 622 usb3-3 { 623 nvidia,function = "xusb"; 624 status = "disabled"; 625 #phy-cells = <0>; 626 }; 627 }; 628 }; 629 }; 630 631 ports { 632 usb2-0 { 633 status = "disabled"; 634 }; 635 636 usb2-1 { 637 status = "disabled"; 638 }; 639 640 usb2-2 { 641 status = "disabled"; 642 }; 643 644 usb2-3 { 645 status = "disabled"; 646 }; 647 648 usb3-0 { 649 status = "disabled"; 650 }; 651 652 usb3-1 { 653 status = "disabled"; 654 }; 655 656 usb3-2 { 657 status = "disabled"; 658 }; 659 660 usb3-3 { 661 status = "disabled"; 662 }; 663 }; 664 }; 665 666 usb@3550000 { 667 compatible = "nvidia,tegra194-xudc"; 668 reg = <0x03550000 0x8000>, 669 <0x03558000 0x1000>; 670 reg-names = "base", "fpci"; 671 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 673 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 674 <&bpmp TEGRA194_CLK_XUSB_SS>, 675 <&bpmp TEGRA194_CLK_XUSB_FS>; 676 clock-names = "dev", "ss", "ss_src", "fs_src"; 677 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 678 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 679 power-domain-names = "dev", "ss"; 680 nvidia,xusb-padctl = <&xusb_padctl>; 681 status = "disabled"; 682 }; 683 684 usb@3610000 { 685 compatible = "nvidia,tegra194-xusb"; 686 reg = <0x03610000 0x40000>, 687 <0x03600000 0x10000>; 688 reg-names = "hcd", "fpci"; 689 690 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 692 693 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 694 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 695 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 696 <&bpmp TEGRA194_CLK_XUSB_SS>, 697 <&bpmp TEGRA194_CLK_CLK_M>, 698 <&bpmp TEGRA194_CLK_XUSB_FS>, 699 <&bpmp TEGRA194_CLK_UTMIPLL>, 700 <&bpmp TEGRA194_CLK_CLK_M>, 701 <&bpmp TEGRA194_CLK_PLLE>; 702 clock-names = "xusb_host", "xusb_falcon_src", 703 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 704 "xusb_fs_src", "pll_u_480m", "clk_m", 705 "pll_e"; 706 707 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 708 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 709 power-domain-names = "xusb_host", "xusb_ss"; 710 711 nvidia,xusb-padctl = <&xusb_padctl>; 712 status = "disabled"; 713 }; 714 715 fuse@3820000 { 716 compatible = "nvidia,tegra194-efuse"; 717 reg = <0x03820000 0x10000>; 718 clocks = <&bpmp TEGRA194_CLK_FUSE>; 719 clock-names = "fuse"; 720 }; 721 722 gic: interrupt-controller@3881000 { 723 compatible = "arm,gic-400"; 724 #interrupt-cells = <3>; 725 interrupt-controller; 726 reg = <0x03881000 0x1000>, 727 <0x03882000 0x2000>, 728 <0x03884000 0x2000>, 729 <0x03886000 0x2000>; 730 interrupts = <GIC_PPI 9 731 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 732 interrupt-parent = <&gic>; 733 }; 734 735 cec@3960000 { 736 compatible = "nvidia,tegra194-cec"; 737 reg = <0x03960000 0x10000>; 738 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&bpmp TEGRA194_CLK_CEC>; 740 clock-names = "cec"; 741 status = "disabled"; 742 }; 743 744 hsp_top0: hsp@3c00000 { 745 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 746 reg = <0x03c00000 0xa0000>; 747 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 756 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 757 "shared3", "shared4", "shared5", "shared6", 758 "shared7"; 759 #mbox-cells = <2>; 760 }; 761 762 p2u_hsio_0: phy@3e10000 { 763 compatible = "nvidia,tegra194-p2u"; 764 reg = <0x03e10000 0x10000>; 765 reg-names = "ctl"; 766 767 #phy-cells = <0>; 768 }; 769 770 p2u_hsio_1: phy@3e20000 { 771 compatible = "nvidia,tegra194-p2u"; 772 reg = <0x03e20000 0x10000>; 773 reg-names = "ctl"; 774 775 #phy-cells = <0>; 776 }; 777 778 p2u_hsio_2: phy@3e30000 { 779 compatible = "nvidia,tegra194-p2u"; 780 reg = <0x03e30000 0x10000>; 781 reg-names = "ctl"; 782 783 #phy-cells = <0>; 784 }; 785 786 p2u_hsio_3: phy@3e40000 { 787 compatible = "nvidia,tegra194-p2u"; 788 reg = <0x03e40000 0x10000>; 789 reg-names = "ctl"; 790 791 #phy-cells = <0>; 792 }; 793 794 p2u_hsio_4: phy@3e50000 { 795 compatible = "nvidia,tegra194-p2u"; 796 reg = <0x03e50000 0x10000>; 797 reg-names = "ctl"; 798 799 #phy-cells = <0>; 800 }; 801 802 p2u_hsio_5: phy@3e60000 { 803 compatible = "nvidia,tegra194-p2u"; 804 reg = <0x03e60000 0x10000>; 805 reg-names = "ctl"; 806 807 #phy-cells = <0>; 808 }; 809 810 p2u_hsio_6: phy@3e70000 { 811 compatible = "nvidia,tegra194-p2u"; 812 reg = <0x03e70000 0x10000>; 813 reg-names = "ctl"; 814 815 #phy-cells = <0>; 816 }; 817 818 p2u_hsio_7: phy@3e80000 { 819 compatible = "nvidia,tegra194-p2u"; 820 reg = <0x03e80000 0x10000>; 821 reg-names = "ctl"; 822 823 #phy-cells = <0>; 824 }; 825 826 p2u_hsio_8: phy@3e90000 { 827 compatible = "nvidia,tegra194-p2u"; 828 reg = <0x03e90000 0x10000>; 829 reg-names = "ctl"; 830 831 #phy-cells = <0>; 832 }; 833 834 p2u_hsio_9: phy@3ea0000 { 835 compatible = "nvidia,tegra194-p2u"; 836 reg = <0x03ea0000 0x10000>; 837 reg-names = "ctl"; 838 839 #phy-cells = <0>; 840 }; 841 842 p2u_nvhs_0: phy@3eb0000 { 843 compatible = "nvidia,tegra194-p2u"; 844 reg = <0x03eb0000 0x10000>; 845 reg-names = "ctl"; 846 847 #phy-cells = <0>; 848 }; 849 850 p2u_nvhs_1: phy@3ec0000 { 851 compatible = "nvidia,tegra194-p2u"; 852 reg = <0x03ec0000 0x10000>; 853 reg-names = "ctl"; 854 855 #phy-cells = <0>; 856 }; 857 858 p2u_nvhs_2: phy@3ed0000 { 859 compatible = "nvidia,tegra194-p2u"; 860 reg = <0x03ed0000 0x10000>; 861 reg-names = "ctl"; 862 863 #phy-cells = <0>; 864 }; 865 866 p2u_nvhs_3: phy@3ee0000 { 867 compatible = "nvidia,tegra194-p2u"; 868 reg = <0x03ee0000 0x10000>; 869 reg-names = "ctl"; 870 871 #phy-cells = <0>; 872 }; 873 874 p2u_nvhs_4: phy@3ef0000 { 875 compatible = "nvidia,tegra194-p2u"; 876 reg = <0x03ef0000 0x10000>; 877 reg-names = "ctl"; 878 879 #phy-cells = <0>; 880 }; 881 882 p2u_nvhs_5: phy@3f00000 { 883 compatible = "nvidia,tegra194-p2u"; 884 reg = <0x03f00000 0x10000>; 885 reg-names = "ctl"; 886 887 #phy-cells = <0>; 888 }; 889 890 p2u_nvhs_6: phy@3f10000 { 891 compatible = "nvidia,tegra194-p2u"; 892 reg = <0x03f10000 0x10000>; 893 reg-names = "ctl"; 894 895 #phy-cells = <0>; 896 }; 897 898 p2u_nvhs_7: phy@3f20000 { 899 compatible = "nvidia,tegra194-p2u"; 900 reg = <0x03f20000 0x10000>; 901 reg-names = "ctl"; 902 903 #phy-cells = <0>; 904 }; 905 906 p2u_hsio_10: phy@3f30000 { 907 compatible = "nvidia,tegra194-p2u"; 908 reg = <0x03f30000 0x10000>; 909 reg-names = "ctl"; 910 911 #phy-cells = <0>; 912 }; 913 914 p2u_hsio_11: phy@3f40000 { 915 compatible = "nvidia,tegra194-p2u"; 916 reg = <0x03f40000 0x10000>; 917 reg-names = "ctl"; 918 919 #phy-cells = <0>; 920 }; 921 922 hsp_aon: hsp@c150000 { 923 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 924 reg = <0x0c150000 0xa0000>; 925 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 929 /* 930 * Shared interrupt 0 is routed only to AON/SPE, so 931 * we only have 4 shared interrupts for the CCPLEX. 932 */ 933 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 934 #mbox-cells = <2>; 935 }; 936 937 gen2_i2c: i2c@c240000 { 938 compatible = "nvidia,tegra194-i2c"; 939 reg = <0x0c240000 0x10000>; 940 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 clocks = <&bpmp TEGRA194_CLK_I2C2>; 944 clock-names = "div-clk"; 945 resets = <&bpmp TEGRA194_RESET_I2C2>; 946 reset-names = "i2c"; 947 status = "disabled"; 948 }; 949 950 gen8_i2c: i2c@c250000 { 951 compatible = "nvidia,tegra194-i2c"; 952 reg = <0x0c250000 0x10000>; 953 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 clocks = <&bpmp TEGRA194_CLK_I2C8>; 957 clock-names = "div-clk"; 958 resets = <&bpmp TEGRA194_RESET_I2C8>; 959 reset-names = "i2c"; 960 status = "disabled"; 961 }; 962 963 uartc: serial@c280000 { 964 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 965 reg = <0x0c280000 0x40>; 966 reg-shift = <2>; 967 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&bpmp TEGRA194_CLK_UARTC>; 969 clock-names = "serial"; 970 resets = <&bpmp TEGRA194_RESET_UARTC>; 971 reset-names = "serial"; 972 status = "disabled"; 973 }; 974 975 uartg: serial@c290000 { 976 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 977 reg = <0x0c290000 0x40>; 978 reg-shift = <2>; 979 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&bpmp TEGRA194_CLK_UARTG>; 981 clock-names = "serial"; 982 resets = <&bpmp TEGRA194_RESET_UARTG>; 983 reset-names = "serial"; 984 status = "disabled"; 985 }; 986 987 rtc: rtc@c2a0000 { 988 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 989 reg = <0x0c2a0000 0x10000>; 990 interrupt-parent = <&pmc>; 991 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 993 clock-names = "rtc"; 994 status = "disabled"; 995 }; 996 997 gpio_aon: gpio@c2f0000 { 998 compatible = "nvidia,tegra194-gpio-aon"; 999 reg-names = "security", "gpio"; 1000 reg = <0xc2f0000 0x1000>, 1001 <0xc2f1000 0x1000>; 1002 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1006 gpio-controller; 1007 #gpio-cells = <2>; 1008 interrupt-controller; 1009 #interrupt-cells = <2>; 1010 }; 1011 1012 pwm4: pwm@c340000 { 1013 compatible = "nvidia,tegra194-pwm", 1014 "nvidia,tegra186-pwm"; 1015 reg = <0xc340000 0x10000>; 1016 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1017 clock-names = "pwm"; 1018 resets = <&bpmp TEGRA194_RESET_PWM4>; 1019 reset-names = "pwm"; 1020 status = "disabled"; 1021 #pwm-cells = <2>; 1022 }; 1023 1024 pmc: pmc@c360000 { 1025 compatible = "nvidia,tegra194-pmc"; 1026 reg = <0x0c360000 0x10000>, 1027 <0x0c370000 0x10000>, 1028 <0x0c380000 0x10000>, 1029 <0x0c390000 0x10000>, 1030 <0x0c3a0000 0x10000>; 1031 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1032 1033 #interrupt-cells = <2>; 1034 interrupt-controller; 1035 }; 1036 1037 host1x@13e00000 { 1038 compatible = "nvidia,tegra194-host1x"; 1039 reg = <0x13e00000 0x10000>, 1040 <0x13e10000 0x10000>; 1041 reg-names = "hypervisor", "vm"; 1042 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1044 interrupt-names = "syncpt", "host1x"; 1045 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1046 clock-names = "host1x"; 1047 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1048 reset-names = "host1x"; 1049 1050 #address-cells = <1>; 1051 #size-cells = <1>; 1052 1053 ranges = <0x15000000 0x15000000 0x01000000>; 1054 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1055 interconnect-names = "dma-mem"; 1056 1057 display-hub@15200000 { 1058 compatible = "nvidia,tegra194-display"; 1059 reg = <0x15200000 0x00040000>; 1060 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1061 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1062 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1063 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1064 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1065 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1066 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1067 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1068 "wgrp3", "wgrp4", "wgrp5"; 1069 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1070 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1071 clock-names = "disp", "hub"; 1072 status = "disabled"; 1073 1074 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1075 1076 #address-cells = <1>; 1077 #size-cells = <1>; 1078 1079 ranges = <0x15200000 0x15200000 0x40000>; 1080 1081 display@15200000 { 1082 compatible = "nvidia,tegra194-dc"; 1083 reg = <0x15200000 0x10000>; 1084 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1086 clock-names = "dc"; 1087 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1088 reset-names = "dc"; 1089 1090 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1091 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1092 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1093 interconnect-names = "dma-mem", "read-1"; 1094 1095 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1096 nvidia,head = <0>; 1097 }; 1098 1099 display@15210000 { 1100 compatible = "nvidia,tegra194-dc"; 1101 reg = <0x15210000 0x10000>; 1102 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1104 clock-names = "dc"; 1105 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1106 reset-names = "dc"; 1107 1108 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1109 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1110 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1111 interconnect-names = "dma-mem", "read-1"; 1112 1113 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1114 nvidia,head = <1>; 1115 }; 1116 1117 display@15220000 { 1118 compatible = "nvidia,tegra194-dc"; 1119 reg = <0x15220000 0x10000>; 1120 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1122 clock-names = "dc"; 1123 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1124 reset-names = "dc"; 1125 1126 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1127 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1128 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1129 interconnect-names = "dma-mem", "read-1"; 1130 1131 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1132 nvidia,head = <2>; 1133 }; 1134 1135 display@15230000 { 1136 compatible = "nvidia,tegra194-dc"; 1137 reg = <0x15230000 0x10000>; 1138 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1140 clock-names = "dc"; 1141 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1142 reset-names = "dc"; 1143 1144 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1145 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1146 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1147 interconnect-names = "dma-mem", "read-1"; 1148 1149 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1150 nvidia,head = <3>; 1151 }; 1152 }; 1153 1154 vic@15340000 { 1155 compatible = "nvidia,tegra194-vic"; 1156 reg = <0x15340000 0x00040000>; 1157 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&bpmp TEGRA194_CLK_VIC>; 1159 clock-names = "vic"; 1160 resets = <&bpmp TEGRA194_RESET_VIC>; 1161 reset-names = "vic"; 1162 1163 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1164 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1165 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1166 interconnect-names = "dma-mem", "write"; 1167 }; 1168 1169 dpaux0: dpaux@155c0000 { 1170 compatible = "nvidia,tegra194-dpaux"; 1171 reg = <0x155c0000 0x10000>; 1172 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1173 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1174 <&bpmp TEGRA194_CLK_PLLDP>; 1175 clock-names = "dpaux", "parent"; 1176 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1177 reset-names = "dpaux"; 1178 status = "disabled"; 1179 1180 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1181 1182 state_dpaux0_aux: pinmux-aux { 1183 groups = "dpaux-io"; 1184 function = "aux"; 1185 }; 1186 1187 state_dpaux0_i2c: pinmux-i2c { 1188 groups = "dpaux-io"; 1189 function = "i2c"; 1190 }; 1191 1192 state_dpaux0_off: pinmux-off { 1193 groups = "dpaux-io"; 1194 function = "off"; 1195 }; 1196 1197 i2c-bus { 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 }; 1201 }; 1202 1203 dpaux1: dpaux@155d0000 { 1204 compatible = "nvidia,tegra194-dpaux"; 1205 reg = <0x155d0000 0x10000>; 1206 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1208 <&bpmp TEGRA194_CLK_PLLDP>; 1209 clock-names = "dpaux", "parent"; 1210 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1211 reset-names = "dpaux"; 1212 status = "disabled"; 1213 1214 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1215 1216 state_dpaux1_aux: pinmux-aux { 1217 groups = "dpaux-io"; 1218 function = "aux"; 1219 }; 1220 1221 state_dpaux1_i2c: pinmux-i2c { 1222 groups = "dpaux-io"; 1223 function = "i2c"; 1224 }; 1225 1226 state_dpaux1_off: pinmux-off { 1227 groups = "dpaux-io"; 1228 function = "off"; 1229 }; 1230 1231 i2c-bus { 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 }; 1235 }; 1236 1237 dpaux2: dpaux@155e0000 { 1238 compatible = "nvidia,tegra194-dpaux"; 1239 reg = <0x155e0000 0x10000>; 1240 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1242 <&bpmp TEGRA194_CLK_PLLDP>; 1243 clock-names = "dpaux", "parent"; 1244 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1245 reset-names = "dpaux"; 1246 status = "disabled"; 1247 1248 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1249 1250 state_dpaux2_aux: pinmux-aux { 1251 groups = "dpaux-io"; 1252 function = "aux"; 1253 }; 1254 1255 state_dpaux2_i2c: pinmux-i2c { 1256 groups = "dpaux-io"; 1257 function = "i2c"; 1258 }; 1259 1260 state_dpaux2_off: pinmux-off { 1261 groups = "dpaux-io"; 1262 function = "off"; 1263 }; 1264 1265 i2c-bus { 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 }; 1269 }; 1270 1271 dpaux3: dpaux@155f0000 { 1272 compatible = "nvidia,tegra194-dpaux"; 1273 reg = <0x155f0000 0x10000>; 1274 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1276 <&bpmp TEGRA194_CLK_PLLDP>; 1277 clock-names = "dpaux", "parent"; 1278 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1279 reset-names = "dpaux"; 1280 status = "disabled"; 1281 1282 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1283 1284 state_dpaux3_aux: pinmux-aux { 1285 groups = "dpaux-io"; 1286 function = "aux"; 1287 }; 1288 1289 state_dpaux3_i2c: pinmux-i2c { 1290 groups = "dpaux-io"; 1291 function = "i2c"; 1292 }; 1293 1294 state_dpaux3_off: pinmux-off { 1295 groups = "dpaux-io"; 1296 function = "off"; 1297 }; 1298 1299 i2c-bus { 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 }; 1303 }; 1304 1305 sor0: sor@15b00000 { 1306 compatible = "nvidia,tegra194-sor"; 1307 reg = <0x15b00000 0x40000>; 1308 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1310 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1311 <&bpmp TEGRA194_CLK_PLLD>, 1312 <&bpmp TEGRA194_CLK_PLLDP>, 1313 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1314 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1315 clock-names = "sor", "out", "parent", "dp", "safe", 1316 "pad"; 1317 resets = <&bpmp TEGRA194_RESET_SOR0>; 1318 reset-names = "sor"; 1319 pinctrl-0 = <&state_dpaux0_aux>; 1320 pinctrl-1 = <&state_dpaux0_i2c>; 1321 pinctrl-2 = <&state_dpaux0_off>; 1322 pinctrl-names = "aux", "i2c", "off"; 1323 status = "disabled"; 1324 1325 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1326 nvidia,interface = <0>; 1327 }; 1328 1329 sor1: sor@15b40000 { 1330 compatible = "nvidia,tegra194-sor"; 1331 reg = <0x15b40000 0x40000>; 1332 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1333 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1334 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1335 <&bpmp TEGRA194_CLK_PLLD2>, 1336 <&bpmp TEGRA194_CLK_PLLDP>, 1337 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1338 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1339 clock-names = "sor", "out", "parent", "dp", "safe", 1340 "pad"; 1341 resets = <&bpmp TEGRA194_RESET_SOR1>; 1342 reset-names = "sor"; 1343 pinctrl-0 = <&state_dpaux1_aux>; 1344 pinctrl-1 = <&state_dpaux1_i2c>; 1345 pinctrl-2 = <&state_dpaux1_off>; 1346 pinctrl-names = "aux", "i2c", "off"; 1347 status = "disabled"; 1348 1349 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1350 nvidia,interface = <1>; 1351 }; 1352 1353 sor2: sor@15b80000 { 1354 compatible = "nvidia,tegra194-sor"; 1355 reg = <0x15b80000 0x40000>; 1356 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1358 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1359 <&bpmp TEGRA194_CLK_PLLD3>, 1360 <&bpmp TEGRA194_CLK_PLLDP>, 1361 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1362 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1363 clock-names = "sor", "out", "parent", "dp", "safe", 1364 "pad"; 1365 resets = <&bpmp TEGRA194_RESET_SOR2>; 1366 reset-names = "sor"; 1367 pinctrl-0 = <&state_dpaux2_aux>; 1368 pinctrl-1 = <&state_dpaux2_i2c>; 1369 pinctrl-2 = <&state_dpaux2_off>; 1370 pinctrl-names = "aux", "i2c", "off"; 1371 status = "disabled"; 1372 1373 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1374 nvidia,interface = <2>; 1375 }; 1376 1377 sor3: sor@15bc0000 { 1378 compatible = "nvidia,tegra194-sor"; 1379 reg = <0x15bc0000 0x40000>; 1380 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1381 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1382 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1383 <&bpmp TEGRA194_CLK_PLLD4>, 1384 <&bpmp TEGRA194_CLK_PLLDP>, 1385 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1386 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1387 clock-names = "sor", "out", "parent", "dp", "safe", 1388 "pad"; 1389 resets = <&bpmp TEGRA194_RESET_SOR3>; 1390 reset-names = "sor"; 1391 pinctrl-0 = <&state_dpaux3_aux>; 1392 pinctrl-1 = <&state_dpaux3_i2c>; 1393 pinctrl-2 = <&state_dpaux3_off>; 1394 pinctrl-names = "aux", "i2c", "off"; 1395 status = "disabled"; 1396 1397 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1398 nvidia,interface = <3>; 1399 }; 1400 }; 1401 }; 1402 1403 pcie@14100000 { 1404 compatible = "nvidia,tegra194-pcie"; 1405 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1406 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1407 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1408 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1409 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1410 reg-names = "appl", "config", "atu_dma", "dbi"; 1411 1412 status = "disabled"; 1413 1414 #address-cells = <3>; 1415 #size-cells = <2>; 1416 device_type = "pci"; 1417 num-lanes = <1>; 1418 num-viewport = <8>; 1419 linux,pci-domain = <1>; 1420 1421 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1422 clock-names = "core"; 1423 1424 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1425 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1426 reset-names = "apb", "core"; 1427 1428 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1429 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1430 interrupt-names = "intr", "msi"; 1431 1432 #interrupt-cells = <1>; 1433 interrupt-map-mask = <0 0 0 0>; 1434 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1435 1436 nvidia,bpmp = <&bpmp 1>; 1437 1438 nvidia,aspm-cmrt-us = <60>; 1439 nvidia,aspm-pwr-on-t-us = <20>; 1440 nvidia,aspm-l0s-entrance-latency-us = <3>; 1441 1442 bus-range = <0x0 0xff>; 1443 1444 ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, /* downstream I/O (1MB) */ 1445 <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768MB) */ 1446 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1447 1448 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1449 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1450 interconnect-names = "read", "write"; 1451 }; 1452 1453 pcie@14120000 { 1454 compatible = "nvidia,tegra194-pcie"; 1455 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1456 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1457 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1458 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1459 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1460 reg-names = "appl", "config", "atu_dma", "dbi"; 1461 1462 status = "disabled"; 1463 1464 #address-cells = <3>; 1465 #size-cells = <2>; 1466 device_type = "pci"; 1467 num-lanes = <1>; 1468 num-viewport = <8>; 1469 linux,pci-domain = <2>; 1470 1471 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1472 clock-names = "core"; 1473 1474 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1475 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1476 reset-names = "apb", "core"; 1477 1478 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1479 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1480 interrupt-names = "intr", "msi"; 1481 1482 #interrupt-cells = <1>; 1483 interrupt-map-mask = <0 0 0 0>; 1484 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1485 1486 nvidia,bpmp = <&bpmp 2>; 1487 1488 nvidia,aspm-cmrt-us = <60>; 1489 nvidia,aspm-pwr-on-t-us = <20>; 1490 nvidia,aspm-l0s-entrance-latency-us = <3>; 1491 1492 bus-range = <0x0 0xff>; 1493 1494 ranges = <0x01000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000>, /* downstream I/O (1MB) */ 1495 <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768MB) */ 1496 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1497 1498 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1499 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1500 interconnect-names = "read", "write"; 1501 }; 1502 1503 pcie@14140000 { 1504 compatible = "nvidia,tegra194-pcie"; 1505 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1506 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1507 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1508 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1509 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1510 reg-names = "appl", "config", "atu_dma", "dbi"; 1511 1512 status = "disabled"; 1513 1514 #address-cells = <3>; 1515 #size-cells = <2>; 1516 device_type = "pci"; 1517 num-lanes = <1>; 1518 num-viewport = <8>; 1519 linux,pci-domain = <3>; 1520 1521 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1522 clock-names = "core"; 1523 1524 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1525 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1526 reset-names = "apb", "core"; 1527 1528 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1529 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1530 interrupt-names = "intr", "msi"; 1531 1532 #interrupt-cells = <1>; 1533 interrupt-map-mask = <0 0 0 0>; 1534 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1535 1536 nvidia,bpmp = <&bpmp 3>; 1537 1538 nvidia,aspm-cmrt-us = <60>; 1539 nvidia,aspm-pwr-on-t-us = <20>; 1540 nvidia,aspm-l0s-entrance-latency-us = <3>; 1541 1542 bus-range = <0x0 0xff>; 1543 1544 ranges = <0x01000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000>, /* downstream I/O (1MB) */ 1545 <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768MB) */ 1546 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1547 1548 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1549 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1550 interconnect-names = "read", "write"; 1551 }; 1552 1553 pcie@14160000 { 1554 compatible = "nvidia,tegra194-pcie"; 1555 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1556 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1557 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1558 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1559 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1560 reg-names = "appl", "config", "atu_dma", "dbi"; 1561 1562 status = "disabled"; 1563 1564 #address-cells = <3>; 1565 #size-cells = <2>; 1566 device_type = "pci"; 1567 num-lanes = <4>; 1568 num-viewport = <8>; 1569 linux,pci-domain = <4>; 1570 1571 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1572 clock-names = "core"; 1573 1574 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1575 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1576 reset-names = "apb", "core"; 1577 1578 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1579 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1580 interrupt-names = "intr", "msi"; 1581 1582 #interrupt-cells = <1>; 1583 interrupt-map-mask = <0 0 0 0>; 1584 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1585 1586 nvidia,bpmp = <&bpmp 4>; 1587 1588 nvidia,aspm-cmrt-us = <60>; 1589 nvidia,aspm-pwr-on-t-us = <20>; 1590 nvidia,aspm-l0s-entrance-latency-us = <3>; 1591 1592 bus-range = <0x0 0xff>; 1593 1594 ranges = <0x01000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000>, /* downstream I/O (1MB) */ 1595 <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13GB) */ 1596 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1597 1598 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1599 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1600 interconnect-names = "read", "write"; 1601 }; 1602 1603 pcie@14180000 { 1604 compatible = "nvidia,tegra194-pcie"; 1605 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1606 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1607 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1608 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1609 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1610 reg-names = "appl", "config", "atu_dma", "dbi"; 1611 1612 status = "disabled"; 1613 1614 #address-cells = <3>; 1615 #size-cells = <2>; 1616 device_type = "pci"; 1617 num-lanes = <8>; 1618 num-viewport = <8>; 1619 linux,pci-domain = <0>; 1620 1621 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1622 clock-names = "core"; 1623 1624 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1625 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1626 reset-names = "apb", "core"; 1627 1628 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1629 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1630 interrupt-names = "intr", "msi"; 1631 1632 #interrupt-cells = <1>; 1633 interrupt-map-mask = <0 0 0 0>; 1634 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1635 1636 nvidia,bpmp = <&bpmp 0>; 1637 1638 nvidia,aspm-cmrt-us = <60>; 1639 nvidia,aspm-pwr-on-t-us = <20>; 1640 nvidia,aspm-l0s-entrance-latency-us = <3>; 1641 1642 bus-range = <0x0 0xff>; 1643 1644 ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O (1MB) */ 1645 <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13GB) */ 1646 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1647 1648 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1649 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1650 interconnect-names = "read", "write"; 1651 }; 1652 1653 pcie@141a0000 { 1654 compatible = "nvidia,tegra194-pcie"; 1655 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1656 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1657 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1658 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1659 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1660 reg-names = "appl", "config", "atu_dma", "dbi"; 1661 1662 status = "disabled"; 1663 1664 #address-cells = <3>; 1665 #size-cells = <2>; 1666 device_type = "pci"; 1667 num-lanes = <8>; 1668 num-viewport = <8>; 1669 linux,pci-domain = <5>; 1670 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1673 1674 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1675 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1676 clock-names = "core", "core_m"; 1677 1678 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1679 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1680 reset-names = "apb", "core"; 1681 1682 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1683 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1684 interrupt-names = "intr", "msi"; 1685 1686 nvidia,bpmp = <&bpmp 5>; 1687 1688 #interrupt-cells = <1>; 1689 interrupt-map-mask = <0 0 0 0>; 1690 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1691 1692 nvidia,aspm-cmrt-us = <60>; 1693 nvidia,aspm-pwr-on-t-us = <20>; 1694 nvidia,aspm-l0s-entrance-latency-us = <3>; 1695 1696 bus-range = <0x0 0xff>; 1697 1698 ranges = <0x01000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000>, /* downstream I/O (1MB) */ 1699 <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13GB) */ 1700 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1701 1702 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1703 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1704 interconnect-names = "read", "write"; 1705 }; 1706 1707 pcie_ep@14160000 { 1708 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1709 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1710 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1711 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1712 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1713 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1714 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1715 1716 status = "disabled"; 1717 1718 num-lanes = <4>; 1719 num-ib-windows = <2>; 1720 num-ob-windows = <8>; 1721 1722 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1723 clock-names = "core"; 1724 1725 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1726 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1727 reset-names = "apb", "core"; 1728 1729 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1730 interrupt-names = "intr"; 1731 1732 nvidia,bpmp = <&bpmp 4>; 1733 1734 nvidia,aspm-cmrt-us = <60>; 1735 nvidia,aspm-pwr-on-t-us = <20>; 1736 nvidia,aspm-l0s-entrance-latency-us = <3>; 1737 }; 1738 1739 pcie_ep@14180000 { 1740 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1741 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1742 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1743 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1744 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1745 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1746 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1747 1748 status = "disabled"; 1749 1750 num-lanes = <8>; 1751 num-ib-windows = <2>; 1752 num-ob-windows = <8>; 1753 1754 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1755 clock-names = "core"; 1756 1757 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1758 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1759 reset-names = "apb", "core"; 1760 1761 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1762 interrupt-names = "intr"; 1763 1764 nvidia,bpmp = <&bpmp 0>; 1765 1766 nvidia,aspm-cmrt-us = <60>; 1767 nvidia,aspm-pwr-on-t-us = <20>; 1768 nvidia,aspm-l0s-entrance-latency-us = <3>; 1769 }; 1770 1771 pcie_ep@141a0000 { 1772 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1773 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1774 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1775 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1776 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1777 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1778 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1779 1780 status = "disabled"; 1781 1782 num-lanes = <8>; 1783 num-ib-windows = <2>; 1784 num-ob-windows = <8>; 1785 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 1788 1789 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 1790 clock-names = "core"; 1791 1792 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1793 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1794 reset-names = "apb", "core"; 1795 1796 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1797 interrupt-names = "intr"; 1798 1799 nvidia,bpmp = <&bpmp 5>; 1800 1801 nvidia,aspm-cmrt-us = <60>; 1802 nvidia,aspm-pwr-on-t-us = <20>; 1803 nvidia,aspm-l0s-entrance-latency-us = <3>; 1804 }; 1805 1806 sram@40000000 { 1807 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 1808 reg = <0x0 0x40000000 0x0 0x50000>; 1809 #address-cells = <1>; 1810 #size-cells = <1>; 1811 ranges = <0x0 0x0 0x40000000 0x50000>; 1812 1813 cpu_bpmp_tx: sram@4e000 { 1814 reg = <0x4e000 0x1000>; 1815 label = "cpu-bpmp-tx"; 1816 pool; 1817 }; 1818 1819 cpu_bpmp_rx: sram@4f000 { 1820 reg = <0x4f000 0x1000>; 1821 label = "cpu-bpmp-rx"; 1822 pool; 1823 }; 1824 }; 1825 1826 bpmp: bpmp { 1827 compatible = "nvidia,tegra186-bpmp"; 1828 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1829 TEGRA_HSP_DB_MASTER_BPMP>; 1830 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1831 #clock-cells = <1>; 1832 #reset-cells = <1>; 1833 #power-domain-cells = <1>; 1834 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 1835 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 1836 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 1837 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 1838 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1839 1840 bpmp_i2c: i2c { 1841 compatible = "nvidia,tegra186-bpmp-i2c"; 1842 nvidia,bpmp-bus-id = <5>; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 }; 1846 1847 bpmp_thermal: thermal { 1848 compatible = "nvidia,tegra186-bpmp-thermal"; 1849 #thermal-sensor-cells = <1>; 1850 }; 1851 }; 1852 1853 cpus { 1854 #address-cells = <1>; 1855 #size-cells = <0>; 1856 1857 cpu0_0: cpu@0 { 1858 compatible = "nvidia,tegra194-carmel"; 1859 device_type = "cpu"; 1860 reg = <0x000>; 1861 enable-method = "psci"; 1862 i-cache-size = <131072>; 1863 i-cache-line-size = <64>; 1864 i-cache-sets = <512>; 1865 d-cache-size = <65536>; 1866 d-cache-line-size = <64>; 1867 d-cache-sets = <256>; 1868 next-level-cache = <&l2c_0>; 1869 }; 1870 1871 cpu0_1: cpu@1 { 1872 compatible = "nvidia,tegra194-carmel"; 1873 device_type = "cpu"; 1874 reg = <0x001>; 1875 enable-method = "psci"; 1876 i-cache-size = <131072>; 1877 i-cache-line-size = <64>; 1878 i-cache-sets = <512>; 1879 d-cache-size = <65536>; 1880 d-cache-line-size = <64>; 1881 d-cache-sets = <256>; 1882 next-level-cache = <&l2c_0>; 1883 }; 1884 1885 cpu1_0: cpu@100 { 1886 compatible = "nvidia,tegra194-carmel"; 1887 device_type = "cpu"; 1888 reg = <0x100>; 1889 enable-method = "psci"; 1890 i-cache-size = <131072>; 1891 i-cache-line-size = <64>; 1892 i-cache-sets = <512>; 1893 d-cache-size = <65536>; 1894 d-cache-line-size = <64>; 1895 d-cache-sets = <256>; 1896 next-level-cache = <&l2c_1>; 1897 }; 1898 1899 cpu1_1: cpu@101 { 1900 compatible = "nvidia,tegra194-carmel"; 1901 device_type = "cpu"; 1902 reg = <0x101>; 1903 enable-method = "psci"; 1904 i-cache-size = <131072>; 1905 i-cache-line-size = <64>; 1906 i-cache-sets = <512>; 1907 d-cache-size = <65536>; 1908 d-cache-line-size = <64>; 1909 d-cache-sets = <256>; 1910 next-level-cache = <&l2c_1>; 1911 }; 1912 1913 cpu2_0: cpu@200 { 1914 compatible = "nvidia,tegra194-carmel"; 1915 device_type = "cpu"; 1916 reg = <0x200>; 1917 enable-method = "psci"; 1918 i-cache-size = <131072>; 1919 i-cache-line-size = <64>; 1920 i-cache-sets = <512>; 1921 d-cache-size = <65536>; 1922 d-cache-line-size = <64>; 1923 d-cache-sets = <256>; 1924 next-level-cache = <&l2c_2>; 1925 }; 1926 1927 cpu2_1: cpu@201 { 1928 compatible = "nvidia,tegra194-carmel"; 1929 device_type = "cpu"; 1930 reg = <0x201>; 1931 enable-method = "psci"; 1932 i-cache-size = <131072>; 1933 i-cache-line-size = <64>; 1934 i-cache-sets = <512>; 1935 d-cache-size = <65536>; 1936 d-cache-line-size = <64>; 1937 d-cache-sets = <256>; 1938 next-level-cache = <&l2c_2>; 1939 }; 1940 1941 cpu3_0: cpu@300 { 1942 compatible = "nvidia,tegra194-carmel"; 1943 device_type = "cpu"; 1944 reg = <0x300>; 1945 enable-method = "psci"; 1946 i-cache-size = <131072>; 1947 i-cache-line-size = <64>; 1948 i-cache-sets = <512>; 1949 d-cache-size = <65536>; 1950 d-cache-line-size = <64>; 1951 d-cache-sets = <256>; 1952 next-level-cache = <&l2c_3>; 1953 }; 1954 1955 cpu3_1: cpu@301 { 1956 compatible = "nvidia,tegra194-carmel"; 1957 device_type = "cpu"; 1958 reg = <0x301>; 1959 enable-method = "psci"; 1960 i-cache-size = <131072>; 1961 i-cache-line-size = <64>; 1962 i-cache-sets = <512>; 1963 d-cache-size = <65536>; 1964 d-cache-line-size = <64>; 1965 d-cache-sets = <256>; 1966 next-level-cache = <&l2c_3>; 1967 }; 1968 1969 cpu-map { 1970 cluster0 { 1971 core0 { 1972 cpu = <&cpu0_0>; 1973 }; 1974 1975 core1 { 1976 cpu = <&cpu0_1>; 1977 }; 1978 }; 1979 1980 cluster1 { 1981 core0 { 1982 cpu = <&cpu1_0>; 1983 }; 1984 1985 core1 { 1986 cpu = <&cpu1_1>; 1987 }; 1988 }; 1989 1990 cluster2 { 1991 core0 { 1992 cpu = <&cpu2_0>; 1993 }; 1994 1995 core1 { 1996 cpu = <&cpu2_1>; 1997 }; 1998 }; 1999 2000 cluster3 { 2001 core0 { 2002 cpu = <&cpu3_0>; 2003 }; 2004 2005 core1 { 2006 cpu = <&cpu3_1>; 2007 }; 2008 }; 2009 }; 2010 2011 l2c_0: l2-cache0 { 2012 cache-size = <2097152>; 2013 cache-line-size = <64>; 2014 cache-sets = <2048>; 2015 next-level-cache = <&l3c>; 2016 }; 2017 2018 l2c_1: l2-cache1 { 2019 cache-size = <2097152>; 2020 cache-line-size = <64>; 2021 cache-sets = <2048>; 2022 next-level-cache = <&l3c>; 2023 }; 2024 2025 l2c_2: l2-cache2 { 2026 cache-size = <2097152>; 2027 cache-line-size = <64>; 2028 cache-sets = <2048>; 2029 next-level-cache = <&l3c>; 2030 }; 2031 2032 l2c_3: l2-cache3 { 2033 cache-size = <2097152>; 2034 cache-line-size = <64>; 2035 cache-sets = <2048>; 2036 next-level-cache = <&l3c>; 2037 }; 2038 2039 l3c: l3-cache { 2040 cache-size = <4194304>; 2041 cache-line-size = <64>; 2042 cache-sets = <4096>; 2043 }; 2044 }; 2045 2046 psci { 2047 compatible = "arm,psci-1.0"; 2048 status = "okay"; 2049 method = "smc"; 2050 }; 2051 2052 tcu: tcu { 2053 compatible = "nvidia,tegra194-tcu"; 2054 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2055 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2056 mbox-names = "rx", "tx"; 2057 }; 2058 2059 thermal-zones { 2060 cpu { 2061 thermal-sensors = <&{/bpmp/thermal} 2062 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2063 status = "disabled"; 2064 }; 2065 2066 gpu { 2067 thermal-sensors = <&{/bpmp/thermal} 2068 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2069 status = "disabled"; 2070 }; 2071 2072 aux { 2073 thermal-sensors = <&{/bpmp/thermal} 2074 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2075 status = "disabled"; 2076 }; 2077 2078 pllx { 2079 thermal-sensors = <&{/bpmp/thermal} 2080 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2081 status = "disabled"; 2082 }; 2083 2084 ao { 2085 thermal-sensors = <&{/bpmp/thermal} 2086 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2087 status = "disabled"; 2088 }; 2089 2090 tj { 2091 thermal-sensors = <&{/bpmp/thermal} 2092 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2093 status = "disabled"; 2094 }; 2095 }; 2096 2097 timer { 2098 compatible = "arm,armv8-timer"; 2099 interrupts = <GIC_PPI 13 2100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2101 <GIC_PPI 14 2102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2103 <GIC_PPI 11 2104 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2105 <GIC_PPI 10 2106 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2107 interrupt-parent = <&gic>; 2108 always-on; 2109 }; 2110}; 2111