1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 bus@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64 interconnect-names = "dma-mem", "write"; 65 status = "disabled"; 66 67 snps,write-requests = <1>; 68 snps,read-requests = <3>; 69 snps,burst-map = <0x7>; 70 snps,txpbl = <16>; 71 snps,rxpbl = <8>; 72 }; 73 74 aconnect@2900000 { 75 compatible = "nvidia,tegra194-aconnect", 76 "nvidia,tegra210-aconnect"; 77 clocks = <&bpmp TEGRA194_CLK_APE>, 78 <&bpmp TEGRA194_CLK_APB2APE>; 79 clock-names = "ape", "apb2ape"; 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x02900000 0x02900000 0x200000>; 84 status = "disabled"; 85 86 adma: dma-controller@2930000 { 87 compatible = "nvidia,tegra194-adma", 88 "nvidia,tegra186-adma"; 89 reg = <0x02930000 0x20000>; 90 interrupt-parent = <&agic>; 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 123 #dma-cells = <1>; 124 clocks = <&bpmp TEGRA194_CLK_AHUB>; 125 clock-names = "d_audio"; 126 status = "disabled"; 127 }; 128 129 agic: interrupt-controller@2a40000 { 130 compatible = "nvidia,tegra194-agic", 131 "nvidia,tegra210-agic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x02a41000 0x1000>, 135 <0x02a42000 0x2000>; 136 interrupts = <GIC_SPI 145 137 (GIC_CPU_MASK_SIMPLE(4) | 138 IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA194_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 144 tegra_ahub: ahub@2900800 { 145 compatible = "nvidia,tegra194-ahub", 146 "nvidia,tegra186-ahub"; 147 reg = <0x02900800 0x800>; 148 clocks = <&bpmp TEGRA194_CLK_AHUB>; 149 clock-names = "ahub"; 150 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 151 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges = <0x02900800 0x02900800 0x11800>; 155 status = "disabled"; 156 157 tegra_admaif: admaif@290f000 { 158 compatible = "nvidia,tegra194-admaif", 159 "nvidia,tegra186-admaif"; 160 reg = <0x0290f000 0x1000>; 161 dmas = <&adma 1>, <&adma 1>, 162 <&adma 2>, <&adma 2>, 163 <&adma 3>, <&adma 3>, 164 <&adma 4>, <&adma 4>, 165 <&adma 5>, <&adma 5>, 166 <&adma 6>, <&adma 6>, 167 <&adma 7>, <&adma 7>, 168 <&adma 8>, <&adma 8>, 169 <&adma 9>, <&adma 9>, 170 <&adma 10>, <&adma 10>, 171 <&adma 11>, <&adma 11>, 172 <&adma 12>, <&adma 12>, 173 <&adma 13>, <&adma 13>, 174 <&adma 14>, <&adma 14>, 175 <&adma 15>, <&adma 15>, 176 <&adma 16>, <&adma 16>, 177 <&adma 17>, <&adma 17>, 178 <&adma 18>, <&adma 18>, 179 <&adma 19>, <&adma 19>, 180 <&adma 20>, <&adma 20>; 181 dma-names = "rx1", "tx1", 182 "rx2", "tx2", 183 "rx3", "tx3", 184 "rx4", "tx4", 185 "rx5", "tx5", 186 "rx6", "tx6", 187 "rx7", "tx7", 188 "rx8", "tx8", 189 "rx9", "tx9", 190 "rx10", "tx10", 191 "rx11", "tx11", 192 "rx12", "tx12", 193 "rx13", "tx13", 194 "rx14", "tx14", 195 "rx15", "tx15", 196 "rx16", "tx16", 197 "rx17", "tx17", 198 "rx18", "tx18", 199 "rx19", "tx19", 200 "rx20", "tx20"; 201 status = "disabled"; 202 }; 203 204 tegra_i2s1: i2s@2901000 { 205 compatible = "nvidia,tegra194-i2s", 206 "nvidia,tegra210-i2s"; 207 reg = <0x2901000 0x100>; 208 clocks = <&bpmp TEGRA194_CLK_I2S1>, 209 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 210 clock-names = "i2s", "sync_input"; 211 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 212 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 213 assigned-clock-rates = <1536000>; 214 sound-name-prefix = "I2S1"; 215 status = "disabled"; 216 }; 217 218 tegra_i2s2: i2s@2901100 { 219 compatible = "nvidia,tegra194-i2s", 220 "nvidia,tegra210-i2s"; 221 reg = <0x2901100 0x100>; 222 clocks = <&bpmp TEGRA194_CLK_I2S2>, 223 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 224 clock-names = "i2s", "sync_input"; 225 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 226 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 227 assigned-clock-rates = <1536000>; 228 sound-name-prefix = "I2S2"; 229 status = "disabled"; 230 }; 231 232 tegra_i2s3: i2s@2901200 { 233 compatible = "nvidia,tegra194-i2s", 234 "nvidia,tegra210-i2s"; 235 reg = <0x2901200 0x100>; 236 clocks = <&bpmp TEGRA194_CLK_I2S3>, 237 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 238 clock-names = "i2s", "sync_input"; 239 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 240 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 241 assigned-clock-rates = <1536000>; 242 sound-name-prefix = "I2S3"; 243 status = "disabled"; 244 }; 245 246 tegra_i2s4: i2s@2901300 { 247 compatible = "nvidia,tegra194-i2s", 248 "nvidia,tegra210-i2s"; 249 reg = <0x2901300 0x100>; 250 clocks = <&bpmp TEGRA194_CLK_I2S4>, 251 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 252 clock-names = "i2s", "sync_input"; 253 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 254 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 255 assigned-clock-rates = <1536000>; 256 sound-name-prefix = "I2S4"; 257 status = "disabled"; 258 }; 259 260 tegra_i2s5: i2s@2901400 { 261 compatible = "nvidia,tegra194-i2s", 262 "nvidia,tegra210-i2s"; 263 reg = <0x2901400 0x100>; 264 clocks = <&bpmp TEGRA194_CLK_I2S5>, 265 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 266 clock-names = "i2s", "sync_input"; 267 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 268 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 269 assigned-clock-rates = <1536000>; 270 sound-name-prefix = "I2S5"; 271 status = "disabled"; 272 }; 273 274 tegra_i2s6: i2s@2901500 { 275 compatible = "nvidia,tegra194-i2s", 276 "nvidia,tegra210-i2s"; 277 reg = <0x2901500 0x100>; 278 clocks = <&bpmp TEGRA194_CLK_I2S6>, 279 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 280 clock-names = "i2s", "sync_input"; 281 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 282 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 283 assigned-clock-rates = <1536000>; 284 sound-name-prefix = "I2S6"; 285 status = "disabled"; 286 }; 287 288 tegra_dmic1: dmic@2904000 { 289 compatible = "nvidia,tegra194-dmic", 290 "nvidia,tegra210-dmic"; 291 reg = <0x2904000 0x100>; 292 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 293 clock-names = "dmic"; 294 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 295 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 296 assigned-clock-rates = <3072000>; 297 sound-name-prefix = "DMIC1"; 298 status = "disabled"; 299 }; 300 301 tegra_dmic2: dmic@2904100 { 302 compatible = "nvidia,tegra194-dmic", 303 "nvidia,tegra210-dmic"; 304 reg = <0x2904100 0x100>; 305 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 306 clock-names = "dmic"; 307 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 308 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 309 assigned-clock-rates = <3072000>; 310 sound-name-prefix = "DMIC2"; 311 status = "disabled"; 312 }; 313 314 tegra_dmic3: dmic@2904200 { 315 compatible = "nvidia,tegra194-dmic", 316 "nvidia,tegra210-dmic"; 317 reg = <0x2904200 0x100>; 318 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 319 clock-names = "dmic"; 320 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 321 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 322 assigned-clock-rates = <3072000>; 323 sound-name-prefix = "DMIC3"; 324 status = "disabled"; 325 }; 326 327 tegra_dmic4: dmic@2904300 { 328 compatible = "nvidia,tegra194-dmic", 329 "nvidia,tegra210-dmic"; 330 reg = <0x2904300 0x100>; 331 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 332 clock-names = "dmic"; 333 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 334 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 335 assigned-clock-rates = <3072000>; 336 sound-name-prefix = "DMIC4"; 337 status = "disabled"; 338 }; 339 340 tegra_dspk1: dspk@2905000 { 341 compatible = "nvidia,tegra194-dspk", 342 "nvidia,tegra186-dspk"; 343 reg = <0x2905000 0x100>; 344 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 345 clock-names = "dspk"; 346 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 347 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 348 assigned-clock-rates = <12288000>; 349 sound-name-prefix = "DSPK1"; 350 status = "disabled"; 351 }; 352 353 tegra_dspk2: dspk@2905100 { 354 compatible = "nvidia,tegra194-dspk", 355 "nvidia,tegra186-dspk"; 356 reg = <0x2905100 0x100>; 357 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 358 clock-names = "dspk"; 359 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 360 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 361 assigned-clock-rates = <12288000>; 362 sound-name-prefix = "DSPK2"; 363 status = "disabled"; 364 }; 365 }; 366 }; 367 368 pinmux: pinmux@2430000 { 369 compatible = "nvidia,tegra194-pinmux"; 370 reg = <0x2430000 0x17000>, 371 <0xc300000 0x4000>; 372 373 status = "okay"; 374 375 pex_rst_c5_out_state: pex_rst_c5_out { 376 pex_rst { 377 nvidia,pins = "pex_l5_rst_n_pgg1"; 378 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 379 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 380 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 381 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 382 nvidia,tristate = <TEGRA_PIN_DISABLE>; 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384 }; 385 }; 386 387 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 388 clkreq { 389 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 390 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 391 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 392 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 393 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 394 nvidia,tristate = <TEGRA_PIN_DISABLE>; 395 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 396 }; 397 }; 398 }; 399 400 mc: memory-controller@2c00000 { 401 compatible = "nvidia,tegra194-mc"; 402 reg = <0x02c00000 0x100000>, 403 <0x02b80000 0x040000>, 404 <0x01700000 0x100000>; 405 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 406 #interconnect-cells = <1>; 407 status = "disabled"; 408 409 #address-cells = <2>; 410 #size-cells = <2>; 411 412 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 413 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 414 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 415 416 /* 417 * Bit 39 of addresses passing through the memory 418 * controller selects the XBAR format used when memory 419 * is accessed. This is used to transparently access 420 * memory in the XBAR format used by the discrete GPU 421 * (bit 39 set) or Tegra (bit 39 clear). 422 * 423 * As a consequence, the operating system must ensure 424 * that bit 39 is never used implicitly, for example 425 * via an I/O virtual address mapping of an IOMMU. If 426 * devices require access to the XBAR switch, their 427 * drivers must set this bit explicitly. 428 * 429 * Limit the DMA range for memory clients to [38:0]. 430 */ 431 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 432 433 emc: external-memory-controller@2c60000 { 434 compatible = "nvidia,tegra194-emc"; 435 reg = <0x0 0x02c60000 0x0 0x90000>, 436 <0x0 0x01780000 0x0 0x80000>; 437 clocks = <&bpmp TEGRA194_CLK_EMC>; 438 clock-names = "emc"; 439 440 #interconnect-cells = <0>; 441 442 nvidia,bpmp = <&bpmp>; 443 }; 444 }; 445 446 uarta: serial@3100000 { 447 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 448 reg = <0x03100000 0x40>; 449 reg-shift = <2>; 450 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&bpmp TEGRA194_CLK_UARTA>; 452 clock-names = "serial"; 453 resets = <&bpmp TEGRA194_RESET_UARTA>; 454 reset-names = "serial"; 455 status = "disabled"; 456 }; 457 458 uartb: serial@3110000 { 459 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 460 reg = <0x03110000 0x40>; 461 reg-shift = <2>; 462 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&bpmp TEGRA194_CLK_UARTB>; 464 clock-names = "serial"; 465 resets = <&bpmp TEGRA194_RESET_UARTB>; 466 reset-names = "serial"; 467 status = "disabled"; 468 }; 469 470 uartd: serial@3130000 { 471 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 472 reg = <0x03130000 0x40>; 473 reg-shift = <2>; 474 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&bpmp TEGRA194_CLK_UARTD>; 476 clock-names = "serial"; 477 resets = <&bpmp TEGRA194_RESET_UARTD>; 478 reset-names = "serial"; 479 status = "disabled"; 480 }; 481 482 uarte: serial@3140000 { 483 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 484 reg = <0x03140000 0x40>; 485 reg-shift = <2>; 486 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&bpmp TEGRA194_CLK_UARTE>; 488 clock-names = "serial"; 489 resets = <&bpmp TEGRA194_RESET_UARTE>; 490 reset-names = "serial"; 491 status = "disabled"; 492 }; 493 494 uartf: serial@3150000 { 495 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 496 reg = <0x03150000 0x40>; 497 reg-shift = <2>; 498 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&bpmp TEGRA194_CLK_UARTF>; 500 clock-names = "serial"; 501 resets = <&bpmp TEGRA194_RESET_UARTF>; 502 reset-names = "serial"; 503 status = "disabled"; 504 }; 505 506 gen1_i2c: i2c@3160000 { 507 compatible = "nvidia,tegra194-i2c"; 508 reg = <0x03160000 0x10000>; 509 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 clocks = <&bpmp TEGRA194_CLK_I2C1>; 513 clock-names = "div-clk"; 514 resets = <&bpmp TEGRA194_RESET_I2C1>; 515 reset-names = "i2c"; 516 status = "disabled"; 517 }; 518 519 uarth: serial@3170000 { 520 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 521 reg = <0x03170000 0x40>; 522 reg-shift = <2>; 523 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&bpmp TEGRA194_CLK_UARTH>; 525 clock-names = "serial"; 526 resets = <&bpmp TEGRA194_RESET_UARTH>; 527 reset-names = "serial"; 528 status = "disabled"; 529 }; 530 531 cam_i2c: i2c@3180000 { 532 compatible = "nvidia,tegra194-i2c"; 533 reg = <0x03180000 0x10000>; 534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 clocks = <&bpmp TEGRA194_CLK_I2C3>; 538 clock-names = "div-clk"; 539 resets = <&bpmp TEGRA194_RESET_I2C3>; 540 reset-names = "i2c"; 541 status = "disabled"; 542 }; 543 544 /* shares pads with dpaux1 */ 545 dp_aux_ch1_i2c: i2c@3190000 { 546 compatible = "nvidia,tegra194-i2c"; 547 reg = <0x03190000 0x10000>; 548 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clocks = <&bpmp TEGRA194_CLK_I2C4>; 552 clock-names = "div-clk"; 553 resets = <&bpmp TEGRA194_RESET_I2C4>; 554 reset-names = "i2c"; 555 pinctrl-0 = <&state_dpaux1_i2c>; 556 pinctrl-1 = <&state_dpaux1_off>; 557 pinctrl-names = "default", "idle"; 558 status = "disabled"; 559 }; 560 561 /* shares pads with dpaux0 */ 562 dp_aux_ch0_i2c: i2c@31b0000 { 563 compatible = "nvidia,tegra194-i2c"; 564 reg = <0x031b0000 0x10000>; 565 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&bpmp TEGRA194_CLK_I2C6>; 569 clock-names = "div-clk"; 570 resets = <&bpmp TEGRA194_RESET_I2C6>; 571 reset-names = "i2c"; 572 pinctrl-0 = <&state_dpaux0_i2c>; 573 pinctrl-1 = <&state_dpaux0_off>; 574 pinctrl-names = "default", "idle"; 575 status = "disabled"; 576 }; 577 578 /* shares pads with dpaux2 */ 579 dp_aux_ch2_i2c: i2c@31c0000 { 580 compatible = "nvidia,tegra194-i2c"; 581 reg = <0x031c0000 0x10000>; 582 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 clocks = <&bpmp TEGRA194_CLK_I2C7>; 586 clock-names = "div-clk"; 587 resets = <&bpmp TEGRA194_RESET_I2C7>; 588 reset-names = "i2c"; 589 pinctrl-0 = <&state_dpaux2_i2c>; 590 pinctrl-1 = <&state_dpaux2_off>; 591 pinctrl-names = "default", "idle"; 592 status = "disabled"; 593 }; 594 595 /* shares pads with dpaux3 */ 596 dp_aux_ch3_i2c: i2c@31e0000 { 597 compatible = "nvidia,tegra194-i2c"; 598 reg = <0x031e0000 0x10000>; 599 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 clocks = <&bpmp TEGRA194_CLK_I2C9>; 603 clock-names = "div-clk"; 604 resets = <&bpmp TEGRA194_RESET_I2C9>; 605 reset-names = "i2c"; 606 pinctrl-0 = <&state_dpaux3_i2c>; 607 pinctrl-1 = <&state_dpaux3_off>; 608 pinctrl-names = "default", "idle"; 609 status = "disabled"; 610 }; 611 612 pwm1: pwm@3280000 { 613 compatible = "nvidia,tegra194-pwm", 614 "nvidia,tegra186-pwm"; 615 reg = <0x3280000 0x10000>; 616 clocks = <&bpmp TEGRA194_CLK_PWM1>; 617 clock-names = "pwm"; 618 resets = <&bpmp TEGRA194_RESET_PWM1>; 619 reset-names = "pwm"; 620 status = "disabled"; 621 #pwm-cells = <2>; 622 }; 623 624 pwm2: pwm@3290000 { 625 compatible = "nvidia,tegra194-pwm", 626 "nvidia,tegra186-pwm"; 627 reg = <0x3290000 0x10000>; 628 clocks = <&bpmp TEGRA194_CLK_PWM2>; 629 clock-names = "pwm"; 630 resets = <&bpmp TEGRA194_RESET_PWM2>; 631 reset-names = "pwm"; 632 status = "disabled"; 633 #pwm-cells = <2>; 634 }; 635 636 pwm3: pwm@32a0000 { 637 compatible = "nvidia,tegra194-pwm", 638 "nvidia,tegra186-pwm"; 639 reg = <0x32a0000 0x10000>; 640 clocks = <&bpmp TEGRA194_CLK_PWM3>; 641 clock-names = "pwm"; 642 resets = <&bpmp TEGRA194_RESET_PWM3>; 643 reset-names = "pwm"; 644 status = "disabled"; 645 #pwm-cells = <2>; 646 }; 647 648 pwm5: pwm@32c0000 { 649 compatible = "nvidia,tegra194-pwm", 650 "nvidia,tegra186-pwm"; 651 reg = <0x32c0000 0x10000>; 652 clocks = <&bpmp TEGRA194_CLK_PWM5>; 653 clock-names = "pwm"; 654 resets = <&bpmp TEGRA194_RESET_PWM5>; 655 reset-names = "pwm"; 656 status = "disabled"; 657 #pwm-cells = <2>; 658 }; 659 660 pwm6: pwm@32d0000 { 661 compatible = "nvidia,tegra194-pwm", 662 "nvidia,tegra186-pwm"; 663 reg = <0x32d0000 0x10000>; 664 clocks = <&bpmp TEGRA194_CLK_PWM6>; 665 clock-names = "pwm"; 666 resets = <&bpmp TEGRA194_RESET_PWM6>; 667 reset-names = "pwm"; 668 status = "disabled"; 669 #pwm-cells = <2>; 670 }; 671 672 pwm7: pwm@32e0000 { 673 compatible = "nvidia,tegra194-pwm", 674 "nvidia,tegra186-pwm"; 675 reg = <0x32e0000 0x10000>; 676 clocks = <&bpmp TEGRA194_CLK_PWM7>; 677 clock-names = "pwm"; 678 resets = <&bpmp TEGRA194_RESET_PWM7>; 679 reset-names = "pwm"; 680 status = "disabled"; 681 #pwm-cells = <2>; 682 }; 683 684 pwm8: pwm@32f0000 { 685 compatible = "nvidia,tegra194-pwm", 686 "nvidia,tegra186-pwm"; 687 reg = <0x32f0000 0x10000>; 688 clocks = <&bpmp TEGRA194_CLK_PWM8>; 689 clock-names = "pwm"; 690 resets = <&bpmp TEGRA194_RESET_PWM8>; 691 reset-names = "pwm"; 692 status = "disabled"; 693 #pwm-cells = <2>; 694 }; 695 696 sdmmc1: mmc@3400000 { 697 compatible = "nvidia,tegra194-sdhci"; 698 reg = <0x03400000 0x10000>; 699 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 701 clock-names = "sdhci"; 702 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 703 reset-names = "sdhci"; 704 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 705 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 706 interconnect-names = "dma-mem", "write"; 707 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 708 <0x07>; 709 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 710 <0x07>; 711 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 712 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 713 <0x07>; 714 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 715 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 716 nvidia,default-tap = <0x9>; 717 nvidia,default-trim = <0x5>; 718 status = "disabled"; 719 }; 720 721 sdmmc3: mmc@3440000 { 722 compatible = "nvidia,tegra194-sdhci"; 723 reg = <0x03440000 0x10000>; 724 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 726 clock-names = "sdhci"; 727 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 728 reset-names = "sdhci"; 729 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 730 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 731 interconnect-names = "dma-mem", "write"; 732 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 733 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 734 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 735 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 736 <0x07>; 737 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 738 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 739 <0x07>; 740 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 741 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 742 nvidia,default-tap = <0x9>; 743 nvidia,default-trim = <0x5>; 744 status = "disabled"; 745 }; 746 747 sdmmc4: mmc@3460000 { 748 compatible = "nvidia,tegra194-sdhci"; 749 reg = <0x03460000 0x10000>; 750 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 752 clock-names = "sdhci"; 753 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 754 <&bpmp TEGRA194_CLK_PLLC4>; 755 assigned-clock-parents = 756 <&bpmp TEGRA194_CLK_PLLC4>; 757 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 758 reset-names = "sdhci"; 759 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 760 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 761 interconnect-names = "dma-mem", "write"; 762 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 763 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 764 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 765 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 766 <0x0a>; 767 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 768 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 769 <0x0a>; 770 nvidia,default-tap = <0x8>; 771 nvidia,default-trim = <0x14>; 772 nvidia,dqs-trim = <40>; 773 supports-cqe; 774 status = "disabled"; 775 }; 776 777 hda@3510000 { 778 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 779 reg = <0x3510000 0x10000>; 780 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&bpmp TEGRA194_CLK_HDA>, 782 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 783 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 784 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 785 resets = <&bpmp TEGRA194_RESET_HDA>, 786 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 787 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 788 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 789 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 790 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 791 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 792 interconnect-names = "dma-mem", "write"; 793 status = "disabled"; 794 }; 795 796 xusb_padctl: padctl@3520000 { 797 compatible = "nvidia,tegra194-xusb-padctl"; 798 reg = <0x03520000 0x1000>, 799 <0x03540000 0x1000>; 800 reg-names = "padctl", "ao"; 801 802 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 803 reset-names = "padctl"; 804 805 status = "disabled"; 806 807 pads { 808 usb2 { 809 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 810 clock-names = "trk"; 811 812 lanes { 813 usb2-0 { 814 nvidia,function = "xusb"; 815 status = "disabled"; 816 #phy-cells = <0>; 817 }; 818 819 usb2-1 { 820 nvidia,function = "xusb"; 821 status = "disabled"; 822 #phy-cells = <0>; 823 }; 824 825 usb2-2 { 826 nvidia,function = "xusb"; 827 status = "disabled"; 828 #phy-cells = <0>; 829 }; 830 831 usb2-3 { 832 nvidia,function = "xusb"; 833 status = "disabled"; 834 #phy-cells = <0>; 835 }; 836 }; 837 }; 838 839 usb3 { 840 lanes { 841 usb3-0 { 842 nvidia,function = "xusb"; 843 status = "disabled"; 844 #phy-cells = <0>; 845 }; 846 847 usb3-1 { 848 nvidia,function = "xusb"; 849 status = "disabled"; 850 #phy-cells = <0>; 851 }; 852 853 usb3-2 { 854 nvidia,function = "xusb"; 855 status = "disabled"; 856 #phy-cells = <0>; 857 }; 858 859 usb3-3 { 860 nvidia,function = "xusb"; 861 status = "disabled"; 862 #phy-cells = <0>; 863 }; 864 }; 865 }; 866 }; 867 868 ports { 869 usb2-0 { 870 status = "disabled"; 871 }; 872 873 usb2-1 { 874 status = "disabled"; 875 }; 876 877 usb2-2 { 878 status = "disabled"; 879 }; 880 881 usb2-3 { 882 status = "disabled"; 883 }; 884 885 usb3-0 { 886 status = "disabled"; 887 }; 888 889 usb3-1 { 890 status = "disabled"; 891 }; 892 893 usb3-2 { 894 status = "disabled"; 895 }; 896 897 usb3-3 { 898 status = "disabled"; 899 }; 900 }; 901 }; 902 903 usb@3550000 { 904 compatible = "nvidia,tegra194-xudc"; 905 reg = <0x03550000 0x8000>, 906 <0x03558000 0x1000>; 907 reg-names = "base", "fpci"; 908 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 910 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 911 <&bpmp TEGRA194_CLK_XUSB_SS>, 912 <&bpmp TEGRA194_CLK_XUSB_FS>; 913 clock-names = "dev", "ss", "ss_src", "fs_src"; 914 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 915 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 916 power-domain-names = "dev", "ss"; 917 nvidia,xusb-padctl = <&xusb_padctl>; 918 status = "disabled"; 919 }; 920 921 usb@3610000 { 922 compatible = "nvidia,tegra194-xusb"; 923 reg = <0x03610000 0x40000>, 924 <0x03600000 0x10000>; 925 reg-names = "hcd", "fpci"; 926 927 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 929 930 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 931 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 932 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 933 <&bpmp TEGRA194_CLK_XUSB_SS>, 934 <&bpmp TEGRA194_CLK_CLK_M>, 935 <&bpmp TEGRA194_CLK_XUSB_FS>, 936 <&bpmp TEGRA194_CLK_UTMIPLL>, 937 <&bpmp TEGRA194_CLK_CLK_M>, 938 <&bpmp TEGRA194_CLK_PLLE>; 939 clock-names = "xusb_host", "xusb_falcon_src", 940 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 941 "xusb_fs_src", "pll_u_480m", "clk_m", 942 "pll_e"; 943 944 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 945 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 946 power-domain-names = "xusb_host", "xusb_ss"; 947 948 nvidia,xusb-padctl = <&xusb_padctl>; 949 status = "disabled"; 950 }; 951 952 fuse@3820000 { 953 compatible = "nvidia,tegra194-efuse"; 954 reg = <0x03820000 0x10000>; 955 clocks = <&bpmp TEGRA194_CLK_FUSE>; 956 clock-names = "fuse"; 957 }; 958 959 gic: interrupt-controller@3881000 { 960 compatible = "arm,gic-400"; 961 #interrupt-cells = <3>; 962 interrupt-controller; 963 reg = <0x03881000 0x1000>, 964 <0x03882000 0x2000>, 965 <0x03884000 0x2000>, 966 <0x03886000 0x2000>; 967 interrupts = <GIC_PPI 9 968 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 969 interrupt-parent = <&gic>; 970 }; 971 972 cec@3960000 { 973 compatible = "nvidia,tegra194-cec"; 974 reg = <0x03960000 0x10000>; 975 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&bpmp TEGRA194_CLK_CEC>; 977 clock-names = "cec"; 978 status = "disabled"; 979 }; 980 981 hsp_top0: hsp@3c00000 { 982 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 983 reg = <0x03c00000 0xa0000>; 984 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 994 "shared3", "shared4", "shared5", "shared6", 995 "shared7"; 996 #mbox-cells = <2>; 997 }; 998 999 p2u_hsio_0: phy@3e10000 { 1000 compatible = "nvidia,tegra194-p2u"; 1001 reg = <0x03e10000 0x10000>; 1002 reg-names = "ctl"; 1003 1004 #phy-cells = <0>; 1005 }; 1006 1007 p2u_hsio_1: phy@3e20000 { 1008 compatible = "nvidia,tegra194-p2u"; 1009 reg = <0x03e20000 0x10000>; 1010 reg-names = "ctl"; 1011 1012 #phy-cells = <0>; 1013 }; 1014 1015 p2u_hsio_2: phy@3e30000 { 1016 compatible = "nvidia,tegra194-p2u"; 1017 reg = <0x03e30000 0x10000>; 1018 reg-names = "ctl"; 1019 1020 #phy-cells = <0>; 1021 }; 1022 1023 p2u_hsio_3: phy@3e40000 { 1024 compatible = "nvidia,tegra194-p2u"; 1025 reg = <0x03e40000 0x10000>; 1026 reg-names = "ctl"; 1027 1028 #phy-cells = <0>; 1029 }; 1030 1031 p2u_hsio_4: phy@3e50000 { 1032 compatible = "nvidia,tegra194-p2u"; 1033 reg = <0x03e50000 0x10000>; 1034 reg-names = "ctl"; 1035 1036 #phy-cells = <0>; 1037 }; 1038 1039 p2u_hsio_5: phy@3e60000 { 1040 compatible = "nvidia,tegra194-p2u"; 1041 reg = <0x03e60000 0x10000>; 1042 reg-names = "ctl"; 1043 1044 #phy-cells = <0>; 1045 }; 1046 1047 p2u_hsio_6: phy@3e70000 { 1048 compatible = "nvidia,tegra194-p2u"; 1049 reg = <0x03e70000 0x10000>; 1050 reg-names = "ctl"; 1051 1052 #phy-cells = <0>; 1053 }; 1054 1055 p2u_hsio_7: phy@3e80000 { 1056 compatible = "nvidia,tegra194-p2u"; 1057 reg = <0x03e80000 0x10000>; 1058 reg-names = "ctl"; 1059 1060 #phy-cells = <0>; 1061 }; 1062 1063 p2u_hsio_8: phy@3e90000 { 1064 compatible = "nvidia,tegra194-p2u"; 1065 reg = <0x03e90000 0x10000>; 1066 reg-names = "ctl"; 1067 1068 #phy-cells = <0>; 1069 }; 1070 1071 p2u_hsio_9: phy@3ea0000 { 1072 compatible = "nvidia,tegra194-p2u"; 1073 reg = <0x03ea0000 0x10000>; 1074 reg-names = "ctl"; 1075 1076 #phy-cells = <0>; 1077 }; 1078 1079 p2u_nvhs_0: phy@3eb0000 { 1080 compatible = "nvidia,tegra194-p2u"; 1081 reg = <0x03eb0000 0x10000>; 1082 reg-names = "ctl"; 1083 1084 #phy-cells = <0>; 1085 }; 1086 1087 p2u_nvhs_1: phy@3ec0000 { 1088 compatible = "nvidia,tegra194-p2u"; 1089 reg = <0x03ec0000 0x10000>; 1090 reg-names = "ctl"; 1091 1092 #phy-cells = <0>; 1093 }; 1094 1095 p2u_nvhs_2: phy@3ed0000 { 1096 compatible = "nvidia,tegra194-p2u"; 1097 reg = <0x03ed0000 0x10000>; 1098 reg-names = "ctl"; 1099 1100 #phy-cells = <0>; 1101 }; 1102 1103 p2u_nvhs_3: phy@3ee0000 { 1104 compatible = "nvidia,tegra194-p2u"; 1105 reg = <0x03ee0000 0x10000>; 1106 reg-names = "ctl"; 1107 1108 #phy-cells = <0>; 1109 }; 1110 1111 p2u_nvhs_4: phy@3ef0000 { 1112 compatible = "nvidia,tegra194-p2u"; 1113 reg = <0x03ef0000 0x10000>; 1114 reg-names = "ctl"; 1115 1116 #phy-cells = <0>; 1117 }; 1118 1119 p2u_nvhs_5: phy@3f00000 { 1120 compatible = "nvidia,tegra194-p2u"; 1121 reg = <0x03f00000 0x10000>; 1122 reg-names = "ctl"; 1123 1124 #phy-cells = <0>; 1125 }; 1126 1127 p2u_nvhs_6: phy@3f10000 { 1128 compatible = "nvidia,tegra194-p2u"; 1129 reg = <0x03f10000 0x10000>; 1130 reg-names = "ctl"; 1131 1132 #phy-cells = <0>; 1133 }; 1134 1135 p2u_nvhs_7: phy@3f20000 { 1136 compatible = "nvidia,tegra194-p2u"; 1137 reg = <0x03f20000 0x10000>; 1138 reg-names = "ctl"; 1139 1140 #phy-cells = <0>; 1141 }; 1142 1143 p2u_hsio_10: phy@3f30000 { 1144 compatible = "nvidia,tegra194-p2u"; 1145 reg = <0x03f30000 0x10000>; 1146 reg-names = "ctl"; 1147 1148 #phy-cells = <0>; 1149 }; 1150 1151 p2u_hsio_11: phy@3f40000 { 1152 compatible = "nvidia,tegra194-p2u"; 1153 reg = <0x03f40000 0x10000>; 1154 reg-names = "ctl"; 1155 1156 #phy-cells = <0>; 1157 }; 1158 1159 hsp_aon: hsp@c150000 { 1160 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 1161 reg = <0x0c150000 0xa0000>; 1162 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1166 /* 1167 * Shared interrupt 0 is routed only to AON/SPE, so 1168 * we only have 4 shared interrupts for the CCPLEX. 1169 */ 1170 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1171 #mbox-cells = <2>; 1172 }; 1173 1174 gen2_i2c: i2c@c240000 { 1175 compatible = "nvidia,tegra194-i2c"; 1176 reg = <0x0c240000 0x10000>; 1177 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1181 clock-names = "div-clk"; 1182 resets = <&bpmp TEGRA194_RESET_I2C2>; 1183 reset-names = "i2c"; 1184 status = "disabled"; 1185 }; 1186 1187 gen8_i2c: i2c@c250000 { 1188 compatible = "nvidia,tegra194-i2c"; 1189 reg = <0x0c250000 0x10000>; 1190 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1194 clock-names = "div-clk"; 1195 resets = <&bpmp TEGRA194_RESET_I2C8>; 1196 reset-names = "i2c"; 1197 status = "disabled"; 1198 }; 1199 1200 uartc: serial@c280000 { 1201 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1202 reg = <0x0c280000 0x40>; 1203 reg-shift = <2>; 1204 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1206 clock-names = "serial"; 1207 resets = <&bpmp TEGRA194_RESET_UARTC>; 1208 reset-names = "serial"; 1209 status = "disabled"; 1210 }; 1211 1212 uartg: serial@c290000 { 1213 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1214 reg = <0x0c290000 0x40>; 1215 reg-shift = <2>; 1216 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1218 clock-names = "serial"; 1219 resets = <&bpmp TEGRA194_RESET_UARTG>; 1220 reset-names = "serial"; 1221 status = "disabled"; 1222 }; 1223 1224 rtc: rtc@c2a0000 { 1225 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1226 reg = <0x0c2a0000 0x10000>; 1227 interrupt-parent = <&pmc>; 1228 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1230 clock-names = "rtc"; 1231 status = "disabled"; 1232 }; 1233 1234 gpio_aon: gpio@c2f0000 { 1235 compatible = "nvidia,tegra194-gpio-aon"; 1236 reg-names = "security", "gpio"; 1237 reg = <0xc2f0000 0x1000>, 1238 <0xc2f1000 0x1000>; 1239 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1240 gpio-controller; 1241 #gpio-cells = <2>; 1242 interrupt-controller; 1243 #interrupt-cells = <2>; 1244 }; 1245 1246 pwm4: pwm@c340000 { 1247 compatible = "nvidia,tegra194-pwm", 1248 "nvidia,tegra186-pwm"; 1249 reg = <0xc340000 0x10000>; 1250 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1251 clock-names = "pwm"; 1252 resets = <&bpmp TEGRA194_RESET_PWM4>; 1253 reset-names = "pwm"; 1254 status = "disabled"; 1255 #pwm-cells = <2>; 1256 }; 1257 1258 pmc: pmc@c360000 { 1259 compatible = "nvidia,tegra194-pmc"; 1260 reg = <0x0c360000 0x10000>, 1261 <0x0c370000 0x10000>, 1262 <0x0c380000 0x10000>, 1263 <0x0c390000 0x10000>, 1264 <0x0c3a0000 0x10000>; 1265 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1266 1267 #interrupt-cells = <2>; 1268 interrupt-controller; 1269 }; 1270 1271 host1x@13e00000 { 1272 compatible = "nvidia,tegra194-host1x"; 1273 reg = <0x13e00000 0x10000>, 1274 <0x13e10000 0x10000>; 1275 reg-names = "hypervisor", "vm"; 1276 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1278 interrupt-names = "syncpt", "host1x"; 1279 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1280 clock-names = "host1x"; 1281 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1282 reset-names = "host1x"; 1283 1284 #address-cells = <1>; 1285 #size-cells = <1>; 1286 1287 ranges = <0x15000000 0x15000000 0x01000000>; 1288 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1289 interconnect-names = "dma-mem"; 1290 1291 display-hub@15200000 { 1292 compatible = "nvidia,tegra194-display"; 1293 reg = <0x15200000 0x00040000>; 1294 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1295 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1296 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1297 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1298 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1299 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1300 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1301 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1302 "wgrp3", "wgrp4", "wgrp5"; 1303 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1304 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1305 clock-names = "disp", "hub"; 1306 status = "disabled"; 1307 1308 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1309 1310 #address-cells = <1>; 1311 #size-cells = <1>; 1312 1313 ranges = <0x15200000 0x15200000 0x40000>; 1314 1315 display@15200000 { 1316 compatible = "nvidia,tegra194-dc"; 1317 reg = <0x15200000 0x10000>; 1318 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1319 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1320 clock-names = "dc"; 1321 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1322 reset-names = "dc"; 1323 1324 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1325 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1326 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1327 interconnect-names = "dma-mem", "read-1"; 1328 1329 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1330 nvidia,head = <0>; 1331 }; 1332 1333 display@15210000 { 1334 compatible = "nvidia,tegra194-dc"; 1335 reg = <0x15210000 0x10000>; 1336 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1337 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1338 clock-names = "dc"; 1339 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1340 reset-names = "dc"; 1341 1342 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1343 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1344 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1345 interconnect-names = "dma-mem", "read-1"; 1346 1347 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1348 nvidia,head = <1>; 1349 }; 1350 1351 display@15220000 { 1352 compatible = "nvidia,tegra194-dc"; 1353 reg = <0x15220000 0x10000>; 1354 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1356 clock-names = "dc"; 1357 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1358 reset-names = "dc"; 1359 1360 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1361 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1362 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1363 interconnect-names = "dma-mem", "read-1"; 1364 1365 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1366 nvidia,head = <2>; 1367 }; 1368 1369 display@15230000 { 1370 compatible = "nvidia,tegra194-dc"; 1371 reg = <0x15230000 0x10000>; 1372 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1373 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1374 clock-names = "dc"; 1375 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1376 reset-names = "dc"; 1377 1378 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1379 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1380 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1381 interconnect-names = "dma-mem", "read-1"; 1382 1383 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1384 nvidia,head = <3>; 1385 }; 1386 }; 1387 1388 vic@15340000 { 1389 compatible = "nvidia,tegra194-vic"; 1390 reg = <0x15340000 0x00040000>; 1391 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&bpmp TEGRA194_CLK_VIC>; 1393 clock-names = "vic"; 1394 resets = <&bpmp TEGRA194_RESET_VIC>; 1395 reset-names = "vic"; 1396 1397 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1398 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1399 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1400 interconnect-names = "dma-mem", "write"; 1401 }; 1402 1403 dpaux0: dpaux@155c0000 { 1404 compatible = "nvidia,tegra194-dpaux"; 1405 reg = <0x155c0000 0x10000>; 1406 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1407 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1408 <&bpmp TEGRA194_CLK_PLLDP>; 1409 clock-names = "dpaux", "parent"; 1410 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1411 reset-names = "dpaux"; 1412 status = "disabled"; 1413 1414 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1415 1416 state_dpaux0_aux: pinmux-aux { 1417 groups = "dpaux-io"; 1418 function = "aux"; 1419 }; 1420 1421 state_dpaux0_i2c: pinmux-i2c { 1422 groups = "dpaux-io"; 1423 function = "i2c"; 1424 }; 1425 1426 state_dpaux0_off: pinmux-off { 1427 groups = "dpaux-io"; 1428 function = "off"; 1429 }; 1430 1431 i2c-bus { 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 }; 1435 }; 1436 1437 dpaux1: dpaux@155d0000 { 1438 compatible = "nvidia,tegra194-dpaux"; 1439 reg = <0x155d0000 0x10000>; 1440 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1441 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1442 <&bpmp TEGRA194_CLK_PLLDP>; 1443 clock-names = "dpaux", "parent"; 1444 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1445 reset-names = "dpaux"; 1446 status = "disabled"; 1447 1448 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1449 1450 state_dpaux1_aux: pinmux-aux { 1451 groups = "dpaux-io"; 1452 function = "aux"; 1453 }; 1454 1455 state_dpaux1_i2c: pinmux-i2c { 1456 groups = "dpaux-io"; 1457 function = "i2c"; 1458 }; 1459 1460 state_dpaux1_off: pinmux-off { 1461 groups = "dpaux-io"; 1462 function = "off"; 1463 }; 1464 1465 i2c-bus { 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 }; 1469 }; 1470 1471 dpaux2: dpaux@155e0000 { 1472 compatible = "nvidia,tegra194-dpaux"; 1473 reg = <0x155e0000 0x10000>; 1474 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1475 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1476 <&bpmp TEGRA194_CLK_PLLDP>; 1477 clock-names = "dpaux", "parent"; 1478 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1479 reset-names = "dpaux"; 1480 status = "disabled"; 1481 1482 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1483 1484 state_dpaux2_aux: pinmux-aux { 1485 groups = "dpaux-io"; 1486 function = "aux"; 1487 }; 1488 1489 state_dpaux2_i2c: pinmux-i2c { 1490 groups = "dpaux-io"; 1491 function = "i2c"; 1492 }; 1493 1494 state_dpaux2_off: pinmux-off { 1495 groups = "dpaux-io"; 1496 function = "off"; 1497 }; 1498 1499 i2c-bus { 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 }; 1503 }; 1504 1505 dpaux3: dpaux@155f0000 { 1506 compatible = "nvidia,tegra194-dpaux"; 1507 reg = <0x155f0000 0x10000>; 1508 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1509 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1510 <&bpmp TEGRA194_CLK_PLLDP>; 1511 clock-names = "dpaux", "parent"; 1512 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1513 reset-names = "dpaux"; 1514 status = "disabled"; 1515 1516 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1517 1518 state_dpaux3_aux: pinmux-aux { 1519 groups = "dpaux-io"; 1520 function = "aux"; 1521 }; 1522 1523 state_dpaux3_i2c: pinmux-i2c { 1524 groups = "dpaux-io"; 1525 function = "i2c"; 1526 }; 1527 1528 state_dpaux3_off: pinmux-off { 1529 groups = "dpaux-io"; 1530 function = "off"; 1531 }; 1532 1533 i2c-bus { 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 }; 1537 }; 1538 1539 sor0: sor@15b00000 { 1540 compatible = "nvidia,tegra194-sor"; 1541 reg = <0x15b00000 0x40000>; 1542 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1544 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1545 <&bpmp TEGRA194_CLK_PLLD>, 1546 <&bpmp TEGRA194_CLK_PLLDP>, 1547 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1548 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1549 clock-names = "sor", "out", "parent", "dp", "safe", 1550 "pad"; 1551 resets = <&bpmp TEGRA194_RESET_SOR0>; 1552 reset-names = "sor"; 1553 pinctrl-0 = <&state_dpaux0_aux>; 1554 pinctrl-1 = <&state_dpaux0_i2c>; 1555 pinctrl-2 = <&state_dpaux0_off>; 1556 pinctrl-names = "aux", "i2c", "off"; 1557 status = "disabled"; 1558 1559 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1560 nvidia,interface = <0>; 1561 }; 1562 1563 sor1: sor@15b40000 { 1564 compatible = "nvidia,tegra194-sor"; 1565 reg = <0x15b40000 0x40000>; 1566 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1568 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1569 <&bpmp TEGRA194_CLK_PLLD2>, 1570 <&bpmp TEGRA194_CLK_PLLDP>, 1571 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1572 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1573 clock-names = "sor", "out", "parent", "dp", "safe", 1574 "pad"; 1575 resets = <&bpmp TEGRA194_RESET_SOR1>; 1576 reset-names = "sor"; 1577 pinctrl-0 = <&state_dpaux1_aux>; 1578 pinctrl-1 = <&state_dpaux1_i2c>; 1579 pinctrl-2 = <&state_dpaux1_off>; 1580 pinctrl-names = "aux", "i2c", "off"; 1581 status = "disabled"; 1582 1583 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1584 nvidia,interface = <1>; 1585 }; 1586 1587 sor2: sor@15b80000 { 1588 compatible = "nvidia,tegra194-sor"; 1589 reg = <0x15b80000 0x40000>; 1590 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1591 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1592 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1593 <&bpmp TEGRA194_CLK_PLLD3>, 1594 <&bpmp TEGRA194_CLK_PLLDP>, 1595 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1596 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1597 clock-names = "sor", "out", "parent", "dp", "safe", 1598 "pad"; 1599 resets = <&bpmp TEGRA194_RESET_SOR2>; 1600 reset-names = "sor"; 1601 pinctrl-0 = <&state_dpaux2_aux>; 1602 pinctrl-1 = <&state_dpaux2_i2c>; 1603 pinctrl-2 = <&state_dpaux2_off>; 1604 pinctrl-names = "aux", "i2c", "off"; 1605 status = "disabled"; 1606 1607 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1608 nvidia,interface = <2>; 1609 }; 1610 1611 sor3: sor@15bc0000 { 1612 compatible = "nvidia,tegra194-sor"; 1613 reg = <0x15bc0000 0x40000>; 1614 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1615 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1616 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1617 <&bpmp TEGRA194_CLK_PLLD4>, 1618 <&bpmp TEGRA194_CLK_PLLDP>, 1619 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1620 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1621 clock-names = "sor", "out", "parent", "dp", "safe", 1622 "pad"; 1623 resets = <&bpmp TEGRA194_RESET_SOR3>; 1624 reset-names = "sor"; 1625 pinctrl-0 = <&state_dpaux3_aux>; 1626 pinctrl-1 = <&state_dpaux3_i2c>; 1627 pinctrl-2 = <&state_dpaux3_off>; 1628 pinctrl-names = "aux", "i2c", "off"; 1629 status = "disabled"; 1630 1631 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1632 nvidia,interface = <3>; 1633 }; 1634 }; 1635 1636 gpu@17000000 { 1637 compatible = "nvidia,gv11b"; 1638 reg = <0x17000000 0x1000000>, 1639 <0x18000000 0x1000000>; 1640 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1642 interrupt-names = "stall", "nonstall"; 1643 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 1644 <&bpmp TEGRA194_CLK_GPU_PWR>, 1645 <&bpmp TEGRA194_CLK_FUSE>; 1646 clock-names = "gpu", "pwr", "fuse"; 1647 resets = <&bpmp TEGRA194_RESET_GPU>; 1648 reset-names = "gpu"; 1649 dma-coherent; 1650 1651 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 1652 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 1653 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 1654 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 1655 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 1656 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 1657 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 1658 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 1659 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 1660 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 1661 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 1662 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 1663 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 1664 interconnect-names = "dma-mem", "read-0-hp", "write-0", 1665 "read-1", "read-1-hp", "write-1", 1666 "read-2", "read-2-hp", "write-2", 1667 "read-3", "read-3-hp", "write-3"; 1668 }; 1669 }; 1670 1671 pcie@14100000 { 1672 compatible = "nvidia,tegra194-pcie"; 1673 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1674 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1675 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1676 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1677 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1678 reg-names = "appl", "config", "atu_dma", "dbi"; 1679 1680 status = "disabled"; 1681 1682 #address-cells = <3>; 1683 #size-cells = <2>; 1684 device_type = "pci"; 1685 num-lanes = <1>; 1686 num-viewport = <8>; 1687 linux,pci-domain = <1>; 1688 1689 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1690 clock-names = "core"; 1691 1692 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1693 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1694 reset-names = "apb", "core"; 1695 1696 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1697 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1698 interrupt-names = "intr", "msi"; 1699 1700 #interrupt-cells = <1>; 1701 interrupt-map-mask = <0 0 0 0>; 1702 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1703 1704 nvidia,bpmp = <&bpmp 1>; 1705 1706 nvidia,aspm-cmrt-us = <60>; 1707 nvidia,aspm-pwr-on-t-us = <20>; 1708 nvidia,aspm-l0s-entrance-latency-us = <3>; 1709 1710 bus-range = <0x0 0xff>; 1711 1712 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1713 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1714 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1715 1716 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1717 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1718 interconnect-names = "read", "write"; 1719 }; 1720 1721 pcie@14120000 { 1722 compatible = "nvidia,tegra194-pcie"; 1723 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1724 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1725 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1726 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1727 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1728 reg-names = "appl", "config", "atu_dma", "dbi"; 1729 1730 status = "disabled"; 1731 1732 #address-cells = <3>; 1733 #size-cells = <2>; 1734 device_type = "pci"; 1735 num-lanes = <1>; 1736 num-viewport = <8>; 1737 linux,pci-domain = <2>; 1738 1739 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1740 clock-names = "core"; 1741 1742 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1743 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1744 reset-names = "apb", "core"; 1745 1746 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1747 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1748 interrupt-names = "intr", "msi"; 1749 1750 #interrupt-cells = <1>; 1751 interrupt-map-mask = <0 0 0 0>; 1752 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1753 1754 nvidia,bpmp = <&bpmp 2>; 1755 1756 nvidia,aspm-cmrt-us = <60>; 1757 nvidia,aspm-pwr-on-t-us = <20>; 1758 nvidia,aspm-l0s-entrance-latency-us = <3>; 1759 1760 bus-range = <0x0 0xff>; 1761 1762 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1763 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 1764 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1765 1766 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1767 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1768 interconnect-names = "read", "write"; 1769 }; 1770 1771 pcie@14140000 { 1772 compatible = "nvidia,tegra194-pcie"; 1773 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1774 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1775 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1776 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1777 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1778 reg-names = "appl", "config", "atu_dma", "dbi"; 1779 1780 status = "disabled"; 1781 1782 #address-cells = <3>; 1783 #size-cells = <2>; 1784 device_type = "pci"; 1785 num-lanes = <1>; 1786 num-viewport = <8>; 1787 linux,pci-domain = <3>; 1788 1789 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1790 clock-names = "core"; 1791 1792 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1793 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1794 reset-names = "apb", "core"; 1795 1796 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1797 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1798 interrupt-names = "intr", "msi"; 1799 1800 #interrupt-cells = <1>; 1801 interrupt-map-mask = <0 0 0 0>; 1802 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1803 1804 nvidia,bpmp = <&bpmp 3>; 1805 1806 nvidia,aspm-cmrt-us = <60>; 1807 nvidia,aspm-pwr-on-t-us = <20>; 1808 nvidia,aspm-l0s-entrance-latency-us = <3>; 1809 1810 bus-range = <0x0 0xff>; 1811 1812 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 1813 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 1814 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1815 1816 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1817 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1818 interconnect-names = "read", "write"; 1819 }; 1820 1821 pcie@14160000 { 1822 compatible = "nvidia,tegra194-pcie"; 1823 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1824 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1825 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1826 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1827 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1828 reg-names = "appl", "config", "atu_dma", "dbi"; 1829 1830 status = "disabled"; 1831 1832 #address-cells = <3>; 1833 #size-cells = <2>; 1834 device_type = "pci"; 1835 num-lanes = <4>; 1836 num-viewport = <8>; 1837 linux,pci-domain = <4>; 1838 1839 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1840 clock-names = "core"; 1841 1842 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1843 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1844 reset-names = "apb", "core"; 1845 1846 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1847 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1848 interrupt-names = "intr", "msi"; 1849 1850 #interrupt-cells = <1>; 1851 interrupt-map-mask = <0 0 0 0>; 1852 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1853 1854 nvidia,bpmp = <&bpmp 4>; 1855 1856 nvidia,aspm-cmrt-us = <60>; 1857 nvidia,aspm-pwr-on-t-us = <20>; 1858 nvidia,aspm-l0s-entrance-latency-us = <3>; 1859 1860 bus-range = <0x0 0xff>; 1861 1862 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1863 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1864 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1865 1866 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1867 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1868 interconnect-names = "read", "write"; 1869 }; 1870 1871 pcie@14180000 { 1872 compatible = "nvidia,tegra194-pcie"; 1873 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1874 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1875 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1876 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1877 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1878 reg-names = "appl", "config", "atu_dma", "dbi"; 1879 1880 status = "disabled"; 1881 1882 #address-cells = <3>; 1883 #size-cells = <2>; 1884 device_type = "pci"; 1885 num-lanes = <8>; 1886 num-viewport = <8>; 1887 linux,pci-domain = <0>; 1888 1889 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1890 clock-names = "core"; 1891 1892 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1893 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1894 reset-names = "apb", "core"; 1895 1896 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1897 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1898 interrupt-names = "intr", "msi"; 1899 1900 #interrupt-cells = <1>; 1901 interrupt-map-mask = <0 0 0 0>; 1902 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1903 1904 nvidia,bpmp = <&bpmp 0>; 1905 1906 nvidia,aspm-cmrt-us = <60>; 1907 nvidia,aspm-pwr-on-t-us = <20>; 1908 nvidia,aspm-l0s-entrance-latency-us = <3>; 1909 1910 bus-range = <0x0 0xff>; 1911 1912 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1913 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1914 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1915 1916 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1917 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1918 interconnect-names = "read", "write"; 1919 }; 1920 1921 pcie@141a0000 { 1922 compatible = "nvidia,tegra194-pcie"; 1923 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1924 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1925 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1926 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1927 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1928 reg-names = "appl", "config", "atu_dma", "dbi"; 1929 1930 status = "disabled"; 1931 1932 #address-cells = <3>; 1933 #size-cells = <2>; 1934 device_type = "pci"; 1935 num-lanes = <8>; 1936 num-viewport = <8>; 1937 linux,pci-domain = <5>; 1938 1939 pinctrl-names = "default"; 1940 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1941 1942 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1943 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1944 clock-names = "core", "core_m"; 1945 1946 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1947 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1948 reset-names = "apb", "core"; 1949 1950 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1951 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1952 interrupt-names = "intr", "msi"; 1953 1954 nvidia,bpmp = <&bpmp 5>; 1955 1956 #interrupt-cells = <1>; 1957 interrupt-map-mask = <0 0 0 0>; 1958 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1959 1960 nvidia,aspm-cmrt-us = <60>; 1961 nvidia,aspm-pwr-on-t-us = <20>; 1962 nvidia,aspm-l0s-entrance-latency-us = <3>; 1963 1964 bus-range = <0x0 0xff>; 1965 1966 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 1967 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 1968 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1969 1970 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1971 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1972 interconnect-names = "read", "write"; 1973 }; 1974 1975 pcie_ep@14160000 { 1976 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1977 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1978 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1979 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1980 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1981 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1982 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1983 1984 status = "disabled"; 1985 1986 num-lanes = <4>; 1987 num-ib-windows = <2>; 1988 num-ob-windows = <8>; 1989 1990 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1991 clock-names = "core"; 1992 1993 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1994 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1995 reset-names = "apb", "core"; 1996 1997 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1998 interrupt-names = "intr"; 1999 2000 nvidia,bpmp = <&bpmp 4>; 2001 2002 nvidia,aspm-cmrt-us = <60>; 2003 nvidia,aspm-pwr-on-t-us = <20>; 2004 nvidia,aspm-l0s-entrance-latency-us = <3>; 2005 }; 2006 2007 pcie_ep@14180000 { 2008 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 2009 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2010 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2011 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2012 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2013 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2014 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2015 2016 status = "disabled"; 2017 2018 num-lanes = <8>; 2019 num-ib-windows = <2>; 2020 num-ob-windows = <8>; 2021 2022 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2023 clock-names = "core"; 2024 2025 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2026 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2027 reset-names = "apb", "core"; 2028 2029 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2030 interrupt-names = "intr"; 2031 2032 nvidia,bpmp = <&bpmp 0>; 2033 2034 nvidia,aspm-cmrt-us = <60>; 2035 nvidia,aspm-pwr-on-t-us = <20>; 2036 nvidia,aspm-l0s-entrance-latency-us = <3>; 2037 }; 2038 2039 pcie_ep@141a0000 { 2040 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 2041 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2042 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2043 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2044 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2045 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2046 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2047 2048 status = "disabled"; 2049 2050 num-lanes = <8>; 2051 num-ib-windows = <2>; 2052 num-ob-windows = <8>; 2053 2054 pinctrl-names = "default"; 2055 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2056 2057 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2058 clock-names = "core"; 2059 2060 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2061 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2062 reset-names = "apb", "core"; 2063 2064 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2065 interrupt-names = "intr"; 2066 2067 nvidia,bpmp = <&bpmp 5>; 2068 2069 nvidia,aspm-cmrt-us = <60>; 2070 nvidia,aspm-pwr-on-t-us = <20>; 2071 nvidia,aspm-l0s-entrance-latency-us = <3>; 2072 }; 2073 2074 sram@40000000 { 2075 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2076 reg = <0x0 0x40000000 0x0 0x50000>; 2077 #address-cells = <1>; 2078 #size-cells = <1>; 2079 ranges = <0x0 0x0 0x40000000 0x50000>; 2080 2081 cpu_bpmp_tx: sram@4e000 { 2082 reg = <0x4e000 0x1000>; 2083 label = "cpu-bpmp-tx"; 2084 pool; 2085 }; 2086 2087 cpu_bpmp_rx: sram@4f000 { 2088 reg = <0x4f000 0x1000>; 2089 label = "cpu-bpmp-rx"; 2090 pool; 2091 }; 2092 }; 2093 2094 bpmp: bpmp { 2095 compatible = "nvidia,tegra186-bpmp"; 2096 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2097 TEGRA_HSP_DB_MASTER_BPMP>; 2098 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 2099 #clock-cells = <1>; 2100 #reset-cells = <1>; 2101 #power-domain-cells = <1>; 2102 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2103 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2104 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2105 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2106 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2107 2108 bpmp_i2c: i2c { 2109 compatible = "nvidia,tegra186-bpmp-i2c"; 2110 nvidia,bpmp-bus-id = <5>; 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 }; 2114 2115 bpmp_thermal: thermal { 2116 compatible = "nvidia,tegra186-bpmp-thermal"; 2117 #thermal-sensor-cells = <1>; 2118 }; 2119 }; 2120 2121 cpus { 2122 compatible = "nvidia,tegra194-ccplex"; 2123 nvidia,bpmp = <&bpmp>; 2124 #address-cells = <1>; 2125 #size-cells = <0>; 2126 2127 cpu0_0: cpu@0 { 2128 compatible = "nvidia,tegra194-carmel"; 2129 device_type = "cpu"; 2130 reg = <0x000>; 2131 enable-method = "psci"; 2132 i-cache-size = <131072>; 2133 i-cache-line-size = <64>; 2134 i-cache-sets = <512>; 2135 d-cache-size = <65536>; 2136 d-cache-line-size = <64>; 2137 d-cache-sets = <256>; 2138 next-level-cache = <&l2c_0>; 2139 }; 2140 2141 cpu0_1: cpu@1 { 2142 compatible = "nvidia,tegra194-carmel"; 2143 device_type = "cpu"; 2144 reg = <0x001>; 2145 enable-method = "psci"; 2146 i-cache-size = <131072>; 2147 i-cache-line-size = <64>; 2148 i-cache-sets = <512>; 2149 d-cache-size = <65536>; 2150 d-cache-line-size = <64>; 2151 d-cache-sets = <256>; 2152 next-level-cache = <&l2c_0>; 2153 }; 2154 2155 cpu1_0: cpu@100 { 2156 compatible = "nvidia,tegra194-carmel"; 2157 device_type = "cpu"; 2158 reg = <0x100>; 2159 enable-method = "psci"; 2160 i-cache-size = <131072>; 2161 i-cache-line-size = <64>; 2162 i-cache-sets = <512>; 2163 d-cache-size = <65536>; 2164 d-cache-line-size = <64>; 2165 d-cache-sets = <256>; 2166 next-level-cache = <&l2c_1>; 2167 }; 2168 2169 cpu1_1: cpu@101 { 2170 compatible = "nvidia,tegra194-carmel"; 2171 device_type = "cpu"; 2172 reg = <0x101>; 2173 enable-method = "psci"; 2174 i-cache-size = <131072>; 2175 i-cache-line-size = <64>; 2176 i-cache-sets = <512>; 2177 d-cache-size = <65536>; 2178 d-cache-line-size = <64>; 2179 d-cache-sets = <256>; 2180 next-level-cache = <&l2c_1>; 2181 }; 2182 2183 cpu2_0: cpu@200 { 2184 compatible = "nvidia,tegra194-carmel"; 2185 device_type = "cpu"; 2186 reg = <0x200>; 2187 enable-method = "psci"; 2188 i-cache-size = <131072>; 2189 i-cache-line-size = <64>; 2190 i-cache-sets = <512>; 2191 d-cache-size = <65536>; 2192 d-cache-line-size = <64>; 2193 d-cache-sets = <256>; 2194 next-level-cache = <&l2c_2>; 2195 }; 2196 2197 cpu2_1: cpu@201 { 2198 compatible = "nvidia,tegra194-carmel"; 2199 device_type = "cpu"; 2200 reg = <0x201>; 2201 enable-method = "psci"; 2202 i-cache-size = <131072>; 2203 i-cache-line-size = <64>; 2204 i-cache-sets = <512>; 2205 d-cache-size = <65536>; 2206 d-cache-line-size = <64>; 2207 d-cache-sets = <256>; 2208 next-level-cache = <&l2c_2>; 2209 }; 2210 2211 cpu3_0: cpu@300 { 2212 compatible = "nvidia,tegra194-carmel"; 2213 device_type = "cpu"; 2214 reg = <0x300>; 2215 enable-method = "psci"; 2216 i-cache-size = <131072>; 2217 i-cache-line-size = <64>; 2218 i-cache-sets = <512>; 2219 d-cache-size = <65536>; 2220 d-cache-line-size = <64>; 2221 d-cache-sets = <256>; 2222 next-level-cache = <&l2c_3>; 2223 }; 2224 2225 cpu3_1: cpu@301 { 2226 compatible = "nvidia,tegra194-carmel"; 2227 device_type = "cpu"; 2228 reg = <0x301>; 2229 enable-method = "psci"; 2230 i-cache-size = <131072>; 2231 i-cache-line-size = <64>; 2232 i-cache-sets = <512>; 2233 d-cache-size = <65536>; 2234 d-cache-line-size = <64>; 2235 d-cache-sets = <256>; 2236 next-level-cache = <&l2c_3>; 2237 }; 2238 2239 cpu-map { 2240 cluster0 { 2241 core0 { 2242 cpu = <&cpu0_0>; 2243 }; 2244 2245 core1 { 2246 cpu = <&cpu0_1>; 2247 }; 2248 }; 2249 2250 cluster1 { 2251 core0 { 2252 cpu = <&cpu1_0>; 2253 }; 2254 2255 core1 { 2256 cpu = <&cpu1_1>; 2257 }; 2258 }; 2259 2260 cluster2 { 2261 core0 { 2262 cpu = <&cpu2_0>; 2263 }; 2264 2265 core1 { 2266 cpu = <&cpu2_1>; 2267 }; 2268 }; 2269 2270 cluster3 { 2271 core0 { 2272 cpu = <&cpu3_0>; 2273 }; 2274 2275 core1 { 2276 cpu = <&cpu3_1>; 2277 }; 2278 }; 2279 }; 2280 2281 l2c_0: l2-cache0 { 2282 cache-size = <2097152>; 2283 cache-line-size = <64>; 2284 cache-sets = <2048>; 2285 next-level-cache = <&l3c>; 2286 }; 2287 2288 l2c_1: l2-cache1 { 2289 cache-size = <2097152>; 2290 cache-line-size = <64>; 2291 cache-sets = <2048>; 2292 next-level-cache = <&l3c>; 2293 }; 2294 2295 l2c_2: l2-cache2 { 2296 cache-size = <2097152>; 2297 cache-line-size = <64>; 2298 cache-sets = <2048>; 2299 next-level-cache = <&l3c>; 2300 }; 2301 2302 l2c_3: l2-cache3 { 2303 cache-size = <2097152>; 2304 cache-line-size = <64>; 2305 cache-sets = <2048>; 2306 next-level-cache = <&l3c>; 2307 }; 2308 2309 l3c: l3-cache { 2310 cache-size = <4194304>; 2311 cache-line-size = <64>; 2312 cache-sets = <4096>; 2313 }; 2314 }; 2315 2316 psci { 2317 compatible = "arm,psci-1.0"; 2318 status = "okay"; 2319 method = "smc"; 2320 }; 2321 2322 tcu: tcu { 2323 compatible = "nvidia,tegra194-tcu"; 2324 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2325 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2326 mbox-names = "rx", "tx"; 2327 }; 2328 2329 thermal-zones { 2330 cpu { 2331 thermal-sensors = <&{/bpmp/thermal} 2332 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2333 status = "disabled"; 2334 }; 2335 2336 gpu { 2337 thermal-sensors = <&{/bpmp/thermal} 2338 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2339 status = "disabled"; 2340 }; 2341 2342 aux { 2343 thermal-sensors = <&{/bpmp/thermal} 2344 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2345 status = "disabled"; 2346 }; 2347 2348 pllx { 2349 thermal-sensors = <&{/bpmp/thermal} 2350 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2351 status = "disabled"; 2352 }; 2353 2354 ao { 2355 thermal-sensors = <&{/bpmp/thermal} 2356 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2357 status = "disabled"; 2358 }; 2359 2360 tj { 2361 thermal-sensors = <&{/bpmp/thermal} 2362 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2363 status = "disabled"; 2364 }; 2365 }; 2366 2367 timer { 2368 compatible = "arm,armv8-timer"; 2369 interrupts = <GIC_PPI 13 2370 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2371 <GIC_PPI 14 2372 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2373 <GIC_PPI 11 2374 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2375 <GIC_PPI 10 2376 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2377 interrupt-parent = <&gic>; 2378 always-on; 2379 }; 2380}; 2381