1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 cbb@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 misc@100000 { 26 compatible = "nvidia,tegra194-misc"; 27 reg = <0x00100000 0xf000>, 28 <0x0010f000 0x1000>; 29 }; 30 31 gpio: gpio@2200000 { 32 compatible = "nvidia,tegra194-gpio"; 33 reg-names = "security", "gpio"; 34 reg = <0x2200000 0x10000>, 35 <0x2210000 0x10000>; 36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42 #interrupt-cells = <2>; 43 interrupt-controller; 44 #gpio-cells = <2>; 45 gpio-controller; 46 }; 47 48 ethernet@2490000 { 49 compatible = "nvidia,tegra194-eqos", 50 "nvidia,tegra186-eqos", 51 "snps,dwc-qos-ethernet-4.10"; 52 reg = <0x02490000 0x10000>; 53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55 <&bpmp TEGRA194_CLK_EQOS_AXI>, 56 <&bpmp TEGRA194_CLK_EQOS_RX>, 57 <&bpmp TEGRA194_CLK_EQOS_TX>, 58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA194_RESET_EQOS>; 61 reset-names = "eqos"; 62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64 interconnect-names = "dma-mem", "write"; 65 status = "disabled"; 66 67 snps,write-requests = <1>; 68 snps,read-requests = <3>; 69 snps,burst-map = <0x7>; 70 snps,txpbl = <16>; 71 snps,rxpbl = <8>; 72 }; 73 74 aconnect@2900000 { 75 compatible = "nvidia,tegra194-aconnect", 76 "nvidia,tegra210-aconnect"; 77 clocks = <&bpmp TEGRA194_CLK_APE>, 78 <&bpmp TEGRA194_CLK_APB2APE>; 79 clock-names = "ape", "apb2ape"; 80 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x02900000 0x02900000 0x200000>; 84 status = "disabled"; 85 86 dma-controller@2930000 { 87 compatible = "nvidia,tegra194-adma", 88 "nvidia,tegra186-adma"; 89 reg = <0x02930000 0x20000>; 90 interrupt-parent = <&agic>; 91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 123 #dma-cells = <1>; 124 clocks = <&bpmp TEGRA194_CLK_AHUB>; 125 clock-names = "d_audio"; 126 status = "disabled"; 127 }; 128 129 agic: interrupt-controller@2a40000 { 130 compatible = "nvidia,tegra194-agic", 131 "nvidia,tegra210-agic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x02a41000 0x1000>, 135 <0x02a42000 0x2000>; 136 interrupts = <GIC_SPI 145 137 (GIC_CPU_MASK_SIMPLE(4) | 138 IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA194_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 }; 144 145 pinmux: pinmux@2430000 { 146 compatible = "nvidia,tegra194-pinmux"; 147 reg = <0x2430000 0x17000 148 0xc300000 0x4000>; 149 150 status = "okay"; 151 152 pex_rst_c5_out_state: pex_rst_c5_out { 153 pex_rst { 154 nvidia,pins = "pex_l5_rst_n_pgg1"; 155 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 156 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 157 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 158 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 159 nvidia,tristate = <TEGRA_PIN_DISABLE>; 160 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 161 }; 162 }; 163 164 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 165 clkreq { 166 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 167 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 168 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 169 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 170 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 171 nvidia,tristate = <TEGRA_PIN_DISABLE>; 172 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 173 }; 174 }; 175 }; 176 177 mc: memory-controller@2c00000 { 178 compatible = "nvidia,tegra194-mc"; 179 reg = <0x02c00000 0x100000>, 180 <0x02b80000 0x040000>, 181 <0x01700000 0x100000>; 182 #interconnect-cells = <1>; 183 status = "disabled"; 184 185 #address-cells = <2>; 186 #size-cells = <2>; 187 188 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 189 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 190 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 191 192 /* 193 * Bit 39 of addresses passing through the memory 194 * controller selects the XBAR format used when memory 195 * is accessed. This is used to transparently access 196 * memory in the XBAR format used by the discrete GPU 197 * (bit 39 set) or Tegra (bit 39 clear). 198 * 199 * As a consequence, the operating system must ensure 200 * that bit 39 is never used implicitly, for example 201 * via an I/O virtual address mapping of an IOMMU. If 202 * devices require access to the XBAR switch, their 203 * drivers must set this bit explicitly. 204 * 205 * Limit the DMA range for memory clients to [38:0]. 206 */ 207 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 208 209 emc: external-memory-controller@2c60000 { 210 compatible = "nvidia,tegra194-emc"; 211 reg = <0x0 0x02c60000 0x0 0x90000>, 212 <0x0 0x01780000 0x0 0x80000>; 213 clocks = <&bpmp TEGRA194_CLK_EMC>; 214 clock-names = "emc"; 215 216 #interconnect-cells = <0>; 217 218 nvidia,bpmp = <&bpmp>; 219 }; 220 }; 221 222 uarta: serial@3100000 { 223 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 224 reg = <0x03100000 0x40>; 225 reg-shift = <2>; 226 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&bpmp TEGRA194_CLK_UARTA>; 228 clock-names = "serial"; 229 resets = <&bpmp TEGRA194_RESET_UARTA>; 230 reset-names = "serial"; 231 status = "disabled"; 232 }; 233 234 uartb: serial@3110000 { 235 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 236 reg = <0x03110000 0x40>; 237 reg-shift = <2>; 238 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&bpmp TEGRA194_CLK_UARTB>; 240 clock-names = "serial"; 241 resets = <&bpmp TEGRA194_RESET_UARTB>; 242 reset-names = "serial"; 243 status = "disabled"; 244 }; 245 246 uartd: serial@3130000 { 247 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 248 reg = <0x03130000 0x40>; 249 reg-shift = <2>; 250 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&bpmp TEGRA194_CLK_UARTD>; 252 clock-names = "serial"; 253 resets = <&bpmp TEGRA194_RESET_UARTD>; 254 reset-names = "serial"; 255 status = "disabled"; 256 }; 257 258 uarte: serial@3140000 { 259 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 260 reg = <0x03140000 0x40>; 261 reg-shift = <2>; 262 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&bpmp TEGRA194_CLK_UARTE>; 264 clock-names = "serial"; 265 resets = <&bpmp TEGRA194_RESET_UARTE>; 266 reset-names = "serial"; 267 status = "disabled"; 268 }; 269 270 uartf: serial@3150000 { 271 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 272 reg = <0x03150000 0x40>; 273 reg-shift = <2>; 274 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&bpmp TEGRA194_CLK_UARTF>; 276 clock-names = "serial"; 277 resets = <&bpmp TEGRA194_RESET_UARTF>; 278 reset-names = "serial"; 279 status = "disabled"; 280 }; 281 282 gen1_i2c: i2c@3160000 { 283 compatible = "nvidia,tegra194-i2c"; 284 reg = <0x03160000 0x10000>; 285 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 clocks = <&bpmp TEGRA194_CLK_I2C1>; 289 clock-names = "div-clk"; 290 resets = <&bpmp TEGRA194_RESET_I2C1>; 291 reset-names = "i2c"; 292 status = "disabled"; 293 }; 294 295 uarth: serial@3170000 { 296 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 297 reg = <0x03170000 0x40>; 298 reg-shift = <2>; 299 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&bpmp TEGRA194_CLK_UARTH>; 301 clock-names = "serial"; 302 resets = <&bpmp TEGRA194_RESET_UARTH>; 303 reset-names = "serial"; 304 status = "disabled"; 305 }; 306 307 cam_i2c: i2c@3180000 { 308 compatible = "nvidia,tegra194-i2c"; 309 reg = <0x03180000 0x10000>; 310 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 clocks = <&bpmp TEGRA194_CLK_I2C3>; 314 clock-names = "div-clk"; 315 resets = <&bpmp TEGRA194_RESET_I2C3>; 316 reset-names = "i2c"; 317 status = "disabled"; 318 }; 319 320 /* shares pads with dpaux1 */ 321 dp_aux_ch1_i2c: i2c@3190000 { 322 compatible = "nvidia,tegra194-i2c"; 323 reg = <0x03190000 0x10000>; 324 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 clocks = <&bpmp TEGRA194_CLK_I2C4>; 328 clock-names = "div-clk"; 329 resets = <&bpmp TEGRA194_RESET_I2C4>; 330 reset-names = "i2c"; 331 status = "disabled"; 332 }; 333 334 /* shares pads with dpaux0 */ 335 dp_aux_ch0_i2c: i2c@31b0000 { 336 compatible = "nvidia,tegra194-i2c"; 337 reg = <0x031b0000 0x10000>; 338 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 clocks = <&bpmp TEGRA194_CLK_I2C6>; 342 clock-names = "div-clk"; 343 resets = <&bpmp TEGRA194_RESET_I2C6>; 344 reset-names = "i2c"; 345 status = "disabled"; 346 }; 347 348 gen7_i2c: i2c@31c0000 { 349 compatible = "nvidia,tegra194-i2c"; 350 reg = <0x031c0000 0x10000>; 351 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 clocks = <&bpmp TEGRA194_CLK_I2C7>; 355 clock-names = "div-clk"; 356 resets = <&bpmp TEGRA194_RESET_I2C7>; 357 reset-names = "i2c"; 358 status = "disabled"; 359 }; 360 361 gen9_i2c: i2c@31e0000 { 362 compatible = "nvidia,tegra194-i2c"; 363 reg = <0x031e0000 0x10000>; 364 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 clocks = <&bpmp TEGRA194_CLK_I2C9>; 368 clock-names = "div-clk"; 369 resets = <&bpmp TEGRA194_RESET_I2C9>; 370 reset-names = "i2c"; 371 status = "disabled"; 372 }; 373 374 pwm1: pwm@3280000 { 375 compatible = "nvidia,tegra194-pwm", 376 "nvidia,tegra186-pwm"; 377 reg = <0x3280000 0x10000>; 378 clocks = <&bpmp TEGRA194_CLK_PWM1>; 379 clock-names = "pwm"; 380 resets = <&bpmp TEGRA194_RESET_PWM1>; 381 reset-names = "pwm"; 382 status = "disabled"; 383 #pwm-cells = <2>; 384 }; 385 386 pwm2: pwm@3290000 { 387 compatible = "nvidia,tegra194-pwm", 388 "nvidia,tegra186-pwm"; 389 reg = <0x3290000 0x10000>; 390 clocks = <&bpmp TEGRA194_CLK_PWM2>; 391 clock-names = "pwm"; 392 resets = <&bpmp TEGRA194_RESET_PWM2>; 393 reset-names = "pwm"; 394 status = "disabled"; 395 #pwm-cells = <2>; 396 }; 397 398 pwm3: pwm@32a0000 { 399 compatible = "nvidia,tegra194-pwm", 400 "nvidia,tegra186-pwm"; 401 reg = <0x32a0000 0x10000>; 402 clocks = <&bpmp TEGRA194_CLK_PWM3>; 403 clock-names = "pwm"; 404 resets = <&bpmp TEGRA194_RESET_PWM3>; 405 reset-names = "pwm"; 406 status = "disabled"; 407 #pwm-cells = <2>; 408 }; 409 410 pwm5: pwm@32c0000 { 411 compatible = "nvidia,tegra194-pwm", 412 "nvidia,tegra186-pwm"; 413 reg = <0x32c0000 0x10000>; 414 clocks = <&bpmp TEGRA194_CLK_PWM5>; 415 clock-names = "pwm"; 416 resets = <&bpmp TEGRA194_RESET_PWM5>; 417 reset-names = "pwm"; 418 status = "disabled"; 419 #pwm-cells = <2>; 420 }; 421 422 pwm6: pwm@32d0000 { 423 compatible = "nvidia,tegra194-pwm", 424 "nvidia,tegra186-pwm"; 425 reg = <0x32d0000 0x10000>; 426 clocks = <&bpmp TEGRA194_CLK_PWM6>; 427 clock-names = "pwm"; 428 resets = <&bpmp TEGRA194_RESET_PWM6>; 429 reset-names = "pwm"; 430 status = "disabled"; 431 #pwm-cells = <2>; 432 }; 433 434 pwm7: pwm@32e0000 { 435 compatible = "nvidia,tegra194-pwm", 436 "nvidia,tegra186-pwm"; 437 reg = <0x32e0000 0x10000>; 438 clocks = <&bpmp TEGRA194_CLK_PWM7>; 439 clock-names = "pwm"; 440 resets = <&bpmp TEGRA194_RESET_PWM7>; 441 reset-names = "pwm"; 442 status = "disabled"; 443 #pwm-cells = <2>; 444 }; 445 446 pwm8: pwm@32f0000 { 447 compatible = "nvidia,tegra194-pwm", 448 "nvidia,tegra186-pwm"; 449 reg = <0x32f0000 0x10000>; 450 clocks = <&bpmp TEGRA194_CLK_PWM8>; 451 clock-names = "pwm"; 452 resets = <&bpmp TEGRA194_RESET_PWM8>; 453 reset-names = "pwm"; 454 status = "disabled"; 455 #pwm-cells = <2>; 456 }; 457 458 sdmmc1: sdhci@3400000 { 459 compatible = "nvidia,tegra194-sdhci"; 460 reg = <0x03400000 0x10000>; 461 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 463 clock-names = "sdhci"; 464 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 465 reset-names = "sdhci"; 466 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 467 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 468 interconnect-names = "dma-mem", "write"; 469 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 470 <0x07>; 471 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 472 <0x07>; 473 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 474 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 475 <0x07>; 476 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 477 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 478 nvidia,default-tap = <0x9>; 479 nvidia,default-trim = <0x5>; 480 status = "disabled"; 481 }; 482 483 sdmmc3: sdhci@3440000 { 484 compatible = "nvidia,tegra194-sdhci"; 485 reg = <0x03440000 0x10000>; 486 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 488 clock-names = "sdhci"; 489 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 490 reset-names = "sdhci"; 491 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 492 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 493 interconnect-names = "dma-mem", "write"; 494 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 495 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 496 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 497 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 498 <0x07>; 499 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 500 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 501 <0x07>; 502 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 503 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 504 nvidia,default-tap = <0x9>; 505 nvidia,default-trim = <0x5>; 506 status = "disabled"; 507 }; 508 509 sdmmc4: sdhci@3460000 { 510 compatible = "nvidia,tegra194-sdhci"; 511 reg = <0x03460000 0x10000>; 512 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 514 clock-names = "sdhci"; 515 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 516 <&bpmp TEGRA194_CLK_PLLC4>; 517 assigned-clock-parents = 518 <&bpmp TEGRA194_CLK_PLLC4>; 519 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 520 reset-names = "sdhci"; 521 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 522 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 523 interconnect-names = "dma-mem", "write"; 524 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 525 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 526 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 527 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 528 <0x0a>; 529 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 530 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 531 <0x0a>; 532 nvidia,default-tap = <0x8>; 533 nvidia,default-trim = <0x14>; 534 nvidia,dqs-trim = <40>; 535 supports-cqe; 536 status = "disabled"; 537 }; 538 539 hda@3510000 { 540 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 541 reg = <0x3510000 0x10000>; 542 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&bpmp TEGRA194_CLK_HDA>, 544 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 545 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 546 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 547 resets = <&bpmp TEGRA194_RESET_HDA>, 548 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 549 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 550 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 551 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 552 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 553 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 554 interconnect-names = "dma-mem", "write"; 555 status = "disabled"; 556 }; 557 558 xusb_padctl: padctl@3520000 { 559 compatible = "nvidia,tegra194-xusb-padctl"; 560 reg = <0x03520000 0x1000>, 561 <0x03540000 0x1000>; 562 reg-names = "padctl", "ao"; 563 564 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 565 reset-names = "padctl"; 566 567 status = "disabled"; 568 569 pads { 570 usb2 { 571 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 572 clock-names = "trk"; 573 574 lanes { 575 usb2-0 { 576 nvidia,function = "xusb"; 577 status = "disabled"; 578 #phy-cells = <0>; 579 }; 580 581 usb2-1 { 582 nvidia,function = "xusb"; 583 status = "disabled"; 584 #phy-cells = <0>; 585 }; 586 587 usb2-2 { 588 nvidia,function = "xusb"; 589 status = "disabled"; 590 #phy-cells = <0>; 591 }; 592 593 usb2-3 { 594 nvidia,function = "xusb"; 595 status = "disabled"; 596 #phy-cells = <0>; 597 }; 598 }; 599 }; 600 601 usb3 { 602 lanes { 603 usb3-0 { 604 nvidia,function = "xusb"; 605 status = "disabled"; 606 #phy-cells = <0>; 607 }; 608 609 usb3-1 { 610 nvidia,function = "xusb"; 611 status = "disabled"; 612 #phy-cells = <0>; 613 }; 614 615 usb3-2 { 616 nvidia,function = "xusb"; 617 status = "disabled"; 618 #phy-cells = <0>; 619 }; 620 621 usb3-3 { 622 nvidia,function = "xusb"; 623 status = "disabled"; 624 #phy-cells = <0>; 625 }; 626 }; 627 }; 628 }; 629 630 ports { 631 usb2-0 { 632 status = "disabled"; 633 }; 634 635 usb2-1 { 636 status = "disabled"; 637 }; 638 639 usb2-2 { 640 status = "disabled"; 641 }; 642 643 usb2-3 { 644 status = "disabled"; 645 }; 646 647 usb3-0 { 648 status = "disabled"; 649 }; 650 651 usb3-1 { 652 status = "disabled"; 653 }; 654 655 usb3-2 { 656 status = "disabled"; 657 }; 658 659 usb3-3 { 660 status = "disabled"; 661 }; 662 }; 663 }; 664 665 usb@3550000 { 666 compatible = "nvidia,tegra194-xudc"; 667 reg = <0x03550000 0x8000>, 668 <0x03558000 0x1000>; 669 reg-names = "base", "fpci"; 670 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 672 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 673 <&bpmp TEGRA194_CLK_XUSB_SS>, 674 <&bpmp TEGRA194_CLK_XUSB_FS>; 675 clock-names = "dev", "ss", "ss_src", "fs_src"; 676 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 677 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 678 power-domain-names = "dev", "ss"; 679 nvidia,xusb-padctl = <&xusb_padctl>; 680 status = "disabled"; 681 }; 682 683 usb@3610000 { 684 compatible = "nvidia,tegra194-xusb"; 685 reg = <0x03610000 0x40000>, 686 <0x03600000 0x10000>; 687 reg-names = "hcd", "fpci"; 688 689 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 692 693 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 694 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 695 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 696 <&bpmp TEGRA194_CLK_XUSB_SS>, 697 <&bpmp TEGRA194_CLK_CLK_M>, 698 <&bpmp TEGRA194_CLK_XUSB_FS>, 699 <&bpmp TEGRA194_CLK_UTMIPLL>, 700 <&bpmp TEGRA194_CLK_CLK_M>, 701 <&bpmp TEGRA194_CLK_PLLE>; 702 clock-names = "xusb_host", "xusb_falcon_src", 703 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 704 "xusb_fs_src", "pll_u_480m", "clk_m", 705 "pll_e"; 706 707 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 708 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 709 power-domain-names = "xusb_host", "xusb_ss"; 710 711 nvidia,xusb-padctl = <&xusb_padctl>; 712 status = "disabled"; 713 }; 714 715 fuse@3820000 { 716 compatible = "nvidia,tegra194-efuse"; 717 reg = <0x03820000 0x10000>; 718 clocks = <&bpmp TEGRA194_CLK_FUSE>; 719 clock-names = "fuse"; 720 }; 721 722 gic: interrupt-controller@3881000 { 723 compatible = "arm,gic-400"; 724 #interrupt-cells = <3>; 725 interrupt-controller; 726 reg = <0x03881000 0x1000>, 727 <0x03882000 0x2000>, 728 <0x03884000 0x2000>, 729 <0x03886000 0x2000>; 730 interrupts = <GIC_PPI 9 731 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 732 interrupt-parent = <&gic>; 733 }; 734 735 cec@3960000 { 736 compatible = "nvidia,tegra194-cec"; 737 reg = <0x03960000 0x10000>; 738 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&bpmp TEGRA194_CLK_CEC>; 740 clock-names = "cec"; 741 status = "disabled"; 742 }; 743 744 hsp_top0: hsp@3c00000 { 745 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 746 reg = <0x03c00000 0xa0000>; 747 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 756 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 757 "shared3", "shared4", "shared5", "shared6", 758 "shared7"; 759 #mbox-cells = <2>; 760 }; 761 762 p2u_hsio_0: phy@3e10000 { 763 compatible = "nvidia,tegra194-p2u"; 764 reg = <0x03e10000 0x10000>; 765 reg-names = "ctl"; 766 767 #phy-cells = <0>; 768 }; 769 770 p2u_hsio_1: phy@3e20000 { 771 compatible = "nvidia,tegra194-p2u"; 772 reg = <0x03e20000 0x10000>; 773 reg-names = "ctl"; 774 775 #phy-cells = <0>; 776 }; 777 778 p2u_hsio_2: phy@3e30000 { 779 compatible = "nvidia,tegra194-p2u"; 780 reg = <0x03e30000 0x10000>; 781 reg-names = "ctl"; 782 783 #phy-cells = <0>; 784 }; 785 786 p2u_hsio_3: phy@3e40000 { 787 compatible = "nvidia,tegra194-p2u"; 788 reg = <0x03e40000 0x10000>; 789 reg-names = "ctl"; 790 791 #phy-cells = <0>; 792 }; 793 794 p2u_hsio_4: phy@3e50000 { 795 compatible = "nvidia,tegra194-p2u"; 796 reg = <0x03e50000 0x10000>; 797 reg-names = "ctl"; 798 799 #phy-cells = <0>; 800 }; 801 802 p2u_hsio_5: phy@3e60000 { 803 compatible = "nvidia,tegra194-p2u"; 804 reg = <0x03e60000 0x10000>; 805 reg-names = "ctl"; 806 807 #phy-cells = <0>; 808 }; 809 810 p2u_hsio_6: phy@3e70000 { 811 compatible = "nvidia,tegra194-p2u"; 812 reg = <0x03e70000 0x10000>; 813 reg-names = "ctl"; 814 815 #phy-cells = <0>; 816 }; 817 818 p2u_hsio_7: phy@3e80000 { 819 compatible = "nvidia,tegra194-p2u"; 820 reg = <0x03e80000 0x10000>; 821 reg-names = "ctl"; 822 823 #phy-cells = <0>; 824 }; 825 826 p2u_hsio_8: phy@3e90000 { 827 compatible = "nvidia,tegra194-p2u"; 828 reg = <0x03e90000 0x10000>; 829 reg-names = "ctl"; 830 831 #phy-cells = <0>; 832 }; 833 834 p2u_hsio_9: phy@3ea0000 { 835 compatible = "nvidia,tegra194-p2u"; 836 reg = <0x03ea0000 0x10000>; 837 reg-names = "ctl"; 838 839 #phy-cells = <0>; 840 }; 841 842 p2u_nvhs_0: phy@3eb0000 { 843 compatible = "nvidia,tegra194-p2u"; 844 reg = <0x03eb0000 0x10000>; 845 reg-names = "ctl"; 846 847 #phy-cells = <0>; 848 }; 849 850 p2u_nvhs_1: phy@3ec0000 { 851 compatible = "nvidia,tegra194-p2u"; 852 reg = <0x03ec0000 0x10000>; 853 reg-names = "ctl"; 854 855 #phy-cells = <0>; 856 }; 857 858 p2u_nvhs_2: phy@3ed0000 { 859 compatible = "nvidia,tegra194-p2u"; 860 reg = <0x03ed0000 0x10000>; 861 reg-names = "ctl"; 862 863 #phy-cells = <0>; 864 }; 865 866 p2u_nvhs_3: phy@3ee0000 { 867 compatible = "nvidia,tegra194-p2u"; 868 reg = <0x03ee0000 0x10000>; 869 reg-names = "ctl"; 870 871 #phy-cells = <0>; 872 }; 873 874 p2u_nvhs_4: phy@3ef0000 { 875 compatible = "nvidia,tegra194-p2u"; 876 reg = <0x03ef0000 0x10000>; 877 reg-names = "ctl"; 878 879 #phy-cells = <0>; 880 }; 881 882 p2u_nvhs_5: phy@3f00000 { 883 compatible = "nvidia,tegra194-p2u"; 884 reg = <0x03f00000 0x10000>; 885 reg-names = "ctl"; 886 887 #phy-cells = <0>; 888 }; 889 890 p2u_nvhs_6: phy@3f10000 { 891 compatible = "nvidia,tegra194-p2u"; 892 reg = <0x03f10000 0x10000>; 893 reg-names = "ctl"; 894 895 #phy-cells = <0>; 896 }; 897 898 p2u_nvhs_7: phy@3f20000 { 899 compatible = "nvidia,tegra194-p2u"; 900 reg = <0x03f20000 0x10000>; 901 reg-names = "ctl"; 902 903 #phy-cells = <0>; 904 }; 905 906 p2u_hsio_10: phy@3f30000 { 907 compatible = "nvidia,tegra194-p2u"; 908 reg = <0x03f30000 0x10000>; 909 reg-names = "ctl"; 910 911 #phy-cells = <0>; 912 }; 913 914 p2u_hsio_11: phy@3f40000 { 915 compatible = "nvidia,tegra194-p2u"; 916 reg = <0x03f40000 0x10000>; 917 reg-names = "ctl"; 918 919 #phy-cells = <0>; 920 }; 921 922 hsp_aon: hsp@c150000 { 923 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 924 reg = <0x0c150000 0xa0000>; 925 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 929 /* 930 * Shared interrupt 0 is routed only to AON/SPE, so 931 * we only have 4 shared interrupts for the CCPLEX. 932 */ 933 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 934 #mbox-cells = <2>; 935 }; 936 937 gen2_i2c: i2c@c240000 { 938 compatible = "nvidia,tegra194-i2c"; 939 reg = <0x0c240000 0x10000>; 940 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 clocks = <&bpmp TEGRA194_CLK_I2C2>; 944 clock-names = "div-clk"; 945 resets = <&bpmp TEGRA194_RESET_I2C2>; 946 reset-names = "i2c"; 947 status = "disabled"; 948 }; 949 950 gen8_i2c: i2c@c250000 { 951 compatible = "nvidia,tegra194-i2c"; 952 reg = <0x0c250000 0x10000>; 953 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 clocks = <&bpmp TEGRA194_CLK_I2C8>; 957 clock-names = "div-clk"; 958 resets = <&bpmp TEGRA194_RESET_I2C8>; 959 reset-names = "i2c"; 960 status = "disabled"; 961 }; 962 963 uartc: serial@c280000 { 964 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 965 reg = <0x0c280000 0x40>; 966 reg-shift = <2>; 967 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&bpmp TEGRA194_CLK_UARTC>; 969 clock-names = "serial"; 970 resets = <&bpmp TEGRA194_RESET_UARTC>; 971 reset-names = "serial"; 972 status = "disabled"; 973 }; 974 975 uartg: serial@c290000 { 976 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 977 reg = <0x0c290000 0x40>; 978 reg-shift = <2>; 979 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&bpmp TEGRA194_CLK_UARTG>; 981 clock-names = "serial"; 982 resets = <&bpmp TEGRA194_RESET_UARTG>; 983 reset-names = "serial"; 984 status = "disabled"; 985 }; 986 987 rtc: rtc@c2a0000 { 988 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 989 reg = <0x0c2a0000 0x10000>; 990 interrupt-parent = <&pmc>; 991 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 993 clock-names = "rtc"; 994 status = "disabled"; 995 }; 996 997 gpio_aon: gpio@c2f0000 { 998 compatible = "nvidia,tegra194-gpio-aon"; 999 reg-names = "security", "gpio"; 1000 reg = <0xc2f0000 0x1000>, 1001 <0xc2f1000 0x1000>; 1002 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1006 gpio-controller; 1007 #gpio-cells = <2>; 1008 interrupt-controller; 1009 #interrupt-cells = <2>; 1010 }; 1011 1012 pwm4: pwm@c340000 { 1013 compatible = "nvidia,tegra194-pwm", 1014 "nvidia,tegra186-pwm"; 1015 reg = <0xc340000 0x10000>; 1016 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1017 clock-names = "pwm"; 1018 resets = <&bpmp TEGRA194_RESET_PWM4>; 1019 reset-names = "pwm"; 1020 status = "disabled"; 1021 #pwm-cells = <2>; 1022 }; 1023 1024 pmc: pmc@c360000 { 1025 compatible = "nvidia,tegra194-pmc"; 1026 reg = <0x0c360000 0x10000>, 1027 <0x0c370000 0x10000>, 1028 <0x0c380000 0x10000>, 1029 <0x0c390000 0x10000>, 1030 <0x0c3a0000 0x10000>; 1031 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1032 1033 #interrupt-cells = <2>; 1034 interrupt-controller; 1035 }; 1036 1037 host1x@13e00000 { 1038 compatible = "nvidia,tegra194-host1x", "simple-bus"; 1039 reg = <0x13e00000 0x10000>, 1040 <0x13e10000 0x10000>; 1041 reg-names = "hypervisor", "vm"; 1042 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1045 clock-names = "host1x"; 1046 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1047 reset-names = "host1x"; 1048 1049 #address-cells = <1>; 1050 #size-cells = <1>; 1051 1052 ranges = <0x15000000 0x15000000 0x01000000>; 1053 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1054 interconnect-names = "dma-mem"; 1055 1056 display-hub@15200000 { 1057 compatible = "nvidia,tegra194-display", "simple-bus"; 1058 reg = <0x15200000 0x00040000>; 1059 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1060 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1061 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1062 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1063 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1064 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1065 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1066 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1067 "wgrp3", "wgrp4", "wgrp5"; 1068 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1069 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1070 clock-names = "disp", "hub"; 1071 status = "disabled"; 1072 1073 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1074 1075 #address-cells = <1>; 1076 #size-cells = <1>; 1077 1078 ranges = <0x15200000 0x15200000 0x40000>; 1079 1080 display@15200000 { 1081 compatible = "nvidia,tegra194-dc"; 1082 reg = <0x15200000 0x10000>; 1083 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1085 clock-names = "dc"; 1086 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1087 reset-names = "dc"; 1088 1089 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1090 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1091 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1092 interconnect-names = "dma-mem", "read-1"; 1093 1094 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1095 nvidia,head = <0>; 1096 }; 1097 1098 display@15210000 { 1099 compatible = "nvidia,tegra194-dc"; 1100 reg = <0x15210000 0x10000>; 1101 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1103 clock-names = "dc"; 1104 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1105 reset-names = "dc"; 1106 1107 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1108 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1109 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1110 interconnect-names = "dma-mem", "read-1"; 1111 1112 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1113 nvidia,head = <1>; 1114 }; 1115 1116 display@15220000 { 1117 compatible = "nvidia,tegra194-dc"; 1118 reg = <0x15220000 0x10000>; 1119 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1121 clock-names = "dc"; 1122 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1123 reset-names = "dc"; 1124 1125 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1126 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1127 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1128 interconnect-names = "dma-mem", "read-1"; 1129 1130 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1131 nvidia,head = <2>; 1132 }; 1133 1134 display@15230000 { 1135 compatible = "nvidia,tegra194-dc"; 1136 reg = <0x15230000 0x10000>; 1137 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1139 clock-names = "dc"; 1140 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1141 reset-names = "dc"; 1142 1143 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1144 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1145 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1146 interconnect-names = "dma-mem", "read-1"; 1147 1148 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1149 nvidia,head = <3>; 1150 }; 1151 }; 1152 1153 vic@15340000 { 1154 compatible = "nvidia,tegra194-vic"; 1155 reg = <0x15340000 0x00040000>; 1156 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&bpmp TEGRA194_CLK_VIC>; 1158 clock-names = "vic"; 1159 resets = <&bpmp TEGRA194_RESET_VIC>; 1160 reset-names = "vic"; 1161 1162 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1163 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1164 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1165 interconnect-names = "dma-mem", "write"; 1166 }; 1167 1168 dpaux0: dpaux@155c0000 { 1169 compatible = "nvidia,tegra194-dpaux"; 1170 reg = <0x155c0000 0x10000>; 1171 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1173 <&bpmp TEGRA194_CLK_PLLDP>; 1174 clock-names = "dpaux", "parent"; 1175 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1176 reset-names = "dpaux"; 1177 status = "disabled"; 1178 1179 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1180 1181 state_dpaux0_aux: pinmux-aux { 1182 groups = "dpaux-io"; 1183 function = "aux"; 1184 }; 1185 1186 state_dpaux0_i2c: pinmux-i2c { 1187 groups = "dpaux-io"; 1188 function = "i2c"; 1189 }; 1190 1191 state_dpaux0_off: pinmux-off { 1192 groups = "dpaux-io"; 1193 function = "off"; 1194 }; 1195 1196 i2c-bus { 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 }; 1200 }; 1201 1202 dpaux1: dpaux@155d0000 { 1203 compatible = "nvidia,tegra194-dpaux"; 1204 reg = <0x155d0000 0x10000>; 1205 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1207 <&bpmp TEGRA194_CLK_PLLDP>; 1208 clock-names = "dpaux", "parent"; 1209 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1210 reset-names = "dpaux"; 1211 status = "disabled"; 1212 1213 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1214 1215 state_dpaux1_aux: pinmux-aux { 1216 groups = "dpaux-io"; 1217 function = "aux"; 1218 }; 1219 1220 state_dpaux1_i2c: pinmux-i2c { 1221 groups = "dpaux-io"; 1222 function = "i2c"; 1223 }; 1224 1225 state_dpaux1_off: pinmux-off { 1226 groups = "dpaux-io"; 1227 function = "off"; 1228 }; 1229 1230 i2c-bus { 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 }; 1234 }; 1235 1236 dpaux2: dpaux@155e0000 { 1237 compatible = "nvidia,tegra194-dpaux"; 1238 reg = <0x155e0000 0x10000>; 1239 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1241 <&bpmp TEGRA194_CLK_PLLDP>; 1242 clock-names = "dpaux", "parent"; 1243 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1244 reset-names = "dpaux"; 1245 status = "disabled"; 1246 1247 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1248 1249 state_dpaux2_aux: pinmux-aux { 1250 groups = "dpaux-io"; 1251 function = "aux"; 1252 }; 1253 1254 state_dpaux2_i2c: pinmux-i2c { 1255 groups = "dpaux-io"; 1256 function = "i2c"; 1257 }; 1258 1259 state_dpaux2_off: pinmux-off { 1260 groups = "dpaux-io"; 1261 function = "off"; 1262 }; 1263 1264 i2c-bus { 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 }; 1268 }; 1269 1270 dpaux3: dpaux@155f0000 { 1271 compatible = "nvidia,tegra194-dpaux"; 1272 reg = <0x155f0000 0x10000>; 1273 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1275 <&bpmp TEGRA194_CLK_PLLDP>; 1276 clock-names = "dpaux", "parent"; 1277 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1278 reset-names = "dpaux"; 1279 status = "disabled"; 1280 1281 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1282 1283 state_dpaux3_aux: pinmux-aux { 1284 groups = "dpaux-io"; 1285 function = "aux"; 1286 }; 1287 1288 state_dpaux3_i2c: pinmux-i2c { 1289 groups = "dpaux-io"; 1290 function = "i2c"; 1291 }; 1292 1293 state_dpaux3_off: pinmux-off { 1294 groups = "dpaux-io"; 1295 function = "off"; 1296 }; 1297 1298 i2c-bus { 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 }; 1302 }; 1303 1304 sor0: sor@15b00000 { 1305 compatible = "nvidia,tegra194-sor"; 1306 reg = <0x15b00000 0x40000>; 1307 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1309 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1310 <&bpmp TEGRA194_CLK_PLLD>, 1311 <&bpmp TEGRA194_CLK_PLLDP>, 1312 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1313 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1314 clock-names = "sor", "out", "parent", "dp", "safe", 1315 "pad"; 1316 resets = <&bpmp TEGRA194_RESET_SOR0>; 1317 reset-names = "sor"; 1318 pinctrl-0 = <&state_dpaux0_aux>; 1319 pinctrl-1 = <&state_dpaux0_i2c>; 1320 pinctrl-2 = <&state_dpaux0_off>; 1321 pinctrl-names = "aux", "i2c", "off"; 1322 status = "disabled"; 1323 1324 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1325 nvidia,interface = <0>; 1326 }; 1327 1328 sor1: sor@15b40000 { 1329 compatible = "nvidia,tegra194-sor"; 1330 reg = <0x15b40000 0x40000>; 1331 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1333 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1334 <&bpmp TEGRA194_CLK_PLLD2>, 1335 <&bpmp TEGRA194_CLK_PLLDP>, 1336 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1337 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1338 clock-names = "sor", "out", "parent", "dp", "safe", 1339 "pad"; 1340 resets = <&bpmp TEGRA194_RESET_SOR1>; 1341 reset-names = "sor"; 1342 pinctrl-0 = <&state_dpaux1_aux>; 1343 pinctrl-1 = <&state_dpaux1_i2c>; 1344 pinctrl-2 = <&state_dpaux1_off>; 1345 pinctrl-names = "aux", "i2c", "off"; 1346 status = "disabled"; 1347 1348 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1349 nvidia,interface = <1>; 1350 }; 1351 1352 sor2: sor@15b80000 { 1353 compatible = "nvidia,tegra194-sor"; 1354 reg = <0x15b80000 0x40000>; 1355 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1356 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1357 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1358 <&bpmp TEGRA194_CLK_PLLD3>, 1359 <&bpmp TEGRA194_CLK_PLLDP>, 1360 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1361 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1362 clock-names = "sor", "out", "parent", "dp", "safe", 1363 "pad"; 1364 resets = <&bpmp TEGRA194_RESET_SOR2>; 1365 reset-names = "sor"; 1366 pinctrl-0 = <&state_dpaux2_aux>; 1367 pinctrl-1 = <&state_dpaux2_i2c>; 1368 pinctrl-2 = <&state_dpaux2_off>; 1369 pinctrl-names = "aux", "i2c", "off"; 1370 status = "disabled"; 1371 1372 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1373 nvidia,interface = <2>; 1374 }; 1375 1376 sor3: sor@15bc0000 { 1377 compatible = "nvidia,tegra194-sor"; 1378 reg = <0x15bc0000 0x40000>; 1379 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1380 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1381 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1382 <&bpmp TEGRA194_CLK_PLLD4>, 1383 <&bpmp TEGRA194_CLK_PLLDP>, 1384 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1385 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1386 clock-names = "sor", "out", "parent", "dp", "safe", 1387 "pad"; 1388 resets = <&bpmp TEGRA194_RESET_SOR3>; 1389 reset-names = "sor"; 1390 pinctrl-0 = <&state_dpaux3_aux>; 1391 pinctrl-1 = <&state_dpaux3_i2c>; 1392 pinctrl-2 = <&state_dpaux3_off>; 1393 pinctrl-names = "aux", "i2c", "off"; 1394 status = "disabled"; 1395 1396 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1397 nvidia,interface = <3>; 1398 }; 1399 }; 1400 }; 1401 1402 pcie@14100000 { 1403 compatible = "nvidia,tegra194-pcie"; 1404 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1405 reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 1406 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 1407 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1408 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1409 reg-names = "appl", "config", "atu_dma", "dbi"; 1410 1411 status = "disabled"; 1412 1413 #address-cells = <3>; 1414 #size-cells = <2>; 1415 device_type = "pci"; 1416 num-lanes = <1>; 1417 num-viewport = <8>; 1418 linux,pci-domain = <1>; 1419 1420 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1421 clock-names = "core"; 1422 1423 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1424 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1425 reset-names = "apb", "core"; 1426 1427 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1428 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1429 interrupt-names = "intr", "msi"; 1430 1431 #interrupt-cells = <1>; 1432 interrupt-map-mask = <0 0 0 0>; 1433 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1434 1435 nvidia,bpmp = <&bpmp 1>; 1436 1437 nvidia,aspm-cmrt-us = <60>; 1438 nvidia,aspm-pwr-on-t-us = <20>; 1439 nvidia,aspm-l0s-entrance-latency-us = <3>; 1440 1441 bus-range = <0x0 0xff>; 1442 1443 ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1444 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1445 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1446 1447 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1448 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1449 interconnect-names = "read", "write"; 1450 }; 1451 1452 pcie@14120000 { 1453 compatible = "nvidia,tegra194-pcie"; 1454 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1455 reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 1456 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 1457 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1458 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1459 reg-names = "appl", "config", "atu_dma", "dbi"; 1460 1461 status = "disabled"; 1462 1463 #address-cells = <3>; 1464 #size-cells = <2>; 1465 device_type = "pci"; 1466 num-lanes = <1>; 1467 num-viewport = <8>; 1468 linux,pci-domain = <2>; 1469 1470 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1471 clock-names = "core"; 1472 1473 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1474 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1475 reset-names = "apb", "core"; 1476 1477 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1478 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1479 interrupt-names = "intr", "msi"; 1480 1481 #interrupt-cells = <1>; 1482 interrupt-map-mask = <0 0 0 0>; 1483 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1484 1485 nvidia,bpmp = <&bpmp 2>; 1486 1487 nvidia,aspm-cmrt-us = <60>; 1488 nvidia,aspm-pwr-on-t-us = <20>; 1489 nvidia,aspm-l0s-entrance-latency-us = <3>; 1490 1491 bus-range = <0x0 0xff>; 1492 1493 ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1494 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1495 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1496 1497 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1498 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1499 interconnect-names = "read", "write"; 1500 }; 1501 1502 pcie@14140000 { 1503 compatible = "nvidia,tegra194-pcie"; 1504 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1505 reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 1506 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 1507 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1508 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1509 reg-names = "appl", "config", "atu_dma", "dbi"; 1510 1511 status = "disabled"; 1512 1513 #address-cells = <3>; 1514 #size-cells = <2>; 1515 device_type = "pci"; 1516 num-lanes = <1>; 1517 num-viewport = <8>; 1518 linux,pci-domain = <3>; 1519 1520 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1521 clock-names = "core"; 1522 1523 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1524 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1525 reset-names = "apb", "core"; 1526 1527 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1528 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1529 interrupt-names = "intr", "msi"; 1530 1531 #interrupt-cells = <1>; 1532 interrupt-map-mask = <0 0 0 0>; 1533 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1534 1535 nvidia,bpmp = <&bpmp 3>; 1536 1537 nvidia,aspm-cmrt-us = <60>; 1538 nvidia,aspm-pwr-on-t-us = <20>; 1539 nvidia,aspm-l0s-entrance-latency-us = <3>; 1540 1541 bus-range = <0x0 0xff>; 1542 1543 ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1544 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1545 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1546 1547 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1548 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1549 interconnect-names = "read", "write"; 1550 }; 1551 1552 pcie@14160000 { 1553 compatible = "nvidia,tegra194-pcie"; 1554 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1555 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 1556 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 1557 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1558 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1559 reg-names = "appl", "config", "atu_dma", "dbi"; 1560 1561 status = "disabled"; 1562 1563 #address-cells = <3>; 1564 #size-cells = <2>; 1565 device_type = "pci"; 1566 num-lanes = <4>; 1567 num-viewport = <8>; 1568 linux,pci-domain = <4>; 1569 1570 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1571 clock-names = "core"; 1572 1573 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1574 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1575 reset-names = "apb", "core"; 1576 1577 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1578 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1579 interrupt-names = "intr", "msi"; 1580 1581 #interrupt-cells = <1>; 1582 interrupt-map-mask = <0 0 0 0>; 1583 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1584 1585 nvidia,bpmp = <&bpmp 4>; 1586 1587 nvidia,aspm-cmrt-us = <60>; 1588 nvidia,aspm-pwr-on-t-us = <20>; 1589 nvidia,aspm-l0s-entrance-latency-us = <3>; 1590 1591 bus-range = <0x0 0xff>; 1592 1593 ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1594 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1595 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1596 1597 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1598 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1599 interconnect-names = "read", "write"; 1600 }; 1601 1602 pcie@14180000 { 1603 compatible = "nvidia,tegra194-pcie"; 1604 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1605 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 1606 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 1607 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1608 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1609 reg-names = "appl", "config", "atu_dma", "dbi"; 1610 1611 status = "disabled"; 1612 1613 #address-cells = <3>; 1614 #size-cells = <2>; 1615 device_type = "pci"; 1616 num-lanes = <8>; 1617 num-viewport = <8>; 1618 linux,pci-domain = <0>; 1619 1620 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1621 clock-names = "core"; 1622 1623 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1624 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1625 reset-names = "apb", "core"; 1626 1627 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1628 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1629 interrupt-names = "intr", "msi"; 1630 1631 #interrupt-cells = <1>; 1632 interrupt-map-mask = <0 0 0 0>; 1633 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1634 1635 nvidia,bpmp = <&bpmp 0>; 1636 1637 nvidia,aspm-cmrt-us = <60>; 1638 nvidia,aspm-pwr-on-t-us = <20>; 1639 nvidia,aspm-l0s-entrance-latency-us = <3>; 1640 1641 bus-range = <0x0 0xff>; 1642 1643 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1644 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1645 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1646 1647 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1648 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1649 interconnect-names = "read", "write"; 1650 }; 1651 1652 pcie@141a0000 { 1653 compatible = "nvidia,tegra194-pcie"; 1654 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1655 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 1656 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 1657 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1658 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1659 reg-names = "appl", "config", "atu_dma", "dbi"; 1660 1661 status = "disabled"; 1662 1663 #address-cells = <3>; 1664 #size-cells = <2>; 1665 device_type = "pci"; 1666 num-lanes = <8>; 1667 num-viewport = <8>; 1668 linux,pci-domain = <5>; 1669 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1672 1673 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1674 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1675 clock-names = "core", "core_m"; 1676 1677 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1678 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1679 reset-names = "apb", "core"; 1680 1681 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1682 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1683 interrupt-names = "intr", "msi"; 1684 1685 nvidia,bpmp = <&bpmp 5>; 1686 1687 #interrupt-cells = <1>; 1688 interrupt-map-mask = <0 0 0 0>; 1689 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1690 1691 nvidia,aspm-cmrt-us = <60>; 1692 nvidia,aspm-pwr-on-t-us = <20>; 1693 nvidia,aspm-l0s-entrance-latency-us = <3>; 1694 1695 bus-range = <0x0 0xff>; 1696 1697 ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1698 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1699 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1700 1701 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1702 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1703 interconnect-names = "read", "write"; 1704 }; 1705 1706 pcie_ep@14160000 { 1707 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1708 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1709 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 1710 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1711 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */ 1712 0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1713 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1714 1715 status = "disabled"; 1716 1717 num-lanes = <4>; 1718 num-ib-windows = <2>; 1719 num-ob-windows = <8>; 1720 1721 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1722 clock-names = "core"; 1723 1724 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1725 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1726 reset-names = "apb", "core"; 1727 1728 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1729 interrupt-names = "intr"; 1730 1731 nvidia,bpmp = <&bpmp 4>; 1732 1733 nvidia,aspm-cmrt-us = <60>; 1734 nvidia,aspm-pwr-on-t-us = <20>; 1735 nvidia,aspm-l0s-entrance-latency-us = <3>; 1736 }; 1737 1738 pcie_ep@14180000 { 1739 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1740 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1741 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 1742 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1743 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */ 1744 0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1745 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1746 1747 status = "disabled"; 1748 1749 num-lanes = <8>; 1750 num-ib-windows = <2>; 1751 num-ob-windows = <8>; 1752 1753 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1754 clock-names = "core"; 1755 1756 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1757 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1758 reset-names = "apb", "core"; 1759 1760 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1761 interrupt-names = "intr"; 1762 1763 nvidia,bpmp = <&bpmp 0>; 1764 1765 nvidia,aspm-cmrt-us = <60>; 1766 nvidia,aspm-pwr-on-t-us = <20>; 1767 nvidia,aspm-l0s-entrance-latency-us = <3>; 1768 }; 1769 1770 pcie_ep@141a0000 { 1771 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 1772 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1773 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 1774 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1775 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ 1776 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 1777 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 1778 1779 status = "disabled"; 1780 1781 num-lanes = <8>; 1782 num-ib-windows = <2>; 1783 num-ob-windows = <8>; 1784 1785 pinctrl-names = "default"; 1786 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 1787 1788 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 1789 clock-names = "core"; 1790 1791 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1792 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1793 reset-names = "apb", "core"; 1794 1795 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1796 interrupt-names = "intr"; 1797 1798 nvidia,bpmp = <&bpmp 5>; 1799 1800 nvidia,aspm-cmrt-us = <60>; 1801 nvidia,aspm-pwr-on-t-us = <20>; 1802 nvidia,aspm-l0s-entrance-latency-us = <3>; 1803 }; 1804 1805 sysram@40000000 { 1806 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 1807 reg = <0x0 0x40000000 0x0 0x50000>; 1808 #address-cells = <1>; 1809 #size-cells = <1>; 1810 ranges = <0x0 0x0 0x40000000 0x50000>; 1811 1812 cpu_bpmp_tx: shmem@4e000 { 1813 compatible = "nvidia,tegra194-bpmp-shmem"; 1814 reg = <0x4e000 0x1000>; 1815 label = "cpu-bpmp-tx"; 1816 pool; 1817 }; 1818 1819 cpu_bpmp_rx: shmem@4f000 { 1820 compatible = "nvidia,tegra194-bpmp-shmem"; 1821 reg = <0x4f000 0x1000>; 1822 label = "cpu-bpmp-rx"; 1823 pool; 1824 }; 1825 }; 1826 1827 bpmp: bpmp { 1828 compatible = "nvidia,tegra186-bpmp"; 1829 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1830 TEGRA_HSP_DB_MASTER_BPMP>; 1831 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1832 #clock-cells = <1>; 1833 #reset-cells = <1>; 1834 #power-domain-cells = <1>; 1835 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 1836 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 1837 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 1838 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 1839 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1840 1841 bpmp_i2c: i2c { 1842 compatible = "nvidia,tegra186-bpmp-i2c"; 1843 nvidia,bpmp-bus-id = <5>; 1844 #address-cells = <1>; 1845 #size-cells = <0>; 1846 }; 1847 1848 bpmp_thermal: thermal { 1849 compatible = "nvidia,tegra186-bpmp-thermal"; 1850 #thermal-sensor-cells = <1>; 1851 }; 1852 }; 1853 1854 cpus { 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 1858 cpu0_0: cpu@0 { 1859 compatible = "nvidia,tegra194-carmel"; 1860 device_type = "cpu"; 1861 reg = <0x000>; 1862 enable-method = "psci"; 1863 i-cache-size = <131072>; 1864 i-cache-line-size = <64>; 1865 i-cache-sets = <512>; 1866 d-cache-size = <65536>; 1867 d-cache-line-size = <64>; 1868 d-cache-sets = <256>; 1869 next-level-cache = <&l2c_0>; 1870 }; 1871 1872 cpu0_1: cpu@1 { 1873 compatible = "nvidia,tegra194-carmel"; 1874 device_type = "cpu"; 1875 reg = <0x001>; 1876 enable-method = "psci"; 1877 i-cache-size = <131072>; 1878 i-cache-line-size = <64>; 1879 i-cache-sets = <512>; 1880 d-cache-size = <65536>; 1881 d-cache-line-size = <64>; 1882 d-cache-sets = <256>; 1883 next-level-cache = <&l2c_0>; 1884 }; 1885 1886 cpu1_0: cpu@100 { 1887 compatible = "nvidia,tegra194-carmel"; 1888 device_type = "cpu"; 1889 reg = <0x100>; 1890 enable-method = "psci"; 1891 i-cache-size = <131072>; 1892 i-cache-line-size = <64>; 1893 i-cache-sets = <512>; 1894 d-cache-size = <65536>; 1895 d-cache-line-size = <64>; 1896 d-cache-sets = <256>; 1897 next-level-cache = <&l2c_1>; 1898 }; 1899 1900 cpu1_1: cpu@101 { 1901 compatible = "nvidia,tegra194-carmel"; 1902 device_type = "cpu"; 1903 reg = <0x101>; 1904 enable-method = "psci"; 1905 i-cache-size = <131072>; 1906 i-cache-line-size = <64>; 1907 i-cache-sets = <512>; 1908 d-cache-size = <65536>; 1909 d-cache-line-size = <64>; 1910 d-cache-sets = <256>; 1911 next-level-cache = <&l2c_1>; 1912 }; 1913 1914 cpu2_0: cpu@200 { 1915 compatible = "nvidia,tegra194-carmel"; 1916 device_type = "cpu"; 1917 reg = <0x200>; 1918 enable-method = "psci"; 1919 i-cache-size = <131072>; 1920 i-cache-line-size = <64>; 1921 i-cache-sets = <512>; 1922 d-cache-size = <65536>; 1923 d-cache-line-size = <64>; 1924 d-cache-sets = <256>; 1925 next-level-cache = <&l2c_2>; 1926 }; 1927 1928 cpu2_1: cpu@201 { 1929 compatible = "nvidia,tegra194-carmel"; 1930 device_type = "cpu"; 1931 reg = <0x201>; 1932 enable-method = "psci"; 1933 i-cache-size = <131072>; 1934 i-cache-line-size = <64>; 1935 i-cache-sets = <512>; 1936 d-cache-size = <65536>; 1937 d-cache-line-size = <64>; 1938 d-cache-sets = <256>; 1939 next-level-cache = <&l2c_2>; 1940 }; 1941 1942 cpu3_0: cpu@300 { 1943 compatible = "nvidia,tegra194-carmel"; 1944 device_type = "cpu"; 1945 reg = <0x300>; 1946 enable-method = "psci"; 1947 i-cache-size = <131072>; 1948 i-cache-line-size = <64>; 1949 i-cache-sets = <512>; 1950 d-cache-size = <65536>; 1951 d-cache-line-size = <64>; 1952 d-cache-sets = <256>; 1953 next-level-cache = <&l2c_3>; 1954 }; 1955 1956 cpu3_1: cpu@301 { 1957 compatible = "nvidia,tegra194-carmel"; 1958 device_type = "cpu"; 1959 reg = <0x301>; 1960 enable-method = "psci"; 1961 i-cache-size = <131072>; 1962 i-cache-line-size = <64>; 1963 i-cache-sets = <512>; 1964 d-cache-size = <65536>; 1965 d-cache-line-size = <64>; 1966 d-cache-sets = <256>; 1967 next-level-cache = <&l2c_3>; 1968 }; 1969 1970 cpu-map { 1971 cluster0 { 1972 core0 { 1973 cpu = <&cpu0_0>; 1974 }; 1975 1976 core1 { 1977 cpu = <&cpu0_1>; 1978 }; 1979 }; 1980 1981 cluster1 { 1982 core0 { 1983 cpu = <&cpu1_0>; 1984 }; 1985 1986 core1 { 1987 cpu = <&cpu1_1>; 1988 }; 1989 }; 1990 1991 cluster2 { 1992 core0 { 1993 cpu = <&cpu2_0>; 1994 }; 1995 1996 core1 { 1997 cpu = <&cpu2_1>; 1998 }; 1999 }; 2000 2001 cluster3 { 2002 core0 { 2003 cpu = <&cpu3_0>; 2004 }; 2005 2006 core1 { 2007 cpu = <&cpu3_1>; 2008 }; 2009 }; 2010 }; 2011 2012 l2c_0: l2-cache0 { 2013 cache-size = <2097152>; 2014 cache-line-size = <64>; 2015 cache-sets = <2048>; 2016 next-level-cache = <&l3c>; 2017 }; 2018 2019 l2c_1: l2-cache1 { 2020 cache-size = <2097152>; 2021 cache-line-size = <64>; 2022 cache-sets = <2048>; 2023 next-level-cache = <&l3c>; 2024 }; 2025 2026 l2c_2: l2-cache2 { 2027 cache-size = <2097152>; 2028 cache-line-size = <64>; 2029 cache-sets = <2048>; 2030 next-level-cache = <&l3c>; 2031 }; 2032 2033 l2c_3: l2-cache3 { 2034 cache-size = <2097152>; 2035 cache-line-size = <64>; 2036 cache-sets = <2048>; 2037 next-level-cache = <&l3c>; 2038 }; 2039 2040 l3c: l3-cache { 2041 cache-size = <4194304>; 2042 cache-line-size = <64>; 2043 cache-sets = <4096>; 2044 }; 2045 }; 2046 2047 psci { 2048 compatible = "arm,psci-1.0"; 2049 status = "okay"; 2050 method = "smc"; 2051 }; 2052 2053 tcu: tcu { 2054 compatible = "nvidia,tegra194-tcu"; 2055 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2056 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2057 mbox-names = "rx", "tx"; 2058 }; 2059 2060 thermal-zones { 2061 cpu { 2062 thermal-sensors = <&{/bpmp/thermal} 2063 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2064 status = "disabled"; 2065 }; 2066 2067 gpu { 2068 thermal-sensors = <&{/bpmp/thermal} 2069 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2070 status = "disabled"; 2071 }; 2072 2073 aux { 2074 thermal-sensors = <&{/bpmp/thermal} 2075 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2076 status = "disabled"; 2077 }; 2078 2079 pllx { 2080 thermal-sensors = <&{/bpmp/thermal} 2081 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2082 status = "disabled"; 2083 }; 2084 2085 ao { 2086 thermal-sensors = <&{/bpmp/thermal} 2087 TEGRA194_BPMP_THERMAL_ZONE_AO>; 2088 status = "disabled"; 2089 }; 2090 2091 tj { 2092 thermal-sensors = <&{/bpmp/thermal} 2093 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2094 status = "disabled"; 2095 }; 2096 }; 2097 2098 timer { 2099 compatible = "arm,armv8-timer"; 2100 interrupts = <GIC_PPI 13 2101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2102 <GIC_PPI 14 2103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2104 <GIC_PPI 11 2105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2106 <GIC_PPI 10 2107 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2108 interrupt-parent = <&gic>; 2109 always-on; 2110 }; 2111}; 2112