8bf86a15 | 13-Jun-2020 |
Álvaro Fernández Rojas <noltari@gmail.com> |
MIPS: BMIPS: add BCM6318 power domain definitions
BCM6318 SoCs have a power domain controller to enable/disable certain components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <nol
MIPS: BMIPS: add BCM6318 power domain definitions
BCM6318 SoCs have a power domain controller to enable/disable certain components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Florian Fainelli <F.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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5a3be0d0 | 13-Jun-2020 |
Álvaro Fernández Rojas <noltari@gmail.com> |
MIPS: BMIPS: add BCM63268 power domain definitions
BCM63268 SoCs have a power domain controller to enable/disable certain components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <n
MIPS: BMIPS: add BCM63268 power domain definitions
BCM63268 SoCs have a power domain controller to enable/disable certain components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Florian Fainelli <F.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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9f9fd976 | 13-Jun-2020 |
Álvaro Fernández Rojas <noltari@gmail.com> |
MIPS: BMIPS: add BCM6362 power domain definitions
BCM6362 SoCs have a power domain controller to enable/disable certain components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <nol
MIPS: BMIPS: add BCM6362 power domain definitions
BCM6362 SoCs have a power domain controller to enable/disable certain components in order to save power.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Florian Fainelli <F.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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cd88f167 | 14-Jan-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock
Tegra PMC has blink functionality that allows 32 kHz clock out to blink pin of the Tegra.
This patch adds id for this blink cloc
dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock
Tegra PMC has blink functionality that allows 32 kHz clock out to blink pin of the Tegra.
This patch adds id for this blink clock to use for enabling or disabling blink output through device tree.
Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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f85fa319 | 14-Jan-2020 |
Sowjanya Komatineni <skomatineni@nvidia.com> |
dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
Tegra PMC has 3 clocks clk_out_1, clk_out_2, and clk_out_3.
This patch documents PMC clock bindings and adds a header defining Tegra PMC cl
dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
Tegra PMC has 3 clocks clk_out_1, clk_out_2, and clk_out_3.
This patch documents PMC clock bindings and adds a header defining Tegra PMC clock ids.
Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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