1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/types.h> 29 #include <linux/mm.h> 30 #include <linux/kthread.h> 31 #include <linux/workqueue.h> 32 #include <kgd_kfd_interface.h> 33 #include <drm/ttm/ttm_execbuf_util.h> 34 #include "amdgpu_sync.h" 35 #include "amdgpu_vm.h" 36 37 extern uint64_t amdgpu_amdkfd_total_mem_size; 38 39 enum TLB_FLUSH_TYPE { 40 TLB_FLUSH_LEGACY = 0, 41 TLB_FLUSH_LIGHTWEIGHT, 42 TLB_FLUSH_HEAVYWEIGHT 43 }; 44 45 struct amdgpu_device; 46 47 enum kfd_mem_attachment_type { 48 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ 49 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ 50 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ 51 }; 52 53 struct kfd_mem_attachment { 54 struct list_head list; 55 enum kfd_mem_attachment_type type; 56 bool is_mapped; 57 struct amdgpu_bo_va *bo_va; 58 struct amdgpu_device *adev; 59 uint64_t va; 60 uint64_t pte_flags; 61 }; 62 63 struct kgd_mem { 64 struct mutex lock; 65 struct amdgpu_bo *bo; 66 struct dma_buf *dmabuf; 67 struct list_head attachments; 68 /* protected by amdkfd_process_info.lock */ 69 struct ttm_validate_buffer validate_list; 70 struct ttm_validate_buffer resv_list; 71 uint32_t domain; 72 unsigned int mapped_to_gpu_memory; 73 uint64_t va; 74 75 uint32_t alloc_flags; 76 77 atomic_t invalid; 78 struct amdkfd_process_info *process_info; 79 80 struct amdgpu_sync sync; 81 82 bool aql_queue; 83 bool is_imported; 84 }; 85 86 /* KFD Memory Eviction */ 87 struct amdgpu_amdkfd_fence { 88 struct dma_fence base; 89 struct mm_struct *mm; 90 spinlock_t lock; 91 char timeline_name[TASK_COMM_LEN]; 92 struct svm_range_bo *svm_bo; 93 }; 94 95 struct amdgpu_kfd_dev { 96 struct kfd_dev *dev; 97 uint64_t vram_used; 98 bool init_complete; 99 }; 100 101 enum kgd_engine_type { 102 KGD_ENGINE_PFP = 1, 103 KGD_ENGINE_ME, 104 KGD_ENGINE_CE, 105 KGD_ENGINE_MEC1, 106 KGD_ENGINE_MEC2, 107 KGD_ENGINE_RLC, 108 KGD_ENGINE_SDMA1, 109 KGD_ENGINE_SDMA2, 110 KGD_ENGINE_MAX 111 }; 112 113 114 struct amdkfd_process_info { 115 /* List head of all VMs that belong to a KFD process */ 116 struct list_head vm_list_head; 117 /* List head for all KFD BOs that belong to a KFD process. */ 118 struct list_head kfd_bo_list; 119 /* List of userptr BOs that are valid or invalid */ 120 struct list_head userptr_valid_list; 121 struct list_head userptr_inval_list; 122 /* Lock to protect kfd_bo_list */ 123 struct mutex lock; 124 125 /* Number of VMs */ 126 unsigned int n_vms; 127 /* Eviction Fence */ 128 struct amdgpu_amdkfd_fence *eviction_fence; 129 130 /* MMU-notifier related fields */ 131 atomic_t evicted_bos; 132 struct delayed_work restore_userptr_work; 133 struct pid *pid; 134 }; 135 136 int amdgpu_amdkfd_init(void); 137 void amdgpu_amdkfd_fini(void); 138 139 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 140 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev); 141 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); 142 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 143 const void *ih_ring_entry); 144 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 145 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 146 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); 147 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 148 uint32_t vmid, uint64_t gpu_addr, 149 uint32_t *ib_cmd, uint32_t ib_len); 150 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle); 151 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd); 152 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid); 153 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid, 154 enum TLB_FLUSH_TYPE flush_type); 155 156 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 157 158 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev); 159 160 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 161 162 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd); 163 164 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 165 int queue_bit); 166 167 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 168 struct mm_struct *mm, 169 struct svm_range_bo *svm_bo); 170 #if IS_ENABLED(CONFIG_HSA_AMD) 171 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 172 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 173 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); 174 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); 175 #else 176 static inline 177 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 178 { 179 return false; 180 } 181 182 static inline 183 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 184 { 185 return NULL; 186 } 187 188 static inline 189 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 190 { 191 return 0; 192 } 193 194 static inline 195 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 196 { 197 return 0; 198 } 199 #endif 200 /* Shared API */ 201 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 202 void **mem_obj, uint64_t *gpu_addr, 203 void **cpu_ptr, bool mqd_gfx9); 204 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj); 205 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, void **mem_obj); 206 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj); 207 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 208 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 209 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 210 enum kgd_engine_type type); 211 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 212 struct kfd_local_mem_info *mem_info); 213 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd); 214 215 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd); 216 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info); 217 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 218 struct kgd_dev **dmabuf_kgd, 219 uint64_t *bo_size, void *metadata_buffer, 220 size_t buffer_size, uint32_t *metadata_size, 221 uint32_t *flags); 222 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd); 223 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd); 224 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd); 225 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd); 226 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd); 227 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd); 228 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd); 229 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src); 230 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev *src, bool is_min); 231 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct kgd_dev *dev, bool is_min); 232 233 /* Read user wptr from a specified user address space with page fault 234 * disabled. The memory must be pinned and mapped to the hardware when 235 * this is called in hqd_load functions, so it should never fault in 236 * the first place. This resolves a circular lock dependency involving 237 * four locks, including the DQM lock and mmap_lock. 238 */ 239 #define read_user_wptr(mmptr, wptr, dst) \ 240 ({ \ 241 bool valid = false; \ 242 if ((mmptr) && (wptr)) { \ 243 pagefault_disable(); \ 244 if ((mmptr) == current->mm) { \ 245 valid = !get_user((dst), (wptr)); \ 246 } else if (current->flags & PF_KTHREAD) { \ 247 kthread_use_mm(mmptr); \ 248 valid = !get_user((dst), (wptr)); \ 249 kthread_unuse_mm(mmptr); \ 250 } \ 251 pagefault_enable(); \ 252 } \ 253 valid; \ 254 }) 255 256 /* GPUVM API */ 257 #define drm_priv_to_vm(drm_priv) \ 258 (&((struct amdgpu_fpriv *) \ 259 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 260 261 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd, 262 struct file *filp, u32 pasid, 263 void **process_info, 264 struct dma_fence **ef); 265 void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv); 266 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 267 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 268 struct kgd_dev *kgd, uint64_t va, uint64_t size, 269 void *drm_priv, struct kgd_mem **mem, 270 uint64_t *offset, uint32_t flags); 271 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 272 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, 273 uint64_t *size); 274 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 275 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool *table_freed); 276 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 277 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv); 278 int amdgpu_amdkfd_gpuvm_sync_memory( 279 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr); 280 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd, 281 struct kgd_mem *mem, void **kptr, uint64_t *size); 282 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_dev *kgd, struct kgd_mem *mem); 283 284 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 285 struct dma_fence **ef); 286 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd, 287 struct kfd_vm_fault_info *info); 288 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, 289 struct dma_buf *dmabuf, 290 uint64_t va, void *drm_priv, 291 struct kgd_mem **mem, uint64_t *size, 292 uint64_t *mmap_offset); 293 int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 294 struct tile_config *config); 295 void amdgpu_amdkfd_ras_poison_consumption_handler(struct kgd_dev *kgd); 296 #if IS_ENABLED(CONFIG_HSA_AMD) 297 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 298 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 299 struct amdgpu_vm *vm); 300 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo); 301 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 302 #else 303 static inline 304 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 305 { 306 } 307 308 static inline 309 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 310 struct amdgpu_vm *vm) 311 { 312 } 313 314 static inline 315 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 316 { 317 } 318 #endif 319 /* KGD2KFD callbacks */ 320 int kgd2kfd_quiesce_mm(struct mm_struct *mm); 321 int kgd2kfd_resume_mm(struct mm_struct *mm); 322 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 323 struct dma_fence *fence); 324 #if IS_ENABLED(CONFIG_HSA_AMD) 325 int kgd2kfd_init(void); 326 void kgd2kfd_exit(void); 327 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf); 328 bool kgd2kfd_device_init(struct kfd_dev *kfd, 329 struct drm_device *ddev, 330 const struct kgd2kfd_shared_resources *gpu_resources); 331 void kgd2kfd_device_exit(struct kfd_dev *kfd); 332 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); 333 int kgd2kfd_resume_iommu(struct kfd_dev *kfd); 334 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); 335 int kgd2kfd_pre_reset(struct kfd_dev *kfd); 336 int kgd2kfd_post_reset(struct kfd_dev *kfd); 337 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 338 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 339 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); 340 #else 341 static inline int kgd2kfd_init(void) 342 { 343 return -ENOENT; 344 } 345 346 static inline void kgd2kfd_exit(void) 347 { 348 } 349 350 static inline 351 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf) 352 { 353 return NULL; 354 } 355 356 static inline 357 bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev, 358 const struct kgd2kfd_shared_resources *gpu_resources) 359 { 360 return false; 361 } 362 363 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 364 { 365 } 366 367 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 368 { 369 } 370 371 static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd) 372 { 373 return 0; 374 } 375 376 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 377 { 378 return 0; 379 } 380 381 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd) 382 { 383 return 0; 384 } 385 386 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 387 { 388 return 0; 389 } 390 391 static inline 392 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 393 { 394 } 395 396 static inline 397 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 398 { 399 } 400 401 static inline 402 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 403 { 404 } 405 #endif 406 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 407