1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *	Shobhit Kumar <shobhit.kumar@intel.com>
25  *	Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
26  */
27 
28 #include <linux/kernel.h>
29 
30 #include "i915_drv.h"
31 #include "intel_display_types.h"
32 #include "intel_dsi.h"
33 #include "intel_sideband.h"
34 
35 static const u16 lfsr_converts[] = {
36 	426, 469, 234, 373, 442, 221, 110, 311, 411,		/* 62 - 70 */
37 	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
38 	106, 53, 282, 397, 454, 227, 113, 56, 284, 142,		/* 81 - 90 */
39 	71, 35, 273, 136, 324, 418, 465, 488, 500, 506		/* 91 - 100 */
40 };
41 
42 /* Get DSI clock from pixel clock */
43 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
44 			     int lane_count)
45 {
46 	u32 dsi_clk_khz;
47 	u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
48 
49 	/* DSI data rate = pixel clock * bits per pixel / lane count
50 	   pixel clock is converted from KHz to Hz */
51 	dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
52 
53 	return dsi_clk_khz;
54 }
55 
56 static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
57 			struct intel_crtc_state *config,
58 			int target_dsi_clk)
59 {
60 	unsigned int m_min, m_max, p_min = 2, p_max = 6;
61 	unsigned int m, n, p;
62 	unsigned int calc_m, calc_p;
63 	int delta, ref_clk;
64 
65 	/* target_dsi_clk is expected in kHz */
66 	if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
67 		drm_err(&dev_priv->drm, "DSI CLK Out of Range\n");
68 		return -ECHRNG;
69 	}
70 
71 	if (IS_CHERRYVIEW(dev_priv)) {
72 		ref_clk = 100000;
73 		n = 4;
74 		m_min = 70;
75 		m_max = 96;
76 	} else {
77 		ref_clk = 25000;
78 		n = 1;
79 		m_min = 62;
80 		m_max = 92;
81 	}
82 
83 	calc_p = p_min;
84 	calc_m = m_min;
85 	delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
86 
87 	for (m = m_min; m <= m_max && delta; m++) {
88 		for (p = p_min; p <= p_max && delta; p++) {
89 			/*
90 			 * Find the optimal m and p divisors with minimal delta
91 			 * +/- the required clock
92 			 */
93 			int calc_dsi_clk = (m * ref_clk) / (p * n);
94 			int d = abs(target_dsi_clk - calc_dsi_clk);
95 			if (d < delta) {
96 				delta = d;
97 				calc_m = m;
98 				calc_p = p;
99 			}
100 		}
101 	}
102 
103 	/* register has log2(N1), this works fine for powers of two */
104 	config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
105 	config->dsi_pll.div =
106 		(ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
107 		(u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
108 
109 	return 0;
110 }
111 
112 /*
113  * XXX: The muxing and gating is hard coded for now. Need to add support for
114  * sharing PLLs with two DSI outputs.
115  */
116 int vlv_dsi_pll_compute(struct intel_encoder *encoder,
117 			struct intel_crtc_state *config)
118 {
119 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
120 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
121 	int ret;
122 	u32 dsi_clk;
123 
124 	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
125 				    intel_dsi->lane_count);
126 
127 	ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
128 	if (ret) {
129 		drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n");
130 		return ret;
131 	}
132 
133 	if (intel_dsi->ports & (1 << PORT_A))
134 		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
135 
136 	if (intel_dsi->ports & (1 << PORT_C))
137 		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
138 
139 	config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
140 
141 	drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n",
142 		    config->dsi_pll.div, config->dsi_pll.ctrl);
143 
144 	return 0;
145 }
146 
147 void vlv_dsi_pll_enable(struct intel_encoder *encoder,
148 			const struct intel_crtc_state *config)
149 {
150 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
151 
152 	drm_dbg_kms(&dev_priv->drm, "\n");
153 
154 	vlv_cck_get(dev_priv);
155 
156 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
157 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
158 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
159 		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
160 
161 	/* wait at least 0.5 us after ungating before enabling VCO,
162 	 * allow hrtimer subsystem optimization by relaxing timing
163 	 */
164 	usleep_range(10, 50);
165 
166 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
167 
168 	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
169 						DSI_PLL_LOCK, 20)) {
170 
171 		vlv_cck_put(dev_priv);
172 		drm_err(&dev_priv->drm, "DSI PLL lock failed\n");
173 		return;
174 	}
175 	vlv_cck_put(dev_priv);
176 
177 	drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");
178 }
179 
180 void vlv_dsi_pll_disable(struct intel_encoder *encoder)
181 {
182 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
183 	u32 tmp;
184 
185 	drm_dbg_kms(&dev_priv->drm, "\n");
186 
187 	vlv_cck_get(dev_priv);
188 
189 	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
190 	tmp &= ~DSI_PLL_VCO_EN;
191 	tmp |= DSI_PLL_LDO_GATE;
192 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
193 
194 	vlv_cck_put(dev_priv);
195 }
196 
197 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
198 {
199 	bool enabled;
200 	u32 val;
201 	u32 mask;
202 
203 	mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
204 	val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
205 	enabled = (val & mask) == mask;
206 
207 	if (!enabled)
208 		return false;
209 
210 	/*
211 	 * Dividers must be programmed with valid values. As per BSEPC, for
212 	 * GEMINLAKE only PORT A divider values are checked while for BXT
213 	 * both divider values are validated. Check this here for
214 	 * paranoia, since BIOS is known to misconfigure PLLs in this way at
215 	 * times, and since accessing DSI registers with invalid dividers
216 	 * causes a system hang.
217 	 */
218 	val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);
219 	if (IS_GEMINILAKE(dev_priv)) {
220 		if (!(val & BXT_DSIA_16X_MASK)) {
221 			drm_dbg(&dev_priv->drm,
222 				"Invalid PLL divider (%08x)\n", val);
223 			enabled = false;
224 		}
225 	} else {
226 		if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
227 			drm_dbg(&dev_priv->drm,
228 				"Invalid PLL divider (%08x)\n", val);
229 			enabled = false;
230 		}
231 	}
232 
233 	return enabled;
234 }
235 
236 void bxt_dsi_pll_disable(struct intel_encoder *encoder)
237 {
238 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
239 	u32 val;
240 
241 	drm_dbg_kms(&dev_priv->drm, "\n");
242 
243 	val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
244 	val &= ~BXT_DSI_PLL_DO_ENABLE;
245 	intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val);
246 
247 	/*
248 	 * PLL lock should deassert within 200us.
249 	 * Wait up to 1ms before timing out.
250 	 */
251 	if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE,
252 				    BXT_DSI_PLL_LOCKED, 1))
253 		drm_err(&dev_priv->drm,
254 			"Timeout waiting for PLL lock deassertion\n");
255 }
256 
257 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
258 		     struct intel_crtc_state *config)
259 {
260 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
261 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
262 	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
263 	u32 dsi_clock, pclk;
264 	u32 pll_ctl, pll_div;
265 	u32 m = 0, p = 0, n;
266 	int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
267 	int i;
268 
269 	drm_dbg_kms(&dev_priv->drm, "\n");
270 
271 	vlv_cck_get(dev_priv);
272 	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
273 	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
274 	vlv_cck_put(dev_priv);
275 
276 	config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
277 	config->dsi_pll.div = pll_div;
278 
279 	/* mask out other bits and extract the P1 divisor */
280 	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
281 	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
282 
283 	/* N1 divisor */
284 	n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
285 	n = 1 << n; /* register has log2(N1) */
286 
287 	/* mask out the other bits and extract the M1 divisor */
288 	pll_div &= DSI_PLL_M1_DIV_MASK;
289 	pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
290 
291 	while (pll_ctl) {
292 		pll_ctl = pll_ctl >> 1;
293 		p++;
294 	}
295 	p--;
296 
297 	if (!p) {
298 		drm_err(&dev_priv->drm, "wrong P1 divisor\n");
299 		return 0;
300 	}
301 
302 	for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
303 		if (lfsr_converts[i] == pll_div)
304 			break;
305 	}
306 
307 	if (i == ARRAY_SIZE(lfsr_converts)) {
308 		drm_err(&dev_priv->drm, "wrong m_seed programmed\n");
309 		return 0;
310 	}
311 
312 	m = i + 62;
313 
314 	dsi_clock = (m * refclk) / (p * n);
315 
316 	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
317 
318 	return pclk;
319 }
320 
321 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
322 		     struct intel_crtc_state *config)
323 {
324 	u32 pclk;
325 	u32 dsi_clk;
326 	u32 dsi_ratio;
327 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
328 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
329 	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
330 
331 	config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);
332 
333 	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
334 
335 	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
336 
337 	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
338 
339 	drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk);
340 	return pclk;
341 }
342 
343 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
344 {
345 	u32 temp;
346 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
347 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
348 
349 	temp = intel_de_read(dev_priv, MIPI_CTRL(port));
350 	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
351 	intel_de_write(dev_priv, MIPI_CTRL(port),
352 		       temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT);
353 }
354 
355 static void glk_dsi_program_esc_clock(struct drm_device *dev,
356 				   const struct intel_crtc_state *config)
357 {
358 	struct drm_i915_private *dev_priv = to_i915(dev);
359 	u32 dsi_rate = 0;
360 	u32 pll_ratio = 0;
361 	u32 ddr_clk = 0;
362 	u32 div1_value = 0;
363 	u32 div2_value = 0;
364 	u32 txesc1_div = 0;
365 	u32 txesc2_div = 0;
366 
367 	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
368 
369 	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
370 
371 	ddr_clk = dsi_rate / 2;
372 
373 	/* Variable divider value */
374 	div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
375 
376 	/* Calculate TXESC1 divider */
377 	if (div1_value <= 10)
378 		txesc1_div = div1_value;
379 	else if ((div1_value > 10) && (div1_value <= 20))
380 		txesc1_div = DIV_ROUND_UP(div1_value, 2);
381 	else if ((div1_value > 20) && (div1_value <= 30))
382 		txesc1_div = DIV_ROUND_UP(div1_value, 4);
383 	else if ((div1_value > 30) && (div1_value <= 40))
384 		txesc1_div = DIV_ROUND_UP(div1_value, 6);
385 	else if ((div1_value > 40) && (div1_value <= 50))
386 		txesc1_div = DIV_ROUND_UP(div1_value, 8);
387 	else
388 		txesc1_div = 10;
389 
390 	/* Calculate TXESC2 divider */
391 	div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
392 
393 	if (div2_value < 10)
394 		txesc2_div = div2_value;
395 	else
396 		txesc2_div = 10;
397 
398 	intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1,
399 		       (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
400 	intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2,
401 		       (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
402 }
403 
404 /* Program BXT Mipi clocks and dividers */
405 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
406 				   const struct intel_crtc_state *config)
407 {
408 	struct drm_i915_private *dev_priv = to_i915(dev);
409 	u32 tmp;
410 	u32 dsi_rate = 0;
411 	u32 pll_ratio = 0;
412 	u32 rx_div;
413 	u32 tx_div;
414 	u32 rx_div_upper;
415 	u32 rx_div_lower;
416 	u32 mipi_8by3_divider;
417 
418 	/* Clear old configurations */
419 	tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL);
420 	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
421 	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
422 	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
423 	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
424 
425 	/* Get the current DSI rate(actual) */
426 	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
427 	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
428 
429 	/*
430 	 * tx clock should be <= 20MHz and the div value must be
431 	 * subtracted by 1 as per bspec
432 	 */
433 	tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
434 	/*
435 	 * rx clock should be <= 150MHz and the div value must be
436 	 * subtracted by 1 as per bspec
437 	 */
438 	rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
439 
440 	/*
441 	 * rx divider value needs to be updated in the
442 	 * two differnt bit fields in the register hence splitting the
443 	 * rx divider value accordingly
444 	 */
445 	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
446 	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
447 
448 	mipi_8by3_divider = 0x2;
449 
450 	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
451 	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
452 	tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
453 	tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
454 
455 	intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp);
456 }
457 
458 int bxt_dsi_pll_compute(struct intel_encoder *encoder,
459 			struct intel_crtc_state *config)
460 {
461 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
462 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
463 	u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
464 	u32 dsi_clk;
465 
466 	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
467 				    intel_dsi->lane_count);
468 
469 	/*
470 	 * From clock diagram, to get PLL ratio divider, divide double of DSI
471 	 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
472 	 * round 'up' the result
473 	 */
474 	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
475 
476 	if (IS_BROXTON(dev_priv)) {
477 		dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
478 		dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
479 	} else {
480 		dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
481 		dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
482 	}
483 
484 	if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
485 		drm_err(&dev_priv->drm,
486 			"Cant get a suitable ratio from DSI PLL ratios\n");
487 		return -ECHRNG;
488 	} else
489 		drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n");
490 
491 	/*
492 	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
493 	 * Spec says both have to be programmed, even if one is not getting
494 	 * used. Configure MIPI_CLOCK_CTL dividers in modeset
495 	 */
496 	config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
497 
498 	/* As per recommendation from hardware team,
499 	 * Prog PVD ratio =1 if dsi ratio <= 50
500 	 */
501 	if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
502 		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
503 
504 	return 0;
505 }
506 
507 void bxt_dsi_pll_enable(struct intel_encoder *encoder,
508 			const struct intel_crtc_state *config)
509 {
510 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
511 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
512 	enum port port;
513 	u32 val;
514 
515 	drm_dbg_kms(&dev_priv->drm, "\n");
516 
517 	/* Configure PLL vales */
518 	intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
519 	intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL);
520 
521 	/* Program TX, RX, Dphy clocks */
522 	if (IS_BROXTON(dev_priv)) {
523 		for_each_dsi_port(port, intel_dsi->ports)
524 			bxt_dsi_program_clocks(encoder->base.dev, port, config);
525 	} else {
526 		glk_dsi_program_esc_clock(encoder->base.dev, config);
527 	}
528 
529 	/* Enable DSI PLL */
530 	val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
531 	val |= BXT_DSI_PLL_DO_ENABLE;
532 	intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val);
533 
534 	/* Timeout and fail if PLL not locked */
535 	if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE,
536 				  BXT_DSI_PLL_LOCKED, 1)) {
537 		drm_err(&dev_priv->drm,
538 			"Timed out waiting for DSI PLL to lock\n");
539 		return;
540 	}
541 
542 	drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");
543 }
544 
545 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
546 {
547 	u32 tmp;
548 	struct drm_device *dev = encoder->base.dev;
549 	struct drm_i915_private *dev_priv = to_i915(dev);
550 
551 	/* Clear old configurations */
552 	if (IS_BROXTON(dev_priv)) {
553 		tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL);
554 		tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
555 		tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
556 		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
557 		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
558 		intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp);
559 	} else {
560 		tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1);
561 		tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
562 		intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp);
563 
564 		tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2);
565 		tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
566 		intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp);
567 	}
568 	intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
569 }
570