1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 55 * of the switch port net devices, towards the CPU port module. 56 * PGID_UC: the flooding destinations for unknown unicast traffic. 57 * PGID_MC: the flooding destinations for broadcast and non-IP multicast 58 * traffic. 59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 61 */ 62 #define PGID_CPU 59 63 #define PGID_UC 60 64 #define PGID_MC 61 65 #define PGID_MCIPV4 62 66 #define PGID_MCIPV6 63 67 68 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 69 for ((pgid) = 0; \ 70 (pgid) < (ocelot)->num_phys_ports; \ 71 (pgid)++) 72 73 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 74 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 75 (pgid) < PGID_CPU; \ 76 (pgid)++) 77 78 #define for_each_aggr_pgid(ocelot, pgid) \ 79 for ((pgid) = PGID_AGGR; \ 80 (pgid) < PGID_SRC; \ 81 (pgid)++) 82 83 /* Aggregation PGIDs, one per Link Aggregation Code */ 84 #define PGID_AGGR 64 85 86 /* Source PGIDs, one per physical port */ 87 #define PGID_SRC 80 88 89 #define IFH_INJ_BYPASS BIT(31) 90 #define IFH_INJ_POP_CNT_DISABLE (3 << 28) 91 92 #define IFH_TAG_TYPE_C 0 93 #define IFH_TAG_TYPE_S 1 94 95 #define IFH_REW_OP_NOOP 0x0 96 #define IFH_REW_OP_DSCP 0x1 97 #define IFH_REW_OP_ONE_STEP_PTP 0x2 98 #define IFH_REW_OP_TWO_STEP_PTP 0x3 99 #define IFH_REW_OP_ORIGIN_PTP 0x5 100 101 #define OCELOT_TAG_LEN 16 102 #define OCELOT_SHORT_PREFIX_LEN 4 103 #define OCELOT_LONG_PREFIX_LEN 16 104 105 #define OCELOT_SPEED_2500 0 106 #define OCELOT_SPEED_1000 1 107 #define OCELOT_SPEED_100 2 108 #define OCELOT_SPEED_10 3 109 110 #define OCELOT_PTP_PINS_NUM 4 111 112 #define TARGET_OFFSET 24 113 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 114 #define REG(reg, offset) [reg & REG_MASK] = offset 115 116 #define REG_RESERVED_ADDR 0xffffffff 117 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 118 119 enum ocelot_target { 120 ANA = 1, 121 QS, 122 QSYS, 123 REW, 124 SYS, 125 S2, 126 HSIO, 127 PTP, 128 GCB, 129 DEV_GMII, 130 TARGET_MAX, 131 }; 132 133 enum ocelot_reg { 134 ANA_ADVLEARN = ANA << TARGET_OFFSET, 135 ANA_VLANMASK, 136 ANA_PORT_B_DOMAIN, 137 ANA_ANAGEFIL, 138 ANA_ANEVENTS, 139 ANA_STORMLIMIT_BURST, 140 ANA_STORMLIMIT_CFG, 141 ANA_ISOLATED_PORTS, 142 ANA_COMMUNITY_PORTS, 143 ANA_AUTOAGE, 144 ANA_MACTOPTIONS, 145 ANA_LEARNDISC, 146 ANA_AGENCTRL, 147 ANA_MIRRORPORTS, 148 ANA_EMIRRORPORTS, 149 ANA_FLOODING, 150 ANA_FLOODING_IPMC, 151 ANA_SFLOW_CFG, 152 ANA_PORT_MODE, 153 ANA_CUT_THRU_CFG, 154 ANA_PGID_PGID, 155 ANA_TABLES_ANMOVED, 156 ANA_TABLES_MACHDATA, 157 ANA_TABLES_MACLDATA, 158 ANA_TABLES_STREAMDATA, 159 ANA_TABLES_MACACCESS, 160 ANA_TABLES_MACTINDX, 161 ANA_TABLES_VLANACCESS, 162 ANA_TABLES_VLANTIDX, 163 ANA_TABLES_ISDXACCESS, 164 ANA_TABLES_ISDXTIDX, 165 ANA_TABLES_ENTRYLIM, 166 ANA_TABLES_PTP_ID_HIGH, 167 ANA_TABLES_PTP_ID_LOW, 168 ANA_TABLES_STREAMACCESS, 169 ANA_TABLES_STREAMTIDX, 170 ANA_TABLES_SEQ_HISTORY, 171 ANA_TABLES_SEQ_MASK, 172 ANA_TABLES_SFID_MASK, 173 ANA_TABLES_SFIDACCESS, 174 ANA_TABLES_SFIDTIDX, 175 ANA_MSTI_STATE, 176 ANA_OAM_UPM_LM_CNT, 177 ANA_SG_ACCESS_CTRL, 178 ANA_SG_CONFIG_REG_1, 179 ANA_SG_CONFIG_REG_2, 180 ANA_SG_CONFIG_REG_3, 181 ANA_SG_CONFIG_REG_4, 182 ANA_SG_CONFIG_REG_5, 183 ANA_SG_GCL_GS_CONFIG, 184 ANA_SG_GCL_TI_CONFIG, 185 ANA_SG_STATUS_REG_1, 186 ANA_SG_STATUS_REG_2, 187 ANA_SG_STATUS_REG_3, 188 ANA_PORT_VLAN_CFG, 189 ANA_PORT_DROP_CFG, 190 ANA_PORT_QOS_CFG, 191 ANA_PORT_VCAP_CFG, 192 ANA_PORT_VCAP_S1_KEY_CFG, 193 ANA_PORT_VCAP_S2_CFG, 194 ANA_PORT_PCP_DEI_MAP, 195 ANA_PORT_CPU_FWD_CFG, 196 ANA_PORT_CPU_FWD_BPDU_CFG, 197 ANA_PORT_CPU_FWD_GARP_CFG, 198 ANA_PORT_CPU_FWD_CCM_CFG, 199 ANA_PORT_PORT_CFG, 200 ANA_PORT_POL_CFG, 201 ANA_PORT_PTP_CFG, 202 ANA_PORT_PTP_DLY1_CFG, 203 ANA_PORT_PTP_DLY2_CFG, 204 ANA_PORT_SFID_CFG, 205 ANA_PFC_PFC_CFG, 206 ANA_PFC_PFC_TIMER, 207 ANA_IPT_OAM_MEP_CFG, 208 ANA_IPT_IPT, 209 ANA_PPT_PPT, 210 ANA_FID_MAP_FID_MAP, 211 ANA_AGGR_CFG, 212 ANA_CPUQ_CFG, 213 ANA_CPUQ_CFG2, 214 ANA_CPUQ_8021_CFG, 215 ANA_DSCP_CFG, 216 ANA_DSCP_REWR_CFG, 217 ANA_VCAP_RNG_TYPE_CFG, 218 ANA_VCAP_RNG_VAL_CFG, 219 ANA_VRAP_CFG, 220 ANA_VRAP_HDR_DATA, 221 ANA_VRAP_HDR_MASK, 222 ANA_DISCARD_CFG, 223 ANA_FID_CFG, 224 ANA_POL_PIR_CFG, 225 ANA_POL_CIR_CFG, 226 ANA_POL_MODE_CFG, 227 ANA_POL_PIR_STATE, 228 ANA_POL_CIR_STATE, 229 ANA_POL_STATE, 230 ANA_POL_FLOWC, 231 ANA_POL_HYST, 232 ANA_POL_MISC_CFG, 233 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 234 QS_XTR_RD, 235 QS_XTR_FRM_PRUNING, 236 QS_XTR_FLUSH, 237 QS_XTR_DATA_PRESENT, 238 QS_XTR_CFG, 239 QS_INJ_GRP_CFG, 240 QS_INJ_WR, 241 QS_INJ_CTRL, 242 QS_INJ_STATUS, 243 QS_INJ_ERR, 244 QS_INH_DBG, 245 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 246 QSYS_SWITCH_PORT_MODE, 247 QSYS_STAT_CNT_CFG, 248 QSYS_EEE_CFG, 249 QSYS_EEE_THRES, 250 QSYS_IGR_NO_SHARING, 251 QSYS_EGR_NO_SHARING, 252 QSYS_SW_STATUS, 253 QSYS_EXT_CPU_CFG, 254 QSYS_PAD_CFG, 255 QSYS_CPU_GROUP_MAP, 256 QSYS_QMAP, 257 QSYS_ISDX_SGRP, 258 QSYS_TIMED_FRAME_ENTRY, 259 QSYS_TFRM_MISC, 260 QSYS_TFRM_PORT_DLY, 261 QSYS_TFRM_TIMER_CFG_1, 262 QSYS_TFRM_TIMER_CFG_2, 263 QSYS_TFRM_TIMER_CFG_3, 264 QSYS_TFRM_TIMER_CFG_4, 265 QSYS_TFRM_TIMER_CFG_5, 266 QSYS_TFRM_TIMER_CFG_6, 267 QSYS_TFRM_TIMER_CFG_7, 268 QSYS_TFRM_TIMER_CFG_8, 269 QSYS_RED_PROFILE, 270 QSYS_RES_QOS_MODE, 271 QSYS_RES_CFG, 272 QSYS_RES_STAT, 273 QSYS_EGR_DROP_MODE, 274 QSYS_EQ_CTRL, 275 QSYS_EVENTS_CORE, 276 QSYS_QMAXSDU_CFG_0, 277 QSYS_QMAXSDU_CFG_1, 278 QSYS_QMAXSDU_CFG_2, 279 QSYS_QMAXSDU_CFG_3, 280 QSYS_QMAXSDU_CFG_4, 281 QSYS_QMAXSDU_CFG_5, 282 QSYS_QMAXSDU_CFG_6, 283 QSYS_QMAXSDU_CFG_7, 284 QSYS_PREEMPTION_CFG, 285 QSYS_CIR_CFG, 286 QSYS_EIR_CFG, 287 QSYS_SE_CFG, 288 QSYS_SE_DWRR_CFG, 289 QSYS_SE_CONNECT, 290 QSYS_SE_DLB_SENSE, 291 QSYS_CIR_STATE, 292 QSYS_EIR_STATE, 293 QSYS_SE_STATE, 294 QSYS_HSCH_MISC_CFG, 295 QSYS_TAG_CONFIG, 296 QSYS_TAS_PARAM_CFG_CTRL, 297 QSYS_PORT_MAX_SDU, 298 QSYS_PARAM_CFG_REG_1, 299 QSYS_PARAM_CFG_REG_2, 300 QSYS_PARAM_CFG_REG_3, 301 QSYS_PARAM_CFG_REG_4, 302 QSYS_PARAM_CFG_REG_5, 303 QSYS_GCL_CFG_REG_1, 304 QSYS_GCL_CFG_REG_2, 305 QSYS_PARAM_STATUS_REG_1, 306 QSYS_PARAM_STATUS_REG_2, 307 QSYS_PARAM_STATUS_REG_3, 308 QSYS_PARAM_STATUS_REG_4, 309 QSYS_PARAM_STATUS_REG_5, 310 QSYS_PARAM_STATUS_REG_6, 311 QSYS_PARAM_STATUS_REG_7, 312 QSYS_PARAM_STATUS_REG_8, 313 QSYS_PARAM_STATUS_REG_9, 314 QSYS_GCL_STATUS_REG_1, 315 QSYS_GCL_STATUS_REG_2, 316 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 317 REW_TAG_CFG, 318 REW_PORT_CFG, 319 REW_DSCP_CFG, 320 REW_PCP_DEI_QOS_MAP_CFG, 321 REW_PTP_CFG, 322 REW_PTP_DLY1_CFG, 323 REW_RED_TAG_CFG, 324 REW_DSCP_REMAP_DP1_CFG, 325 REW_DSCP_REMAP_CFG, 326 REW_STAT_CFG, 327 REW_REW_STICKY, 328 REW_PPT, 329 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 330 SYS_COUNT_RX_UNICAST, 331 SYS_COUNT_RX_MULTICAST, 332 SYS_COUNT_RX_BROADCAST, 333 SYS_COUNT_RX_SHORTS, 334 SYS_COUNT_RX_FRAGMENTS, 335 SYS_COUNT_RX_JABBERS, 336 SYS_COUNT_RX_CRC_ALIGN_ERRS, 337 SYS_COUNT_RX_SYM_ERRS, 338 SYS_COUNT_RX_64, 339 SYS_COUNT_RX_65_127, 340 SYS_COUNT_RX_128_255, 341 SYS_COUNT_RX_256_1023, 342 SYS_COUNT_RX_1024_1526, 343 SYS_COUNT_RX_1527_MAX, 344 SYS_COUNT_RX_PAUSE, 345 SYS_COUNT_RX_CONTROL, 346 SYS_COUNT_RX_LONGS, 347 SYS_COUNT_RX_CLASSIFIED_DROPS, 348 SYS_COUNT_TX_OCTETS, 349 SYS_COUNT_TX_UNICAST, 350 SYS_COUNT_TX_MULTICAST, 351 SYS_COUNT_TX_BROADCAST, 352 SYS_COUNT_TX_COLLISION, 353 SYS_COUNT_TX_DROPS, 354 SYS_COUNT_TX_PAUSE, 355 SYS_COUNT_TX_64, 356 SYS_COUNT_TX_65_127, 357 SYS_COUNT_TX_128_511, 358 SYS_COUNT_TX_512_1023, 359 SYS_COUNT_TX_1024_1526, 360 SYS_COUNT_TX_1527_MAX, 361 SYS_COUNT_TX_AGING, 362 SYS_RESET_CFG, 363 SYS_SR_ETYPE_CFG, 364 SYS_VLAN_ETYPE_CFG, 365 SYS_PORT_MODE, 366 SYS_FRONT_PORT_MODE, 367 SYS_FRM_AGING, 368 SYS_STAT_CFG, 369 SYS_SW_STATUS, 370 SYS_MISC_CFG, 371 SYS_REW_MAC_HIGH_CFG, 372 SYS_REW_MAC_LOW_CFG, 373 SYS_TIMESTAMP_OFFSET, 374 SYS_CMID, 375 SYS_PAUSE_CFG, 376 SYS_PAUSE_TOT_CFG, 377 SYS_ATOP, 378 SYS_ATOP_TOT_CFG, 379 SYS_MAC_FC_CFG, 380 SYS_MMGT, 381 SYS_MMGT_FAST, 382 SYS_EVENTS_DIF, 383 SYS_EVENTS_CORE, 384 SYS_CNT, 385 SYS_PTP_STATUS, 386 SYS_PTP_TXSTAMP, 387 SYS_PTP_NXT, 388 SYS_PTP_CFG, 389 SYS_RAM_INIT, 390 SYS_CM_ADDR, 391 SYS_CM_DATA_WR, 392 SYS_CM_DATA_RD, 393 SYS_CM_OP, 394 SYS_CM_DATA, 395 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET, 396 S2_CORE_MV_CFG, 397 S2_CACHE_ENTRY_DAT, 398 S2_CACHE_MASK_DAT, 399 S2_CACHE_ACTION_DAT, 400 S2_CACHE_CNT_DAT, 401 S2_CACHE_TG_DAT, 402 PTP_PIN_CFG = PTP << TARGET_OFFSET, 403 PTP_PIN_TOD_SEC_MSB, 404 PTP_PIN_TOD_SEC_LSB, 405 PTP_PIN_TOD_NSEC, 406 PTP_PIN_WF_HIGH_PERIOD, 407 PTP_PIN_WF_LOW_PERIOD, 408 PTP_CFG_MISC, 409 PTP_CLK_CFG_ADJ_CFG, 410 PTP_CLK_CFG_ADJ_FREQ, 411 GCB_SOFT_RST = GCB << TARGET_OFFSET, 412 GCB_MIIM_MII_STATUS, 413 GCB_MIIM_MII_CMD, 414 GCB_MIIM_MII_DATA, 415 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 416 DEV_PORT_MISC, 417 DEV_EVENTS, 418 DEV_EEE_CFG, 419 DEV_RX_PATH_DELAY, 420 DEV_TX_PATH_DELAY, 421 DEV_PTP_PREDICT_CFG, 422 DEV_MAC_ENA_CFG, 423 DEV_MAC_MODE_CFG, 424 DEV_MAC_MAXLEN_CFG, 425 DEV_MAC_TAGS_CFG, 426 DEV_MAC_ADV_CHK_CFG, 427 DEV_MAC_IFG_CFG, 428 DEV_MAC_HDX_CFG, 429 DEV_MAC_DBG_CFG, 430 DEV_MAC_FC_MAC_LOW_CFG, 431 DEV_MAC_FC_MAC_HIGH_CFG, 432 DEV_MAC_STICKY, 433 PCS1G_CFG, 434 PCS1G_MODE_CFG, 435 PCS1G_SD_CFG, 436 PCS1G_ANEG_CFG, 437 PCS1G_ANEG_NP_CFG, 438 PCS1G_LB_CFG, 439 PCS1G_DBG_CFG, 440 PCS1G_CDET_CFG, 441 PCS1G_ANEG_STATUS, 442 PCS1G_ANEG_NP_STATUS, 443 PCS1G_LINK_STATUS, 444 PCS1G_LINK_DOWN_CNT, 445 PCS1G_STICKY, 446 PCS1G_DEBUG_STATUS, 447 PCS1G_LPI_CFG, 448 PCS1G_LPI_WAKE_ERROR_CNT, 449 PCS1G_LPI_STATUS, 450 PCS1G_TSTPAT_MODE_CFG, 451 PCS1G_TSTPAT_STATUS, 452 DEV_PCS_FX100_CFG, 453 DEV_PCS_FX100_STATUS, 454 }; 455 456 enum ocelot_regfield { 457 ANA_ADVLEARN_VLAN_CHK, 458 ANA_ADVLEARN_LEARN_MIRROR, 459 ANA_ANEVENTS_FLOOD_DISCARD, 460 ANA_ANEVENTS_MSTI_DROP, 461 ANA_ANEVENTS_ACLKILL, 462 ANA_ANEVENTS_ACLUSED, 463 ANA_ANEVENTS_AUTOAGE, 464 ANA_ANEVENTS_VS2TTL1, 465 ANA_ANEVENTS_STORM_DROP, 466 ANA_ANEVENTS_LEARN_DROP, 467 ANA_ANEVENTS_AGED_ENTRY, 468 ANA_ANEVENTS_CPU_LEARN_FAILED, 469 ANA_ANEVENTS_AUTO_LEARN_FAILED, 470 ANA_ANEVENTS_LEARN_REMOVE, 471 ANA_ANEVENTS_AUTO_LEARNED, 472 ANA_ANEVENTS_AUTO_MOVED, 473 ANA_ANEVENTS_DROPPED, 474 ANA_ANEVENTS_CLASSIFIED_DROP, 475 ANA_ANEVENTS_CLASSIFIED_COPY, 476 ANA_ANEVENTS_VLAN_DISCARD, 477 ANA_ANEVENTS_FWD_DISCARD, 478 ANA_ANEVENTS_MULTICAST_FLOOD, 479 ANA_ANEVENTS_UNICAST_FLOOD, 480 ANA_ANEVENTS_DEST_KNOWN, 481 ANA_ANEVENTS_BUCKET3_MATCH, 482 ANA_ANEVENTS_BUCKET2_MATCH, 483 ANA_ANEVENTS_BUCKET1_MATCH, 484 ANA_ANEVENTS_BUCKET0_MATCH, 485 ANA_ANEVENTS_CPU_OPERATION, 486 ANA_ANEVENTS_DMAC_LOOKUP, 487 ANA_ANEVENTS_SMAC_LOOKUP, 488 ANA_ANEVENTS_SEQ_GEN_ERR_0, 489 ANA_ANEVENTS_SEQ_GEN_ERR_1, 490 ANA_TABLES_MACACCESS_B_DOM, 491 ANA_TABLES_MACTINDX_BUCKET, 492 ANA_TABLES_MACTINDX_M_INDEX, 493 QSYS_SWITCH_PORT_MODE_PORT_ENA, 494 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 495 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 496 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 497 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 498 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 499 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 500 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 501 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 502 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 503 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 504 SYS_PORT_MODE_DATA_WO_TS, 505 SYS_PORT_MODE_INCL_INJ_HDR, 506 SYS_PORT_MODE_INCL_XTR_HDR, 507 SYS_PORT_MODE_INCL_HDR_ERR, 508 SYS_RESET_CFG_CORE_ENA, 509 SYS_RESET_CFG_MEM_ENA, 510 SYS_RESET_CFG_MEM_INIT, 511 GCB_SOFT_RST_SWC_RST, 512 GCB_MIIM_MII_STATUS_PENDING, 513 GCB_MIIM_MII_STATUS_BUSY, 514 SYS_PAUSE_CFG_PAUSE_START, 515 SYS_PAUSE_CFG_PAUSE_STOP, 516 SYS_PAUSE_CFG_PAUSE_ENA, 517 REGFIELD_MAX 518 }; 519 520 enum ocelot_ptp_pins { 521 PTP_PIN_0, 522 PTP_PIN_1, 523 PTP_PIN_2, 524 PTP_PIN_3, 525 TOD_ACC_PIN 526 }; 527 528 struct ocelot_stat_layout { 529 u32 offset; 530 char name[ETH_GSTRING_LEN]; 531 }; 532 533 enum ocelot_tag_prefix { 534 OCELOT_TAG_PREFIX_DISABLED = 0, 535 OCELOT_TAG_PREFIX_NONE, 536 OCELOT_TAG_PREFIX_SHORT, 537 OCELOT_TAG_PREFIX_LONG, 538 }; 539 540 struct ocelot; 541 542 struct ocelot_ops { 543 int (*reset)(struct ocelot *ocelot); 544 u16 (*wm_enc)(u16 value); 545 }; 546 547 struct ocelot_vcap_block { 548 struct list_head rules; 549 int count; 550 int pol_lpr; 551 }; 552 553 struct ocelot_port { 554 struct ocelot *ocelot; 555 556 struct regmap *target; 557 558 bool vlan_aware; 559 560 /* Ingress default VLAN (pvid) */ 561 u16 pvid; 562 563 /* Egress default VLAN (vid) */ 564 u16 vid; 565 566 u8 ptp_cmd; 567 struct sk_buff_head tx_skbs; 568 u8 ts_id; 569 570 phy_interface_t phy_mode; 571 572 u8 *xmit_template; 573 }; 574 575 struct ocelot { 576 struct device *dev; 577 578 const struct ocelot_ops *ops; 579 struct regmap *targets[TARGET_MAX]; 580 struct regmap_field *regfields[REGFIELD_MAX]; 581 const u32 *const *map; 582 const struct ocelot_stat_layout *stats_layout; 583 unsigned int num_stats; 584 585 int shared_queue_sz; 586 int num_mact_rows; 587 588 struct net_device *hw_bridge_dev; 589 u16 bridge_mask; 590 u16 bridge_fwd_mask; 591 592 struct ocelot_port **ports; 593 594 u8 base_mac[ETH_ALEN]; 595 596 /* Keep track of the vlan port masks */ 597 u32 vlan_mask[VLAN_N_VID]; 598 599 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 600 * the CPU is located after the physical ports (at the 601 * num_phys_ports index). 602 */ 603 u8 num_phys_ports; 604 605 int npi; 606 607 enum ocelot_tag_prefix inj_prefix; 608 enum ocelot_tag_prefix xtr_prefix; 609 610 u32 *lags; 611 612 struct list_head multicast; 613 614 struct ocelot_vcap_block block; 615 616 const struct vcap_field *vcap_is2_keys; 617 const struct vcap_field *vcap_is2_actions; 618 const struct vcap_props *vcap; 619 620 /* Workqueue to check statistics for overflow with its lock */ 621 struct mutex stats_lock; 622 u64 *stats; 623 struct delayed_work stats_work; 624 struct workqueue_struct *stats_queue; 625 626 u8 ptp:1; 627 struct ptp_clock *ptp_clock; 628 struct ptp_clock_info ptp_info; 629 struct hwtstamp_config hwtstamp_config; 630 /* Protects the PTP interface state */ 631 struct mutex ptp_lock; 632 /* Protects the PTP clock */ 633 spinlock_t ptp_clock_lock; 634 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 635 }; 636 637 struct ocelot_policer { 638 u32 rate; /* kilobit per second */ 639 u32 burst; /* bytes */ 640 }; 641 642 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 643 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 644 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 645 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 646 647 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 648 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 649 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 650 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 651 652 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 653 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 654 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 655 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 656 657 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 658 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 659 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 660 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 661 662 /* I/O */ 663 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 664 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 665 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 666 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 667 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 668 u32 offset); 669 670 /* Hardware initialization */ 671 int ocelot_regfields_init(struct ocelot *ocelot, 672 const struct reg_field *const regfields); 673 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 674 void ocelot_configure_cpu(struct ocelot *ocelot, int npi, 675 enum ocelot_tag_prefix injection, 676 enum ocelot_tag_prefix extraction); 677 int ocelot_init(struct ocelot *ocelot); 678 void ocelot_deinit(struct ocelot *ocelot); 679 void ocelot_init_port(struct ocelot *ocelot, int port); 680 681 /* DSA callbacks */ 682 void ocelot_port_enable(struct ocelot *ocelot, int port, 683 struct phy_device *phy); 684 void ocelot_port_disable(struct ocelot *ocelot, int port); 685 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 686 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 687 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 688 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 689 struct ethtool_ts_info *info); 690 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 691 void ocelot_adjust_link(struct ocelot *ocelot, int port, 692 struct phy_device *phydev); 693 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 694 bool vlan_aware); 695 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 696 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 697 struct net_device *bridge); 698 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 699 struct net_device *bridge); 700 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 701 dsa_fdb_dump_cb_t *cb, void *data); 702 int ocelot_fdb_add(struct ocelot *ocelot, int port, 703 const unsigned char *addr, u16 vid); 704 int ocelot_fdb_del(struct ocelot *ocelot, int port, 705 const unsigned char *addr, u16 vid); 706 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 707 bool untagged); 708 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 709 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 710 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 711 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port, 712 struct sk_buff *skb); 713 void ocelot_get_txtstamp(struct ocelot *ocelot); 714 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 715 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 716 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 717 struct ocelot_policer *pol); 718 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 719 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 720 struct flow_cls_offload *f, bool ingress); 721 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 722 struct flow_cls_offload *f, bool ingress); 723 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 724 struct flow_cls_offload *f, bool ingress); 725 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 726 const struct switchdev_obj_port_mdb *mdb); 727 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 728 const struct switchdev_obj_port_mdb *mdb); 729 730 #endif 731