1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 static int psp_rap_terminate(struct psp_context *psp); 50 static int psp_securedisplay_terminate(struct psp_context *psp); 51 52 /* 53 * Due to DF Cstate management centralized to PMFW, the firmware 54 * loading sequence will be updated as below: 55 * - Load KDB 56 * - Load SYS_DRV 57 * - Load tOS 58 * - Load PMFW 59 * - Setup TMR 60 * - Load other non-psp fw 61 * - Load ASD 62 * - Load XGMI/RAS/HDCP/DTM TA if any 63 * 64 * This new sequence is required for 65 * - Arcturus and onwards 66 */ 67 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 68 { 69 struct amdgpu_device *adev = psp->adev; 70 71 if (amdgpu_sriov_vf(adev)) { 72 psp->pmfw_centralized_cstate_management = false; 73 return; 74 } 75 76 switch (adev->ip_versions[MP0_HWIP][0]) { 77 case IP_VERSION(11, 0, 0): 78 case IP_VERSION(11, 0, 4): 79 case IP_VERSION(11, 0, 5): 80 case IP_VERSION(11, 0, 7): 81 case IP_VERSION(11, 0, 9): 82 case IP_VERSION(11, 0, 11): 83 case IP_VERSION(11, 0, 12): 84 case IP_VERSION(11, 0, 13): 85 case IP_VERSION(13, 0, 2): 86 psp->pmfw_centralized_cstate_management = true; 87 break; 88 default: 89 psp->pmfw_centralized_cstate_management = false; 90 break; 91 } 92 } 93 94 static int psp_early_init(void *handle) 95 { 96 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 97 struct psp_context *psp = &adev->psp; 98 99 switch (adev->ip_versions[MP0_HWIP][0]) { 100 case IP_VERSION(9, 0, 0): 101 psp_v3_1_set_psp_funcs(psp); 102 psp->autoload_supported = false; 103 break; 104 case IP_VERSION(10, 0, 0): 105 case IP_VERSION(10, 0, 1): 106 psp_v10_0_set_psp_funcs(psp); 107 psp->autoload_supported = false; 108 break; 109 case IP_VERSION(11, 0, 2): 110 case IP_VERSION(11, 0, 4): 111 psp_v11_0_set_psp_funcs(psp); 112 psp->autoload_supported = false; 113 break; 114 case IP_VERSION(11, 0, 0): 115 case IP_VERSION(11, 0, 5): 116 case IP_VERSION(11, 0, 9): 117 case IP_VERSION(11, 0, 7): 118 case IP_VERSION(11, 0, 11): 119 case IP_VERSION(11, 5, 0): 120 case IP_VERSION(11, 0, 12): 121 case IP_VERSION(11, 0, 13): 122 psp_v11_0_set_psp_funcs(psp); 123 psp->autoload_supported = true; 124 break; 125 case IP_VERSION(11, 0, 3): 126 case IP_VERSION(12, 0, 1): 127 psp_v12_0_set_psp_funcs(psp); 128 break; 129 case IP_VERSION(13, 0, 2): 130 psp_v13_0_set_psp_funcs(psp); 131 break; 132 case IP_VERSION(13, 0, 1): 133 case IP_VERSION(13, 0, 3): 134 case IP_VERSION(13, 0, 5): 135 case IP_VERSION(13, 0, 8): 136 psp_v13_0_set_psp_funcs(psp); 137 psp->autoload_supported = true; 138 break; 139 case IP_VERSION(11, 0, 8): 140 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 141 psp_v11_0_8_set_psp_funcs(psp); 142 psp->autoload_supported = false; 143 } 144 break; 145 default: 146 return -EINVAL; 147 } 148 149 psp->adev = adev; 150 151 psp_check_pmfw_centralized_cstate_management(psp); 152 153 return 0; 154 } 155 156 static void psp_memory_training_fini(struct psp_context *psp) 157 { 158 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 159 160 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 161 kfree(ctx->sys_cache); 162 ctx->sys_cache = NULL; 163 } 164 165 static int psp_memory_training_init(struct psp_context *psp) 166 { 167 int ret; 168 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 169 170 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 171 DRM_DEBUG("memory training is not supported!\n"); 172 return 0; 173 } 174 175 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 176 if (ctx->sys_cache == NULL) { 177 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 178 ret = -ENOMEM; 179 goto Err_out; 180 } 181 182 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 183 ctx->train_data_size, 184 ctx->p2c_train_data_offset, 185 ctx->c2p_train_data_offset); 186 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 187 return 0; 188 189 Err_out: 190 psp_memory_training_fini(psp); 191 return ret; 192 } 193 194 /* 195 * Helper funciton to query psp runtime database entry 196 * 197 * @adev: amdgpu_device pointer 198 * @entry_type: the type of psp runtime database entry 199 * @db_entry: runtime database entry pointer 200 * 201 * Return false if runtime database doesn't exit or entry is invalid 202 * or true if the specific database entry is found, and copy to @db_entry 203 */ 204 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 205 enum psp_runtime_entry_type entry_type, 206 void *db_entry) 207 { 208 uint64_t db_header_pos, db_dir_pos; 209 struct psp_runtime_data_header db_header = {0}; 210 struct psp_runtime_data_directory db_dir = {0}; 211 bool ret = false; 212 int i; 213 214 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 215 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 216 217 /* read runtime db header from vram */ 218 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 219 sizeof(struct psp_runtime_data_header), false); 220 221 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 222 /* runtime db doesn't exist, exit */ 223 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 224 return false; 225 } 226 227 /* read runtime database entry from vram */ 228 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 229 sizeof(struct psp_runtime_data_directory), false); 230 231 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 232 /* invalid db entry count, exit */ 233 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 234 return false; 235 } 236 237 /* look up for requested entry type */ 238 for (i = 0; i < db_dir.entry_count && !ret; i++) { 239 if (db_dir.entry_list[i].entry_type == entry_type) { 240 switch (entry_type) { 241 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 242 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 243 /* invalid db entry size */ 244 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 245 return false; 246 } 247 /* read runtime database entry */ 248 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 249 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 250 ret = true; 251 break; 252 default: 253 ret = false; 254 break; 255 } 256 } 257 } 258 259 return ret; 260 } 261 262 static int psp_init_sriov_microcode(struct psp_context *psp) 263 { 264 struct amdgpu_device *adev = psp->adev; 265 int ret = 0; 266 267 switch (adev->ip_versions[MP0_HWIP][0]) { 268 case IP_VERSION(9, 0, 0): 269 ret = psp_init_cap_microcode(psp, "vega10"); 270 break; 271 case IP_VERSION(11, 0, 9): 272 ret = psp_init_cap_microcode(psp, "navi12"); 273 break; 274 case IP_VERSION(11, 0, 7): 275 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 276 break; 277 case IP_VERSION(13, 0, 2): 278 ret = psp_init_cap_microcode(psp, "aldebaran"); 279 break; 280 default: 281 BUG(); 282 break; 283 } 284 285 return ret; 286 } 287 288 static int psp_sw_init(void *handle) 289 { 290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 291 struct psp_context *psp = &adev->psp; 292 int ret; 293 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 294 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 295 296 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 297 if (!psp->cmd) { 298 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 299 ret = -ENOMEM; 300 } 301 302 if (amdgpu_sriov_vf(adev)) 303 ret = psp_init_sriov_microcode(psp); 304 else 305 ret = psp_init_microcode(psp); 306 if (ret) { 307 DRM_ERROR("Failed to load psp firmware!\n"); 308 return ret; 309 } 310 311 adev->psp.xgmi_context.supports_extended_data = 312 !adev->gmc.xgmi.connected_to_cpu && 313 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 314 315 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 316 if (psp_get_runtime_db_entry(adev, 317 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 318 &boot_cfg_entry)) { 319 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 320 if ((psp->boot_cfg_bitmask) & 321 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 322 /* If psp runtime database exists, then 323 * only enable two stage memory training 324 * when TWO_STAGE_DRAM_TRAINING bit is set 325 * in runtime database */ 326 mem_training_ctx->enable_mem_training = true; 327 } 328 329 } else { 330 /* If psp runtime database doesn't exist or 331 * is invalid, force enable two stage memory 332 * training */ 333 mem_training_ctx->enable_mem_training = true; 334 } 335 336 if (mem_training_ctx->enable_mem_training) { 337 ret = psp_memory_training_init(psp); 338 if (ret) { 339 DRM_ERROR("Failed to initialize memory training!\n"); 340 return ret; 341 } 342 343 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 344 if (ret) { 345 DRM_ERROR("Failed to process memory training!\n"); 346 return ret; 347 } 348 } 349 350 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 351 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 352 ret= psp_sysfs_init(adev); 353 if (ret) { 354 return ret; 355 } 356 } 357 358 return 0; 359 } 360 361 static int psp_sw_fini(void *handle) 362 { 363 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 364 struct psp_context *psp = &adev->psp; 365 struct psp_gfx_cmd_resp *cmd = psp->cmd; 366 367 psp_memory_training_fini(psp); 368 if (psp->sos_fw) { 369 release_firmware(psp->sos_fw); 370 psp->sos_fw = NULL; 371 } 372 if (psp->asd_fw) { 373 release_firmware(psp->asd_fw); 374 psp->asd_fw = NULL; 375 } 376 if (psp->ta_fw) { 377 release_firmware(psp->ta_fw); 378 psp->ta_fw = NULL; 379 } 380 if (adev->psp.cap_fw) { 381 release_firmware(psp->cap_fw); 382 psp->cap_fw = NULL; 383 } 384 385 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 386 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 387 psp_sysfs_fini(adev); 388 389 kfree(cmd); 390 cmd = NULL; 391 392 return 0; 393 } 394 395 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 396 uint32_t reg_val, uint32_t mask, bool check_changed) 397 { 398 uint32_t val; 399 int i; 400 struct amdgpu_device *adev = psp->adev; 401 402 if (psp->adev->no_hw_access) 403 return 0; 404 405 for (i = 0; i < adev->usec_timeout; i++) { 406 val = RREG32(reg_index); 407 if (check_changed) { 408 if (val != reg_val) 409 return 0; 410 } else { 411 if ((val & mask) == reg_val) 412 return 0; 413 } 414 udelay(1); 415 } 416 417 return -ETIME; 418 } 419 420 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 421 { 422 switch (cmd_id) { 423 case GFX_CMD_ID_LOAD_TA: 424 return "LOAD_TA"; 425 case GFX_CMD_ID_UNLOAD_TA: 426 return "UNLOAD_TA"; 427 case GFX_CMD_ID_INVOKE_CMD: 428 return "INVOKE_CMD"; 429 case GFX_CMD_ID_LOAD_ASD: 430 return "LOAD_ASD"; 431 case GFX_CMD_ID_SETUP_TMR: 432 return "SETUP_TMR"; 433 case GFX_CMD_ID_LOAD_IP_FW: 434 return "LOAD_IP_FW"; 435 case GFX_CMD_ID_DESTROY_TMR: 436 return "DESTROY_TMR"; 437 case GFX_CMD_ID_SAVE_RESTORE: 438 return "SAVE_RESTORE_IP_FW"; 439 case GFX_CMD_ID_SETUP_VMR: 440 return "SETUP_VMR"; 441 case GFX_CMD_ID_DESTROY_VMR: 442 return "DESTROY_VMR"; 443 case GFX_CMD_ID_PROG_REG: 444 return "PROG_REG"; 445 case GFX_CMD_ID_GET_FW_ATTESTATION: 446 return "GET_FW_ATTESTATION"; 447 case GFX_CMD_ID_LOAD_TOC: 448 return "ID_LOAD_TOC"; 449 case GFX_CMD_ID_AUTOLOAD_RLC: 450 return "AUTOLOAD_RLC"; 451 case GFX_CMD_ID_BOOT_CFG: 452 return "BOOT_CFG"; 453 default: 454 return "UNKNOWN CMD"; 455 } 456 } 457 458 static int 459 psp_cmd_submit_buf(struct psp_context *psp, 460 struct amdgpu_firmware_info *ucode, 461 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 462 { 463 int ret; 464 int index, idx; 465 int timeout = 20000; 466 bool ras_intr = false; 467 bool skip_unsupport = false; 468 469 if (psp->adev->no_hw_access) 470 return 0; 471 472 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 473 return 0; 474 475 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 476 477 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 478 479 index = atomic_inc_return(&psp->fence_value); 480 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 481 if (ret) { 482 atomic_dec(&psp->fence_value); 483 goto exit; 484 } 485 486 amdgpu_device_invalidate_hdp(psp->adev, NULL); 487 while (*((unsigned int *)psp->fence_buf) != index) { 488 if (--timeout == 0) 489 break; 490 /* 491 * Shouldn't wait for timeout when err_event_athub occurs, 492 * because gpu reset thread triggered and lock resource should 493 * be released for psp resume sequence. 494 */ 495 ras_intr = amdgpu_ras_intr_triggered(); 496 if (ras_intr) 497 break; 498 usleep_range(10, 100); 499 amdgpu_device_invalidate_hdp(psp->adev, NULL); 500 } 501 502 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 503 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 504 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 505 506 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 507 508 /* In some cases, psp response status is not 0 even there is no 509 * problem while the command is submitted. Some version of PSP FW 510 * doesn't write 0 to that field. 511 * So here we would like to only print a warning instead of an error 512 * during psp initialization to avoid breaking hw_init and it doesn't 513 * return -EINVAL. 514 */ 515 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 516 if (ucode) 517 DRM_WARN("failed to load ucode %s(0x%X) ", 518 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 519 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 520 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 521 psp->cmd_buf_mem->resp.status); 522 /* If we load CAP FW, PSP must return 0 under SRIOV 523 * also return failure in case of timeout 524 */ 525 if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) { 526 ret = -EINVAL; 527 goto exit; 528 } 529 } 530 531 if (ucode) { 532 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 533 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 534 } 535 536 exit: 537 drm_dev_exit(idx); 538 return ret; 539 } 540 541 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 542 { 543 struct psp_gfx_cmd_resp *cmd = psp->cmd; 544 545 mutex_lock(&psp->mutex); 546 547 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 548 549 return cmd; 550 } 551 552 static void release_psp_cmd_buf(struct psp_context *psp) 553 { 554 mutex_unlock(&psp->mutex); 555 } 556 557 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 558 struct psp_gfx_cmd_resp *cmd, 559 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 560 { 561 struct amdgpu_device *adev = psp->adev; 562 uint32_t size = amdgpu_bo_size(tmr_bo); 563 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 564 565 if (amdgpu_sriov_vf(psp->adev)) 566 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 567 else 568 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 569 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 570 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 571 cmd->cmd.cmd_setup_tmr.buf_size = size; 572 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 573 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 574 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 575 } 576 577 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 578 uint64_t pri_buf_mc, uint32_t size) 579 { 580 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 581 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 582 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 583 cmd->cmd.cmd_load_toc.toc_size = size; 584 } 585 586 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 587 static int psp_load_toc(struct psp_context *psp, 588 uint32_t *tmr_size) 589 { 590 int ret; 591 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 592 593 /* Copy toc to psp firmware private buffer */ 594 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 595 596 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 597 598 ret = psp_cmd_submit_buf(psp, NULL, cmd, 599 psp->fence_buf_mc_addr); 600 if (!ret) 601 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 602 603 release_psp_cmd_buf(psp); 604 605 return ret; 606 } 607 608 /* Set up Trusted Memory Region */ 609 static int psp_tmr_init(struct psp_context *psp) 610 { 611 int ret; 612 int tmr_size; 613 void *tmr_buf; 614 void **pptr; 615 616 /* 617 * According to HW engineer, they prefer the TMR address be "naturally 618 * aligned" , e.g. the start address be an integer divide of TMR size. 619 * 620 * Note: this memory need be reserved till the driver 621 * uninitializes. 622 */ 623 tmr_size = PSP_TMR_SIZE(psp->adev); 624 625 /* For ASICs support RLC autoload, psp will parse the toc 626 * and calculate the total size of TMR needed */ 627 if (!amdgpu_sriov_vf(psp->adev) && 628 psp->toc.start_addr && 629 psp->toc.size_bytes && 630 psp->fw_pri_buf) { 631 ret = psp_load_toc(psp, &tmr_size); 632 if (ret) { 633 DRM_ERROR("Failed to load toc\n"); 634 return ret; 635 } 636 } 637 638 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 639 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 640 AMDGPU_GEM_DOMAIN_VRAM, 641 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 642 643 return ret; 644 } 645 646 static bool psp_skip_tmr(struct psp_context *psp) 647 { 648 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 649 case IP_VERSION(11, 0, 9): 650 case IP_VERSION(11, 0, 7): 651 case IP_VERSION(13, 0, 2): 652 return true; 653 default: 654 return false; 655 } 656 } 657 658 static int psp_tmr_load(struct psp_context *psp) 659 { 660 int ret; 661 struct psp_gfx_cmd_resp *cmd; 662 663 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 664 * Already set up by host driver. 665 */ 666 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 667 return 0; 668 669 cmd = acquire_psp_cmd_buf(psp); 670 671 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 672 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 673 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 674 675 ret = psp_cmd_submit_buf(psp, NULL, cmd, 676 psp->fence_buf_mc_addr); 677 678 release_psp_cmd_buf(psp); 679 680 return ret; 681 } 682 683 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 684 struct psp_gfx_cmd_resp *cmd) 685 { 686 if (amdgpu_sriov_vf(psp->adev)) 687 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 688 else 689 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 690 } 691 692 static int psp_tmr_unload(struct psp_context *psp) 693 { 694 int ret; 695 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 696 697 psp_prep_tmr_unload_cmd_buf(psp, cmd); 698 DRM_INFO("free PSP TMR buffer\n"); 699 700 ret = psp_cmd_submit_buf(psp, NULL, cmd, 701 psp->fence_buf_mc_addr); 702 703 release_psp_cmd_buf(psp); 704 705 return ret; 706 } 707 708 static int psp_tmr_terminate(struct psp_context *psp) 709 { 710 int ret; 711 void *tmr_buf; 712 void **pptr; 713 714 ret = psp_tmr_unload(psp); 715 if (ret) 716 return ret; 717 718 /* free TMR memory buffer */ 719 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 720 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 721 722 return 0; 723 } 724 725 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 726 uint64_t *output_ptr) 727 { 728 int ret; 729 struct psp_gfx_cmd_resp *cmd; 730 731 if (!output_ptr) 732 return -EINVAL; 733 734 if (amdgpu_sriov_vf(psp->adev)) 735 return 0; 736 737 cmd = acquire_psp_cmd_buf(psp); 738 739 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 740 741 ret = psp_cmd_submit_buf(psp, NULL, cmd, 742 psp->fence_buf_mc_addr); 743 744 if (!ret) { 745 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 746 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 747 } 748 749 release_psp_cmd_buf(psp); 750 751 return ret; 752 } 753 754 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 755 { 756 struct psp_context *psp = &adev->psp; 757 struct psp_gfx_cmd_resp *cmd; 758 int ret; 759 760 if (amdgpu_sriov_vf(adev)) 761 return 0; 762 763 cmd = acquire_psp_cmd_buf(psp); 764 765 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 766 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 767 768 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 769 if (!ret) { 770 *boot_cfg = 771 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 772 } 773 774 release_psp_cmd_buf(psp); 775 776 return ret; 777 } 778 779 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 780 { 781 int ret; 782 struct psp_context *psp = &adev->psp; 783 struct psp_gfx_cmd_resp *cmd; 784 785 if (amdgpu_sriov_vf(adev)) 786 return 0; 787 788 cmd = acquire_psp_cmd_buf(psp); 789 790 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 791 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 792 cmd->cmd.boot_cfg.boot_config = boot_cfg; 793 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 794 795 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 796 797 release_psp_cmd_buf(psp); 798 799 return ret; 800 } 801 802 static int psp_rl_load(struct amdgpu_device *adev) 803 { 804 int ret; 805 struct psp_context *psp = &adev->psp; 806 struct psp_gfx_cmd_resp *cmd; 807 808 if (!is_psp_fw_valid(psp->rl)) 809 return 0; 810 811 cmd = acquire_psp_cmd_buf(psp); 812 813 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 814 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 815 816 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 817 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 818 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 819 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 820 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 821 822 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 823 824 release_psp_cmd_buf(psp); 825 826 return ret; 827 } 828 829 static int psp_asd_load(struct psp_context *psp) 830 { 831 return psp_ta_load(psp, &psp->asd_context); 832 } 833 834 static int psp_asd_initialize(struct psp_context *psp) 835 { 836 int ret; 837 838 /* If PSP version doesn't match ASD version, asd loading will be failed. 839 * add workaround to bypass it for sriov now. 840 * TODO: add version check to make it common 841 */ 842 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 843 return 0; 844 845 psp->asd_context.mem_context.shared_mc_addr = 0; 846 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 847 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 848 849 ret = psp_asd_load(psp); 850 if (!ret) 851 psp->asd_context.initialized = true; 852 853 return ret; 854 } 855 856 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 857 uint32_t session_id) 858 { 859 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 860 cmd->cmd.cmd_unload_ta.session_id = session_id; 861 } 862 863 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 864 { 865 int ret; 866 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 867 868 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 869 870 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 871 872 release_psp_cmd_buf(psp); 873 874 return ret; 875 } 876 877 static int psp_asd_unload(struct psp_context *psp) 878 { 879 return psp_ta_unload(psp, &psp->asd_context); 880 } 881 882 static int psp_asd_terminate(struct psp_context *psp) 883 { 884 int ret; 885 886 if (amdgpu_sriov_vf(psp->adev)) 887 return 0; 888 889 if (!psp->asd_context.initialized) 890 return 0; 891 892 ret = psp_asd_unload(psp); 893 894 if (!ret) 895 psp->asd_context.initialized = false; 896 897 return ret; 898 } 899 900 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 901 uint32_t id, uint32_t value) 902 { 903 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 904 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 905 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 906 } 907 908 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 909 uint32_t value) 910 { 911 struct psp_gfx_cmd_resp *cmd; 912 int ret = 0; 913 914 if (reg >= PSP_REG_LAST) 915 return -EINVAL; 916 917 cmd = acquire_psp_cmd_buf(psp); 918 919 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 920 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 921 if (ret) 922 DRM_ERROR("PSP failed to program reg id %d", reg); 923 924 release_psp_cmd_buf(psp); 925 926 return ret; 927 } 928 929 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 930 uint64_t ta_bin_mc, 931 struct ta_context *context) 932 { 933 cmd->cmd_id = context->ta_load_type; 934 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 935 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 936 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 937 938 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 939 lower_32_bits(context->mem_context.shared_mc_addr); 940 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 941 upper_32_bits(context->mem_context.shared_mc_addr); 942 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 943 } 944 945 int psp_ta_init_shared_buf(struct psp_context *psp, 946 struct ta_mem_context *mem_ctx) 947 { 948 /* 949 * Allocate 16k memory aligned to 4k from Frame Buffer (local 950 * physical) for ta to host memory 951 */ 952 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 953 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 954 &mem_ctx->shared_bo, 955 &mem_ctx->shared_mc_addr, 956 &mem_ctx->shared_buf); 957 } 958 959 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 960 { 961 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 962 &mem_ctx->shared_buf); 963 } 964 965 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 966 { 967 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 968 } 969 970 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 971 uint32_t ta_cmd_id, 972 struct ta_context *context) 973 { 974 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 975 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 976 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 977 978 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 979 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 980 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 981 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 982 lower_32_bits(context->mem_context.shared_mc_addr); 983 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 984 upper_32_bits(context->mem_context.shared_mc_addr); 985 } 986 987 int psp_ta_invoke_indirect(struct psp_context *psp, 988 uint32_t ta_cmd_id, 989 struct ta_context *context) 990 { 991 int ret; 992 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 993 994 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 995 996 ret = psp_cmd_submit_buf(psp, NULL, cmd, 997 psp->fence_buf_mc_addr); 998 999 context->resp_status = cmd->resp.status; 1000 1001 release_psp_cmd_buf(psp); 1002 1003 return ret; 1004 } 1005 1006 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1007 uint32_t ta_cmd_id, 1008 uint32_t session_id) 1009 { 1010 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1011 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1012 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1013 } 1014 1015 int psp_ta_invoke(struct psp_context *psp, 1016 uint32_t ta_cmd_id, 1017 struct ta_context *context) 1018 { 1019 int ret; 1020 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1021 1022 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1023 1024 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1025 psp->fence_buf_mc_addr); 1026 1027 context->resp_status = cmd->resp.status; 1028 1029 release_psp_cmd_buf(psp); 1030 1031 return ret; 1032 } 1033 1034 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1035 { 1036 int ret; 1037 struct psp_gfx_cmd_resp *cmd; 1038 1039 cmd = acquire_psp_cmd_buf(psp); 1040 1041 psp_copy_fw(psp, context->bin_desc.start_addr, 1042 context->bin_desc.size_bytes); 1043 1044 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1045 1046 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1047 psp->fence_buf_mc_addr); 1048 1049 context->resp_status = cmd->resp.status; 1050 1051 if (!ret) { 1052 context->session_id = cmd->resp.session_id; 1053 } 1054 1055 release_psp_cmd_buf(psp); 1056 1057 return ret; 1058 } 1059 1060 static int psp_xgmi_load(struct psp_context *psp) 1061 { 1062 return psp_ta_load(psp, &psp->xgmi_context.context); 1063 } 1064 1065 static int psp_xgmi_unload(struct psp_context *psp) 1066 { 1067 return psp_ta_unload(psp, &psp->xgmi_context.context); 1068 } 1069 1070 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1071 { 1072 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1073 } 1074 1075 int psp_xgmi_terminate(struct psp_context *psp) 1076 { 1077 int ret; 1078 struct amdgpu_device *adev = psp->adev; 1079 1080 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1081 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1082 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1083 adev->gmc.xgmi.connected_to_cpu)) 1084 return 0; 1085 1086 if (!psp->xgmi_context.context.initialized) 1087 return 0; 1088 1089 ret = psp_xgmi_unload(psp); 1090 if (ret) 1091 return ret; 1092 1093 psp->xgmi_context.context.initialized = false; 1094 1095 /* free xgmi shared memory */ 1096 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1097 1098 return 0; 1099 } 1100 1101 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1102 { 1103 struct ta_xgmi_shared_memory *xgmi_cmd; 1104 int ret; 1105 1106 if (!psp->ta_fw || 1107 !psp->xgmi_context.context.bin_desc.size_bytes || 1108 !psp->xgmi_context.context.bin_desc.start_addr) 1109 return -ENOENT; 1110 1111 if (!load_ta) 1112 goto invoke; 1113 1114 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1115 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1116 1117 if (!psp->xgmi_context.context.initialized) { 1118 ret = psp_xgmi_init_shared_buf(psp); 1119 if (ret) 1120 return ret; 1121 } 1122 1123 /* Load XGMI TA */ 1124 ret = psp_xgmi_load(psp); 1125 if (!ret) 1126 psp->xgmi_context.context.initialized = true; 1127 else 1128 return ret; 1129 1130 invoke: 1131 /* Initialize XGMI session */ 1132 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1133 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1134 xgmi_cmd->flag_extend_link_record = set_extended_data; 1135 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1136 1137 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1138 1139 return ret; 1140 } 1141 1142 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1143 { 1144 struct ta_xgmi_shared_memory *xgmi_cmd; 1145 int ret; 1146 1147 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1148 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1149 1150 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1151 1152 /* Invoke xgmi ta to get hive id */ 1153 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1154 if (ret) 1155 return ret; 1156 1157 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1158 1159 return 0; 1160 } 1161 1162 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1163 { 1164 struct ta_xgmi_shared_memory *xgmi_cmd; 1165 int ret; 1166 1167 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1168 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1169 1170 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1171 1172 /* Invoke xgmi ta to get the node id */ 1173 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1174 if (ret) 1175 return ret; 1176 1177 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1178 1179 return 0; 1180 } 1181 1182 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1183 { 1184 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1185 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1186 } 1187 1188 /* 1189 * Chips that support extended topology information require the driver to 1190 * reflect topology information in the opposite direction. This is 1191 * because the TA has already exceeded its link record limit and if the 1192 * TA holds bi-directional information, the driver would have to do 1193 * multiple fetches instead of just two. 1194 */ 1195 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1196 struct psp_xgmi_node_info node_info) 1197 { 1198 struct amdgpu_device *mirror_adev; 1199 struct amdgpu_hive_info *hive; 1200 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1201 uint64_t dst_node_id = node_info.node_id; 1202 uint8_t dst_num_hops = node_info.num_hops; 1203 uint8_t dst_num_links = node_info.num_links; 1204 1205 hive = amdgpu_get_xgmi_hive(psp->adev); 1206 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1207 struct psp_xgmi_topology_info *mirror_top_info; 1208 int j; 1209 1210 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1211 continue; 1212 1213 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1214 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1215 if (mirror_top_info->nodes[j].node_id != src_node_id) 1216 continue; 1217 1218 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1219 /* 1220 * prevent 0 num_links value re-reflection since reflection 1221 * criteria is based on num_hops (direct or indirect). 1222 * 1223 */ 1224 if (dst_num_links) 1225 mirror_top_info->nodes[j].num_links = dst_num_links; 1226 1227 break; 1228 } 1229 1230 break; 1231 } 1232 } 1233 1234 int psp_xgmi_get_topology_info(struct psp_context *psp, 1235 int number_devices, 1236 struct psp_xgmi_topology_info *topology, 1237 bool get_extended_data) 1238 { 1239 struct ta_xgmi_shared_memory *xgmi_cmd; 1240 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1241 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1242 int i; 1243 int ret; 1244 1245 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1246 return -EINVAL; 1247 1248 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1249 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1250 xgmi_cmd->flag_extend_link_record = get_extended_data; 1251 1252 /* Fill in the shared memory with topology information as input */ 1253 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1254 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1255 topology_info_input->num_nodes = number_devices; 1256 1257 for (i = 0; i < topology_info_input->num_nodes; i++) { 1258 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1259 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1260 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1261 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1262 } 1263 1264 /* Invoke xgmi ta to get the topology information */ 1265 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1266 if (ret) 1267 return ret; 1268 1269 /* Read the output topology information from the shared memory */ 1270 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1271 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1272 for (i = 0; i < topology->num_nodes; i++) { 1273 /* extended data will either be 0 or equal to non-extended data */ 1274 if (topology_info_output->nodes[i].num_hops) 1275 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1276 1277 /* non-extended data gets everything here so no need to update */ 1278 if (!get_extended_data) { 1279 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1280 topology->nodes[i].is_sharing_enabled = 1281 topology_info_output->nodes[i].is_sharing_enabled; 1282 topology->nodes[i].sdma_engine = 1283 topology_info_output->nodes[i].sdma_engine; 1284 } 1285 1286 } 1287 1288 /* Invoke xgmi ta again to get the link information */ 1289 if (psp_xgmi_peer_link_info_supported(psp)) { 1290 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1291 1292 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1293 1294 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1295 1296 if (ret) 1297 return ret; 1298 1299 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1300 for (i = 0; i < topology->num_nodes; i++) { 1301 /* accumulate num_links on extended data */ 1302 topology->nodes[i].num_links = get_extended_data ? 1303 topology->nodes[i].num_links + 1304 link_info_output->nodes[i].num_links : 1305 link_info_output->nodes[i].num_links; 1306 1307 /* reflect the topology information for bi-directionality */ 1308 if (psp->xgmi_context.supports_extended_data && 1309 get_extended_data && topology->nodes[i].num_hops) 1310 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1311 } 1312 } 1313 1314 return 0; 1315 } 1316 1317 int psp_xgmi_set_topology_info(struct psp_context *psp, 1318 int number_devices, 1319 struct psp_xgmi_topology_info *topology) 1320 { 1321 struct ta_xgmi_shared_memory *xgmi_cmd; 1322 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1323 int i; 1324 1325 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1326 return -EINVAL; 1327 1328 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1329 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1330 1331 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1332 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1333 topology_info_input->num_nodes = number_devices; 1334 1335 for (i = 0; i < topology_info_input->num_nodes; i++) { 1336 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1337 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1338 topology_info_input->nodes[i].is_sharing_enabled = 1; 1339 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1340 } 1341 1342 /* Invoke xgmi ta to set topology information */ 1343 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1344 } 1345 1346 // ras begin 1347 static int psp_ras_init_shared_buf(struct psp_context *psp) 1348 { 1349 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1350 } 1351 1352 static int psp_ras_load(struct psp_context *psp) 1353 { 1354 return psp_ta_load(psp, &psp->ras_context.context); 1355 } 1356 1357 static int psp_ras_unload(struct psp_context *psp) 1358 { 1359 return psp_ta_unload(psp, &psp->ras_context.context); 1360 } 1361 1362 static void psp_ras_ta_check_status(struct psp_context *psp) 1363 { 1364 struct ta_ras_shared_memory *ras_cmd = 1365 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1366 1367 switch (ras_cmd->ras_status) { 1368 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1369 dev_warn(psp->adev->dev, 1370 "RAS WARNING: cmd failed due to unsupported ip\n"); 1371 break; 1372 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1373 dev_warn(psp->adev->dev, 1374 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1375 break; 1376 case TA_RAS_STATUS__SUCCESS: 1377 break; 1378 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1379 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1380 dev_warn(psp->adev->dev, 1381 "RAS WARNING: Inject error to critical region is not allowed\n"); 1382 break; 1383 default: 1384 dev_warn(psp->adev->dev, 1385 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1386 break; 1387 } 1388 } 1389 1390 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1391 { 1392 struct ta_ras_shared_memory *ras_cmd; 1393 int ret; 1394 1395 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1396 1397 /* 1398 * TODO: bypass the loading in sriov for now 1399 */ 1400 if (amdgpu_sriov_vf(psp->adev)) 1401 return 0; 1402 1403 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1404 1405 if (amdgpu_ras_intr_triggered()) 1406 return ret; 1407 1408 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1409 { 1410 DRM_WARN("RAS: Unsupported Interface"); 1411 return -EINVAL; 1412 } 1413 1414 if (!ret) { 1415 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1416 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1417 1418 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1419 } 1420 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1421 dev_warn(psp->adev->dev, 1422 "RAS internal register access blocked\n"); 1423 1424 psp_ras_ta_check_status(psp); 1425 } 1426 1427 return ret; 1428 } 1429 1430 int psp_ras_enable_features(struct psp_context *psp, 1431 union ta_ras_cmd_input *info, bool enable) 1432 { 1433 struct ta_ras_shared_memory *ras_cmd; 1434 int ret; 1435 1436 if (!psp->ras_context.context.initialized) 1437 return -EINVAL; 1438 1439 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1440 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1441 1442 if (enable) 1443 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1444 else 1445 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1446 1447 ras_cmd->ras_in_message = *info; 1448 1449 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1450 if (ret) 1451 return -EINVAL; 1452 1453 return 0; 1454 } 1455 1456 int psp_ras_terminate(struct psp_context *psp) 1457 { 1458 int ret; 1459 1460 /* 1461 * TODO: bypass the terminate in sriov for now 1462 */ 1463 if (amdgpu_sriov_vf(psp->adev)) 1464 return 0; 1465 1466 if (!psp->ras_context.context.initialized) 1467 return 0; 1468 1469 ret = psp_ras_unload(psp); 1470 if (ret) 1471 return ret; 1472 1473 psp->ras_context.context.initialized = false; 1474 1475 /* free ras shared memory */ 1476 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1477 1478 return 0; 1479 } 1480 1481 static int psp_ras_initialize(struct psp_context *psp) 1482 { 1483 int ret; 1484 uint32_t boot_cfg = 0xFF; 1485 struct amdgpu_device *adev = psp->adev; 1486 struct ta_ras_shared_memory *ras_cmd; 1487 1488 /* 1489 * TODO: bypass the initialize in sriov for now 1490 */ 1491 if (amdgpu_sriov_vf(adev)) 1492 return 0; 1493 1494 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1495 !adev->psp.ras_context.context.bin_desc.start_addr) { 1496 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1497 return 0; 1498 } 1499 1500 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1501 /* query GECC enablement status from boot config 1502 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1503 */ 1504 ret = psp_boot_config_get(adev, &boot_cfg); 1505 if (ret) 1506 dev_warn(adev->dev, "PSP get boot config failed\n"); 1507 1508 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1509 if (!boot_cfg) { 1510 dev_info(adev->dev, "GECC is disabled\n"); 1511 } else { 1512 /* disable GECC in next boot cycle if ras is 1513 * disabled by module parameter amdgpu_ras_enable 1514 * and/or amdgpu_ras_mask, or boot_config_get call 1515 * is failed 1516 */ 1517 ret = psp_boot_config_set(adev, 0); 1518 if (ret) 1519 dev_warn(adev->dev, "PSP set boot config failed\n"); 1520 else 1521 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1522 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1523 } 1524 } else { 1525 if (1 == boot_cfg) { 1526 dev_info(adev->dev, "GECC is enabled\n"); 1527 } else { 1528 /* enable GECC in next boot cycle if it is disabled 1529 * in boot config, or force enable GECC if failed to 1530 * get boot configuration 1531 */ 1532 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1533 if (ret) 1534 dev_warn(adev->dev, "PSP set boot config failed\n"); 1535 else 1536 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1537 } 1538 } 1539 } 1540 1541 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1542 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1543 1544 if (!psp->ras_context.context.initialized) { 1545 ret = psp_ras_init_shared_buf(psp); 1546 if (ret) 1547 return ret; 1548 } 1549 1550 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1551 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1552 1553 if (amdgpu_ras_is_poison_mode_supported(adev)) 1554 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1555 if (!adev->gmc.xgmi.connected_to_cpu) 1556 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1557 1558 ret = psp_ras_load(psp); 1559 1560 if (!ret && !ras_cmd->ras_status) 1561 psp->ras_context.context.initialized = true; 1562 else { 1563 if (ras_cmd->ras_status) 1564 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1565 amdgpu_ras_fini(psp->adev); 1566 } 1567 1568 return ret; 1569 } 1570 1571 int psp_ras_trigger_error(struct psp_context *psp, 1572 struct ta_ras_trigger_error_input *info) 1573 { 1574 struct ta_ras_shared_memory *ras_cmd; 1575 int ret; 1576 1577 if (!psp->ras_context.context.initialized) 1578 return -EINVAL; 1579 1580 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1581 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1582 1583 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1584 ras_cmd->ras_in_message.trigger_error = *info; 1585 1586 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1587 if (ret) 1588 return -EINVAL; 1589 1590 /* If err_event_athub occurs error inject was successful, however 1591 return status from TA is no long reliable */ 1592 if (amdgpu_ras_intr_triggered()) 1593 return 0; 1594 1595 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1596 return -EACCES; 1597 else if (ras_cmd->ras_status) 1598 return -EINVAL; 1599 1600 return 0; 1601 } 1602 // ras end 1603 1604 // HDCP start 1605 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1606 { 1607 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1608 } 1609 1610 static int psp_hdcp_load(struct psp_context *psp) 1611 { 1612 return psp_ta_load(psp, &psp->hdcp_context.context); 1613 } 1614 1615 static int psp_hdcp_initialize(struct psp_context *psp) 1616 { 1617 int ret; 1618 1619 /* 1620 * TODO: bypass the initialize in sriov for now 1621 */ 1622 if (amdgpu_sriov_vf(psp->adev)) 1623 return 0; 1624 1625 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1626 !psp->hdcp_context.context.bin_desc.start_addr) { 1627 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1628 return 0; 1629 } 1630 1631 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1632 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1633 1634 if (!psp->hdcp_context.context.initialized) { 1635 ret = psp_hdcp_init_shared_buf(psp); 1636 if (ret) 1637 return ret; 1638 } 1639 1640 ret = psp_hdcp_load(psp); 1641 if (!ret) { 1642 psp->hdcp_context.context.initialized = true; 1643 mutex_init(&psp->hdcp_context.mutex); 1644 } 1645 1646 return ret; 1647 } 1648 1649 static int psp_hdcp_unload(struct psp_context *psp) 1650 { 1651 return psp_ta_unload(psp, &psp->hdcp_context.context); 1652 } 1653 1654 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1655 { 1656 /* 1657 * TODO: bypass the loading in sriov for now 1658 */ 1659 if (amdgpu_sriov_vf(psp->adev)) 1660 return 0; 1661 1662 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1663 } 1664 1665 static int psp_hdcp_terminate(struct psp_context *psp) 1666 { 1667 int ret; 1668 1669 /* 1670 * TODO: bypass the terminate in sriov for now 1671 */ 1672 if (amdgpu_sriov_vf(psp->adev)) 1673 return 0; 1674 1675 if (!psp->hdcp_context.context.initialized) { 1676 if (psp->hdcp_context.context.mem_context.shared_buf) 1677 goto out; 1678 else 1679 return 0; 1680 } 1681 1682 ret = psp_hdcp_unload(psp); 1683 if (ret) 1684 return ret; 1685 1686 psp->hdcp_context.context.initialized = false; 1687 1688 out: 1689 /* free hdcp shared memory */ 1690 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1691 1692 return 0; 1693 } 1694 // HDCP end 1695 1696 // DTM start 1697 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1698 { 1699 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1700 } 1701 1702 static int psp_dtm_load(struct psp_context *psp) 1703 { 1704 return psp_ta_load(psp, &psp->dtm_context.context); 1705 } 1706 1707 static int psp_dtm_initialize(struct psp_context *psp) 1708 { 1709 int ret; 1710 1711 /* 1712 * TODO: bypass the initialize in sriov for now 1713 */ 1714 if (amdgpu_sriov_vf(psp->adev)) 1715 return 0; 1716 1717 if (!psp->dtm_context.context.bin_desc.size_bytes || 1718 !psp->dtm_context.context.bin_desc.start_addr) { 1719 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1720 return 0; 1721 } 1722 1723 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1724 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1725 1726 if (!psp->dtm_context.context.initialized) { 1727 ret = psp_dtm_init_shared_buf(psp); 1728 if (ret) 1729 return ret; 1730 } 1731 1732 ret = psp_dtm_load(psp); 1733 if (!ret) { 1734 psp->dtm_context.context.initialized = true; 1735 mutex_init(&psp->dtm_context.mutex); 1736 } 1737 1738 return ret; 1739 } 1740 1741 static int psp_dtm_unload(struct psp_context *psp) 1742 { 1743 return psp_ta_unload(psp, &psp->dtm_context.context); 1744 } 1745 1746 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1747 { 1748 /* 1749 * TODO: bypass the loading in sriov for now 1750 */ 1751 if (amdgpu_sriov_vf(psp->adev)) 1752 return 0; 1753 1754 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1755 } 1756 1757 static int psp_dtm_terminate(struct psp_context *psp) 1758 { 1759 int ret; 1760 1761 /* 1762 * TODO: bypass the terminate in sriov for now 1763 */ 1764 if (amdgpu_sriov_vf(psp->adev)) 1765 return 0; 1766 1767 if (!psp->dtm_context.context.initialized) { 1768 if (psp->dtm_context.context.mem_context.shared_buf) 1769 goto out; 1770 else 1771 return 0; 1772 } 1773 1774 ret = psp_dtm_unload(psp); 1775 if (ret) 1776 return ret; 1777 1778 psp->dtm_context.context.initialized = false; 1779 1780 out: 1781 /* free dtm shared memory */ 1782 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1783 1784 return 0; 1785 } 1786 // DTM end 1787 1788 // RAP start 1789 static int psp_rap_init_shared_buf(struct psp_context *psp) 1790 { 1791 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1792 } 1793 1794 static int psp_rap_load(struct psp_context *psp) 1795 { 1796 return psp_ta_load(psp, &psp->rap_context.context); 1797 } 1798 1799 static int psp_rap_unload(struct psp_context *psp) 1800 { 1801 return psp_ta_unload(psp, &psp->rap_context.context); 1802 } 1803 1804 static int psp_rap_initialize(struct psp_context *psp) 1805 { 1806 int ret; 1807 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1808 1809 /* 1810 * TODO: bypass the initialize in sriov for now 1811 */ 1812 if (amdgpu_sriov_vf(psp->adev)) 1813 return 0; 1814 1815 if (!psp->rap_context.context.bin_desc.size_bytes || 1816 !psp->rap_context.context.bin_desc.start_addr) { 1817 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1818 return 0; 1819 } 1820 1821 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1822 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1823 1824 if (!psp->rap_context.context.initialized) { 1825 ret = psp_rap_init_shared_buf(psp); 1826 if (ret) 1827 return ret; 1828 } 1829 1830 ret = psp_rap_load(psp); 1831 if (!ret) { 1832 psp->rap_context.context.initialized = true; 1833 mutex_init(&psp->rap_context.mutex); 1834 } else 1835 return ret; 1836 1837 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1838 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1839 psp_rap_terminate(psp); 1840 1841 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1842 ret, status); 1843 1844 return ret; 1845 } 1846 1847 return 0; 1848 } 1849 1850 static int psp_rap_terminate(struct psp_context *psp) 1851 { 1852 int ret; 1853 1854 if (!psp->rap_context.context.initialized) 1855 return 0; 1856 1857 ret = psp_rap_unload(psp); 1858 1859 psp->rap_context.context.initialized = false; 1860 1861 /* free rap shared memory */ 1862 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1863 1864 return ret; 1865 } 1866 1867 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1868 { 1869 struct ta_rap_shared_memory *rap_cmd; 1870 int ret = 0; 1871 1872 if (!psp->rap_context.context.initialized) 1873 return 0; 1874 1875 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1876 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1877 return -EINVAL; 1878 1879 mutex_lock(&psp->rap_context.mutex); 1880 1881 rap_cmd = (struct ta_rap_shared_memory *) 1882 psp->rap_context.context.mem_context.shared_buf; 1883 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1884 1885 rap_cmd->cmd_id = ta_cmd_id; 1886 rap_cmd->validation_method_id = METHOD_A; 1887 1888 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1889 if (ret) 1890 goto out_unlock; 1891 1892 if (status) 1893 *status = rap_cmd->rap_status; 1894 1895 out_unlock: 1896 mutex_unlock(&psp->rap_context.mutex); 1897 1898 return ret; 1899 } 1900 // RAP end 1901 1902 /* securedisplay start */ 1903 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 1904 { 1905 return psp_ta_init_shared_buf( 1906 psp, &psp->securedisplay_context.context.mem_context); 1907 } 1908 1909 static int psp_securedisplay_load(struct psp_context *psp) 1910 { 1911 return psp_ta_load(psp, &psp->securedisplay_context.context); 1912 } 1913 1914 static int psp_securedisplay_unload(struct psp_context *psp) 1915 { 1916 return psp_ta_unload(psp, &psp->securedisplay_context.context); 1917 } 1918 1919 static int psp_securedisplay_initialize(struct psp_context *psp) 1920 { 1921 int ret; 1922 struct securedisplay_cmd *securedisplay_cmd; 1923 1924 /* 1925 * TODO: bypass the initialize in sriov for now 1926 */ 1927 if (amdgpu_sriov_vf(psp->adev)) 1928 return 0; 1929 1930 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1931 !psp->securedisplay_context.context.bin_desc.start_addr) { 1932 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1933 return 0; 1934 } 1935 1936 psp->securedisplay_context.context.mem_context.shared_mem_size = 1937 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1938 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1939 1940 if (!psp->securedisplay_context.context.initialized) { 1941 ret = psp_securedisplay_init_shared_buf(psp); 1942 if (ret) 1943 return ret; 1944 } 1945 1946 ret = psp_securedisplay_load(psp); 1947 if (!ret) { 1948 psp->securedisplay_context.context.initialized = true; 1949 mutex_init(&psp->securedisplay_context.mutex); 1950 } else 1951 return ret; 1952 1953 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1954 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1955 1956 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1957 if (ret) { 1958 psp_securedisplay_terminate(psp); 1959 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1960 return -EINVAL; 1961 } 1962 1963 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1964 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1965 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1966 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1967 } 1968 1969 return 0; 1970 } 1971 1972 static int psp_securedisplay_terminate(struct psp_context *psp) 1973 { 1974 int ret; 1975 1976 /* 1977 * TODO:bypass the terminate in sriov for now 1978 */ 1979 if (amdgpu_sriov_vf(psp->adev)) 1980 return 0; 1981 1982 if (!psp->securedisplay_context.context.initialized) 1983 return 0; 1984 1985 ret = psp_securedisplay_unload(psp); 1986 if (ret) 1987 return ret; 1988 1989 psp->securedisplay_context.context.initialized = false; 1990 1991 /* free securedisplay shared memory */ 1992 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1993 1994 return ret; 1995 } 1996 1997 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1998 { 1999 int ret; 2000 2001 if (!psp->securedisplay_context.context.initialized) 2002 return -EINVAL; 2003 2004 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2005 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2006 return -EINVAL; 2007 2008 mutex_lock(&psp->securedisplay_context.mutex); 2009 2010 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2011 2012 mutex_unlock(&psp->securedisplay_context.mutex); 2013 2014 return ret; 2015 } 2016 /* SECUREDISPLAY end */ 2017 2018 static int psp_hw_start(struct psp_context *psp) 2019 { 2020 struct amdgpu_device *adev = psp->adev; 2021 int ret; 2022 2023 if (!amdgpu_sriov_vf(adev)) { 2024 if ((is_psp_fw_valid(psp->kdb)) && 2025 (psp->funcs->bootloader_load_kdb != NULL)) { 2026 ret = psp_bootloader_load_kdb(psp); 2027 if (ret) { 2028 DRM_ERROR("PSP load kdb failed!\n"); 2029 return ret; 2030 } 2031 } 2032 2033 if ((is_psp_fw_valid(psp->spl)) && 2034 (psp->funcs->bootloader_load_spl != NULL)) { 2035 ret = psp_bootloader_load_spl(psp); 2036 if (ret) { 2037 DRM_ERROR("PSP load spl failed!\n"); 2038 return ret; 2039 } 2040 } 2041 2042 if ((is_psp_fw_valid(psp->sys)) && 2043 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2044 ret = psp_bootloader_load_sysdrv(psp); 2045 if (ret) { 2046 DRM_ERROR("PSP load sys drv failed!\n"); 2047 return ret; 2048 } 2049 } 2050 2051 if ((is_psp_fw_valid(psp->soc_drv)) && 2052 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2053 ret = psp_bootloader_load_soc_drv(psp); 2054 if (ret) { 2055 DRM_ERROR("PSP load soc drv failed!\n"); 2056 return ret; 2057 } 2058 } 2059 2060 if ((is_psp_fw_valid(psp->intf_drv)) && 2061 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2062 ret = psp_bootloader_load_intf_drv(psp); 2063 if (ret) { 2064 DRM_ERROR("PSP load intf drv failed!\n"); 2065 return ret; 2066 } 2067 } 2068 2069 if ((is_psp_fw_valid(psp->dbg_drv)) && 2070 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2071 ret = psp_bootloader_load_dbg_drv(psp); 2072 if (ret) { 2073 DRM_ERROR("PSP load dbg drv failed!\n"); 2074 return ret; 2075 } 2076 } 2077 2078 if ((is_psp_fw_valid(psp->sos)) && 2079 (psp->funcs->bootloader_load_sos != NULL)) { 2080 ret = psp_bootloader_load_sos(psp); 2081 if (ret) { 2082 DRM_ERROR("PSP load sos failed!\n"); 2083 return ret; 2084 } 2085 } 2086 } 2087 2088 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2089 if (ret) { 2090 DRM_ERROR("PSP create ring failed!\n"); 2091 return ret; 2092 } 2093 2094 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2095 goto skip_pin_bo; 2096 2097 ret = psp_tmr_init(psp); 2098 if (ret) { 2099 DRM_ERROR("PSP tmr init failed!\n"); 2100 return ret; 2101 } 2102 2103 skip_pin_bo: 2104 /* 2105 * For ASICs with DF Cstate management centralized 2106 * to PMFW, TMR setup should be performed after PMFW 2107 * loaded and before other non-psp firmware loaded. 2108 */ 2109 if (psp->pmfw_centralized_cstate_management) { 2110 ret = psp_load_smu_fw(psp); 2111 if (ret) 2112 return ret; 2113 } 2114 2115 ret = psp_tmr_load(psp); 2116 if (ret) { 2117 DRM_ERROR("PSP load tmr failed!\n"); 2118 return ret; 2119 } 2120 2121 return 0; 2122 } 2123 2124 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2125 enum psp_gfx_fw_type *type) 2126 { 2127 switch (ucode->ucode_id) { 2128 case AMDGPU_UCODE_ID_CAP: 2129 *type = GFX_FW_TYPE_CAP; 2130 break; 2131 case AMDGPU_UCODE_ID_SDMA0: 2132 *type = GFX_FW_TYPE_SDMA0; 2133 break; 2134 case AMDGPU_UCODE_ID_SDMA1: 2135 *type = GFX_FW_TYPE_SDMA1; 2136 break; 2137 case AMDGPU_UCODE_ID_SDMA2: 2138 *type = GFX_FW_TYPE_SDMA2; 2139 break; 2140 case AMDGPU_UCODE_ID_SDMA3: 2141 *type = GFX_FW_TYPE_SDMA3; 2142 break; 2143 case AMDGPU_UCODE_ID_SDMA4: 2144 *type = GFX_FW_TYPE_SDMA4; 2145 break; 2146 case AMDGPU_UCODE_ID_SDMA5: 2147 *type = GFX_FW_TYPE_SDMA5; 2148 break; 2149 case AMDGPU_UCODE_ID_SDMA6: 2150 *type = GFX_FW_TYPE_SDMA6; 2151 break; 2152 case AMDGPU_UCODE_ID_SDMA7: 2153 *type = GFX_FW_TYPE_SDMA7; 2154 break; 2155 case AMDGPU_UCODE_ID_CP_MES: 2156 *type = GFX_FW_TYPE_CP_MES; 2157 break; 2158 case AMDGPU_UCODE_ID_CP_MES_DATA: 2159 *type = GFX_FW_TYPE_MES_STACK; 2160 break; 2161 case AMDGPU_UCODE_ID_CP_CE: 2162 *type = GFX_FW_TYPE_CP_CE; 2163 break; 2164 case AMDGPU_UCODE_ID_CP_PFP: 2165 *type = GFX_FW_TYPE_CP_PFP; 2166 break; 2167 case AMDGPU_UCODE_ID_CP_ME: 2168 *type = GFX_FW_TYPE_CP_ME; 2169 break; 2170 case AMDGPU_UCODE_ID_CP_MEC1: 2171 *type = GFX_FW_TYPE_CP_MEC; 2172 break; 2173 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2174 *type = GFX_FW_TYPE_CP_MEC_ME1; 2175 break; 2176 case AMDGPU_UCODE_ID_CP_MEC2: 2177 *type = GFX_FW_TYPE_CP_MEC; 2178 break; 2179 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2180 *type = GFX_FW_TYPE_CP_MEC_ME2; 2181 break; 2182 case AMDGPU_UCODE_ID_RLC_G: 2183 *type = GFX_FW_TYPE_RLC_G; 2184 break; 2185 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2186 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2187 break; 2188 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2189 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2190 break; 2191 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2192 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2193 break; 2194 case AMDGPU_UCODE_ID_RLC_IRAM: 2195 *type = GFX_FW_TYPE_RLC_IRAM; 2196 break; 2197 case AMDGPU_UCODE_ID_RLC_DRAM: 2198 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2199 break; 2200 case AMDGPU_UCODE_ID_SMC: 2201 *type = GFX_FW_TYPE_SMU; 2202 break; 2203 case AMDGPU_UCODE_ID_UVD: 2204 *type = GFX_FW_TYPE_UVD; 2205 break; 2206 case AMDGPU_UCODE_ID_UVD1: 2207 *type = GFX_FW_TYPE_UVD1; 2208 break; 2209 case AMDGPU_UCODE_ID_VCE: 2210 *type = GFX_FW_TYPE_VCE; 2211 break; 2212 case AMDGPU_UCODE_ID_VCN: 2213 *type = GFX_FW_TYPE_VCN; 2214 break; 2215 case AMDGPU_UCODE_ID_VCN1: 2216 *type = GFX_FW_TYPE_VCN1; 2217 break; 2218 case AMDGPU_UCODE_ID_DMCU_ERAM: 2219 *type = GFX_FW_TYPE_DMCU_ERAM; 2220 break; 2221 case AMDGPU_UCODE_ID_DMCU_INTV: 2222 *type = GFX_FW_TYPE_DMCU_ISR; 2223 break; 2224 case AMDGPU_UCODE_ID_VCN0_RAM: 2225 *type = GFX_FW_TYPE_VCN0_RAM; 2226 break; 2227 case AMDGPU_UCODE_ID_VCN1_RAM: 2228 *type = GFX_FW_TYPE_VCN1_RAM; 2229 break; 2230 case AMDGPU_UCODE_ID_DMCUB: 2231 *type = GFX_FW_TYPE_DMUB; 2232 break; 2233 case AMDGPU_UCODE_ID_MAXIMUM: 2234 default: 2235 return -EINVAL; 2236 } 2237 2238 return 0; 2239 } 2240 2241 static void psp_print_fw_hdr(struct psp_context *psp, 2242 struct amdgpu_firmware_info *ucode) 2243 { 2244 struct amdgpu_device *adev = psp->adev; 2245 struct common_firmware_header *hdr; 2246 2247 switch (ucode->ucode_id) { 2248 case AMDGPU_UCODE_ID_SDMA0: 2249 case AMDGPU_UCODE_ID_SDMA1: 2250 case AMDGPU_UCODE_ID_SDMA2: 2251 case AMDGPU_UCODE_ID_SDMA3: 2252 case AMDGPU_UCODE_ID_SDMA4: 2253 case AMDGPU_UCODE_ID_SDMA5: 2254 case AMDGPU_UCODE_ID_SDMA6: 2255 case AMDGPU_UCODE_ID_SDMA7: 2256 hdr = (struct common_firmware_header *) 2257 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2258 amdgpu_ucode_print_sdma_hdr(hdr); 2259 break; 2260 case AMDGPU_UCODE_ID_CP_CE: 2261 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2262 amdgpu_ucode_print_gfx_hdr(hdr); 2263 break; 2264 case AMDGPU_UCODE_ID_CP_PFP: 2265 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2266 amdgpu_ucode_print_gfx_hdr(hdr); 2267 break; 2268 case AMDGPU_UCODE_ID_CP_ME: 2269 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2270 amdgpu_ucode_print_gfx_hdr(hdr); 2271 break; 2272 case AMDGPU_UCODE_ID_CP_MEC1: 2273 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2274 amdgpu_ucode_print_gfx_hdr(hdr); 2275 break; 2276 case AMDGPU_UCODE_ID_RLC_G: 2277 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2278 amdgpu_ucode_print_rlc_hdr(hdr); 2279 break; 2280 case AMDGPU_UCODE_ID_SMC: 2281 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2282 amdgpu_ucode_print_smc_hdr(hdr); 2283 break; 2284 default: 2285 break; 2286 } 2287 } 2288 2289 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2290 struct psp_gfx_cmd_resp *cmd) 2291 { 2292 int ret; 2293 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2294 2295 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2296 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2297 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2298 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2299 2300 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2301 if (ret) 2302 DRM_ERROR("Unknown firmware type\n"); 2303 2304 return ret; 2305 } 2306 2307 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2308 struct amdgpu_firmware_info *ucode) 2309 { 2310 int ret = 0; 2311 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2312 2313 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2314 if (!ret) { 2315 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2316 psp->fence_buf_mc_addr); 2317 } 2318 2319 release_psp_cmd_buf(psp); 2320 2321 return ret; 2322 } 2323 2324 static int psp_load_smu_fw(struct psp_context *psp) 2325 { 2326 int ret; 2327 struct amdgpu_device *adev = psp->adev; 2328 struct amdgpu_firmware_info *ucode = 2329 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2330 struct amdgpu_ras *ras = psp->ras_context.ras; 2331 2332 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2333 return 0; 2334 2335 if ((amdgpu_in_reset(adev) && 2336 ras && adev->ras_enabled && 2337 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2338 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2339 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2340 if (ret) { 2341 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2342 } 2343 } 2344 2345 ret = psp_execute_non_psp_fw_load(psp, ucode); 2346 2347 if (ret) 2348 DRM_ERROR("PSP load smu failed!\n"); 2349 2350 return ret; 2351 } 2352 2353 static bool fw_load_skip_check(struct psp_context *psp, 2354 struct amdgpu_firmware_info *ucode) 2355 { 2356 if (!ucode->fw) 2357 return true; 2358 2359 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2360 (psp_smu_reload_quirk(psp) || 2361 psp->autoload_supported || 2362 psp->pmfw_centralized_cstate_management)) 2363 return true; 2364 2365 if (amdgpu_sriov_vf(psp->adev) && 2366 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2367 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2368 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2369 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2370 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2371 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2372 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2373 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2374 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2375 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2376 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2377 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2378 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2379 /*skip ucode loading in SRIOV VF */ 2380 return true; 2381 2382 if (psp->autoload_supported && 2383 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2384 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2385 /* skip mec JT when autoload is enabled */ 2386 return true; 2387 2388 return false; 2389 } 2390 2391 int psp_load_fw_list(struct psp_context *psp, 2392 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2393 { 2394 int ret = 0, i; 2395 struct amdgpu_firmware_info *ucode; 2396 2397 for (i = 0; i < ucode_count; ++i) { 2398 ucode = ucode_list[i]; 2399 psp_print_fw_hdr(psp, ucode); 2400 ret = psp_execute_non_psp_fw_load(psp, ucode); 2401 if (ret) 2402 return ret; 2403 } 2404 return ret; 2405 } 2406 2407 static int psp_load_non_psp_fw(struct psp_context *psp) 2408 { 2409 int i, ret; 2410 struct amdgpu_firmware_info *ucode; 2411 struct amdgpu_device *adev = psp->adev; 2412 2413 if (psp->autoload_supported && 2414 !psp->pmfw_centralized_cstate_management) { 2415 ret = psp_load_smu_fw(psp); 2416 if (ret) 2417 return ret; 2418 } 2419 2420 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2421 ucode = &adev->firmware.ucode[i]; 2422 2423 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2424 !fw_load_skip_check(psp, ucode)) { 2425 ret = psp_load_smu_fw(psp); 2426 if (ret) 2427 return ret; 2428 continue; 2429 } 2430 2431 if (fw_load_skip_check(psp, ucode)) 2432 continue; 2433 2434 if (psp->autoload_supported && 2435 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2436 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2437 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2438 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2439 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2440 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2441 /* PSP only receive one SDMA fw for sienna_cichlid, 2442 * as all four sdma fw are same */ 2443 continue; 2444 2445 psp_print_fw_hdr(psp, ucode); 2446 2447 ret = psp_execute_non_psp_fw_load(psp, ucode); 2448 if (ret) 2449 return ret; 2450 2451 /* Start rlc autoload after psp recieved all the gfx firmware */ 2452 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2453 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2454 ret = psp_rlc_autoload_start(psp); 2455 if (ret) { 2456 DRM_ERROR("Failed to start rlc autoload\n"); 2457 return ret; 2458 } 2459 } 2460 } 2461 2462 return 0; 2463 } 2464 2465 static int psp_load_fw(struct amdgpu_device *adev) 2466 { 2467 int ret; 2468 struct psp_context *psp = &adev->psp; 2469 2470 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2471 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */ 2472 goto skip_memalloc; 2473 } 2474 2475 if (amdgpu_sriov_vf(adev)) { 2476 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2477 AMDGPU_GEM_DOMAIN_VRAM, 2478 &psp->fw_pri_bo, 2479 &psp->fw_pri_mc_addr, 2480 &psp->fw_pri_buf); 2481 } else { 2482 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 2483 AMDGPU_GEM_DOMAIN_GTT, 2484 &psp->fw_pri_bo, 2485 &psp->fw_pri_mc_addr, 2486 &psp->fw_pri_buf); 2487 } 2488 2489 if (ret) 2490 goto failed; 2491 2492 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 2493 AMDGPU_GEM_DOMAIN_VRAM, 2494 &psp->fence_buf_bo, 2495 &psp->fence_buf_mc_addr, 2496 &psp->fence_buf); 2497 if (ret) 2498 goto failed; 2499 2500 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 2501 AMDGPU_GEM_DOMAIN_VRAM, 2502 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2503 (void **)&psp->cmd_buf_mem); 2504 if (ret) 2505 goto failed; 2506 2507 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2508 2509 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2510 if (ret) { 2511 DRM_ERROR("PSP ring init failed!\n"); 2512 goto failed; 2513 } 2514 2515 skip_memalloc: 2516 ret = psp_hw_start(psp); 2517 if (ret) 2518 goto failed; 2519 2520 ret = psp_load_non_psp_fw(psp); 2521 if (ret) 2522 goto failed; 2523 2524 ret = psp_asd_initialize(psp); 2525 if (ret) { 2526 DRM_ERROR("PSP load asd failed!\n"); 2527 return ret; 2528 } 2529 2530 ret = psp_rl_load(adev); 2531 if (ret) { 2532 DRM_ERROR("PSP load RL failed!\n"); 2533 return ret; 2534 } 2535 2536 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2537 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2538 ret = psp_xgmi_initialize(psp, false, true); 2539 /* Warning the XGMI seesion initialize failure 2540 * Instead of stop driver initialization 2541 */ 2542 if (ret) 2543 dev_err(psp->adev->dev, 2544 "XGMI: Failed to initialize XGMI session\n"); 2545 } 2546 } 2547 2548 if (psp->ta_fw) { 2549 ret = psp_ras_initialize(psp); 2550 if (ret) 2551 dev_err(psp->adev->dev, 2552 "RAS: Failed to initialize RAS\n"); 2553 2554 ret = psp_hdcp_initialize(psp); 2555 if (ret) 2556 dev_err(psp->adev->dev, 2557 "HDCP: Failed to initialize HDCP\n"); 2558 2559 ret = psp_dtm_initialize(psp); 2560 if (ret) 2561 dev_err(psp->adev->dev, 2562 "DTM: Failed to initialize DTM\n"); 2563 2564 ret = psp_rap_initialize(psp); 2565 if (ret) 2566 dev_err(psp->adev->dev, 2567 "RAP: Failed to initialize RAP\n"); 2568 2569 ret = psp_securedisplay_initialize(psp); 2570 if (ret) 2571 dev_err(psp->adev->dev, 2572 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2573 } 2574 2575 return 0; 2576 2577 failed: 2578 /* 2579 * all cleanup jobs (xgmi terminate, ras terminate, 2580 * ring destroy, cmd/fence/fw buffers destory, 2581 * psp->cmd destory) are delayed to psp_hw_fini 2582 */ 2583 return ret; 2584 } 2585 2586 static int psp_hw_init(void *handle) 2587 { 2588 int ret; 2589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2590 2591 mutex_lock(&adev->firmware.mutex); 2592 /* 2593 * This sequence is just used on hw_init only once, no need on 2594 * resume. 2595 */ 2596 ret = amdgpu_ucode_init_bo(adev); 2597 if (ret) 2598 goto failed; 2599 2600 ret = psp_load_fw(adev); 2601 if (ret) { 2602 DRM_ERROR("PSP firmware loading failed\n"); 2603 goto failed; 2604 } 2605 2606 mutex_unlock(&adev->firmware.mutex); 2607 return 0; 2608 2609 failed: 2610 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2611 mutex_unlock(&adev->firmware.mutex); 2612 return -EINVAL; 2613 } 2614 2615 static int psp_hw_fini(void *handle) 2616 { 2617 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2618 struct psp_context *psp = &adev->psp; 2619 2620 if (psp->ta_fw) { 2621 psp_ras_terminate(psp); 2622 psp_securedisplay_terminate(psp); 2623 psp_rap_terminate(psp); 2624 psp_dtm_terminate(psp); 2625 psp_hdcp_terminate(psp); 2626 } 2627 2628 psp_asd_terminate(psp); 2629 2630 psp_tmr_terminate(psp); 2631 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2632 2633 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 2634 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 2635 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 2636 &psp->fence_buf_mc_addr, &psp->fence_buf); 2637 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 2638 (void **)&psp->cmd_buf_mem); 2639 2640 return 0; 2641 } 2642 2643 static int psp_suspend(void *handle) 2644 { 2645 int ret; 2646 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2647 struct psp_context *psp = &adev->psp; 2648 2649 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2650 psp->xgmi_context.context.initialized) { 2651 ret = psp_xgmi_terminate(psp); 2652 if (ret) { 2653 DRM_ERROR("Failed to terminate xgmi ta\n"); 2654 return ret; 2655 } 2656 } 2657 2658 if (psp->ta_fw) { 2659 ret = psp_ras_terminate(psp); 2660 if (ret) { 2661 DRM_ERROR("Failed to terminate ras ta\n"); 2662 return ret; 2663 } 2664 ret = psp_hdcp_terminate(psp); 2665 if (ret) { 2666 DRM_ERROR("Failed to terminate hdcp ta\n"); 2667 return ret; 2668 } 2669 ret = psp_dtm_terminate(psp); 2670 if (ret) { 2671 DRM_ERROR("Failed to terminate dtm ta\n"); 2672 return ret; 2673 } 2674 ret = psp_rap_terminate(psp); 2675 if (ret) { 2676 DRM_ERROR("Failed to terminate rap ta\n"); 2677 return ret; 2678 } 2679 ret = psp_securedisplay_terminate(psp); 2680 if (ret) { 2681 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2682 return ret; 2683 } 2684 } 2685 2686 ret = psp_asd_terminate(psp); 2687 if (ret) { 2688 DRM_ERROR("Failed to terminate asd\n"); 2689 return ret; 2690 } 2691 2692 ret = psp_tmr_terminate(psp); 2693 if (ret) { 2694 DRM_ERROR("Failed to terminate tmr\n"); 2695 return ret; 2696 } 2697 2698 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2699 if (ret) { 2700 DRM_ERROR("PSP ring stop failed\n"); 2701 return ret; 2702 } 2703 2704 return 0; 2705 } 2706 2707 static int psp_resume(void *handle) 2708 { 2709 int ret; 2710 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2711 struct psp_context *psp = &adev->psp; 2712 2713 DRM_INFO("PSP is resuming...\n"); 2714 2715 if (psp->mem_train_ctx.enable_mem_training) { 2716 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2717 if (ret) { 2718 DRM_ERROR("Failed to process memory training!\n"); 2719 return ret; 2720 } 2721 } 2722 2723 mutex_lock(&adev->firmware.mutex); 2724 2725 ret = psp_hw_start(psp); 2726 if (ret) 2727 goto failed; 2728 2729 ret = psp_load_non_psp_fw(psp); 2730 if (ret) 2731 goto failed; 2732 2733 ret = psp_asd_initialize(psp); 2734 if (ret) { 2735 DRM_ERROR("PSP load asd failed!\n"); 2736 goto failed; 2737 } 2738 2739 ret = psp_rl_load(adev); 2740 if (ret) { 2741 dev_err(adev->dev, "PSP load RL failed!\n"); 2742 goto failed; 2743 } 2744 2745 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2746 ret = psp_xgmi_initialize(psp, false, true); 2747 /* Warning the XGMI seesion initialize failure 2748 * Instead of stop driver initialization 2749 */ 2750 if (ret) 2751 dev_err(psp->adev->dev, 2752 "XGMI: Failed to initialize XGMI session\n"); 2753 } 2754 2755 if (psp->ta_fw) { 2756 ret = psp_ras_initialize(psp); 2757 if (ret) 2758 dev_err(psp->adev->dev, 2759 "RAS: Failed to initialize RAS\n"); 2760 2761 ret = psp_hdcp_initialize(psp); 2762 if (ret) 2763 dev_err(psp->adev->dev, 2764 "HDCP: Failed to initialize HDCP\n"); 2765 2766 ret = psp_dtm_initialize(psp); 2767 if (ret) 2768 dev_err(psp->adev->dev, 2769 "DTM: Failed to initialize DTM\n"); 2770 2771 ret = psp_rap_initialize(psp); 2772 if (ret) 2773 dev_err(psp->adev->dev, 2774 "RAP: Failed to initialize RAP\n"); 2775 2776 ret = psp_securedisplay_initialize(psp); 2777 if (ret) 2778 dev_err(psp->adev->dev, 2779 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2780 } 2781 2782 mutex_unlock(&adev->firmware.mutex); 2783 2784 return 0; 2785 2786 failed: 2787 DRM_ERROR("PSP resume failed\n"); 2788 mutex_unlock(&adev->firmware.mutex); 2789 return ret; 2790 } 2791 2792 int psp_gpu_reset(struct amdgpu_device *adev) 2793 { 2794 int ret; 2795 2796 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2797 return 0; 2798 2799 mutex_lock(&adev->psp.mutex); 2800 ret = psp_mode1_reset(&adev->psp); 2801 mutex_unlock(&adev->psp.mutex); 2802 2803 return ret; 2804 } 2805 2806 int psp_rlc_autoload_start(struct psp_context *psp) 2807 { 2808 int ret; 2809 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2810 2811 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2812 2813 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2814 psp->fence_buf_mc_addr); 2815 2816 release_psp_cmd_buf(psp); 2817 2818 return ret; 2819 } 2820 2821 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2822 uint64_t cmd_gpu_addr, int cmd_size) 2823 { 2824 struct amdgpu_firmware_info ucode = {0}; 2825 2826 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2827 AMDGPU_UCODE_ID_VCN0_RAM; 2828 ucode.mc_addr = cmd_gpu_addr; 2829 ucode.ucode_size = cmd_size; 2830 2831 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2832 } 2833 2834 int psp_ring_cmd_submit(struct psp_context *psp, 2835 uint64_t cmd_buf_mc_addr, 2836 uint64_t fence_mc_addr, 2837 int index) 2838 { 2839 unsigned int psp_write_ptr_reg = 0; 2840 struct psp_gfx_rb_frame *write_frame; 2841 struct psp_ring *ring = &psp->km_ring; 2842 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2843 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2844 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2845 struct amdgpu_device *adev = psp->adev; 2846 uint32_t ring_size_dw = ring->ring_size / 4; 2847 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2848 2849 /* KM (GPCOM) prepare write pointer */ 2850 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2851 2852 /* Update KM RB frame pointer to new frame */ 2853 /* write_frame ptr increments by size of rb_frame in bytes */ 2854 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2855 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2856 write_frame = ring_buffer_start; 2857 else 2858 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2859 /* Check invalid write_frame ptr address */ 2860 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2861 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2862 ring_buffer_start, ring_buffer_end, write_frame); 2863 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2864 return -EINVAL; 2865 } 2866 2867 /* Initialize KM RB frame */ 2868 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2869 2870 /* Update KM RB frame */ 2871 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2872 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2873 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2874 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2875 write_frame->fence_value = index; 2876 amdgpu_device_flush_hdp(adev, NULL); 2877 2878 /* Update the write Pointer in DWORDs */ 2879 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2880 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2881 return 0; 2882 } 2883 2884 int psp_init_asd_microcode(struct psp_context *psp, 2885 const char *chip_name) 2886 { 2887 struct amdgpu_device *adev = psp->adev; 2888 char fw_name[PSP_FW_NAME_LEN]; 2889 const struct psp_firmware_header_v1_0 *asd_hdr; 2890 int err = 0; 2891 2892 if (!chip_name) { 2893 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2894 return -EINVAL; 2895 } 2896 2897 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2898 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2899 if (err) 2900 goto out; 2901 2902 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2903 if (err) 2904 goto out; 2905 2906 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2907 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2908 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2909 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2910 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2911 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2912 return 0; 2913 out: 2914 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2915 release_firmware(adev->psp.asd_fw); 2916 adev->psp.asd_fw = NULL; 2917 return err; 2918 } 2919 2920 int psp_init_toc_microcode(struct psp_context *psp, 2921 const char *chip_name) 2922 { 2923 struct amdgpu_device *adev = psp->adev; 2924 char fw_name[PSP_FW_NAME_LEN]; 2925 const struct psp_firmware_header_v1_0 *toc_hdr; 2926 int err = 0; 2927 2928 if (!chip_name) { 2929 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2930 return -EINVAL; 2931 } 2932 2933 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2934 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2935 if (err) 2936 goto out; 2937 2938 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2939 if (err) 2940 goto out; 2941 2942 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2943 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2944 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2945 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2946 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2947 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2948 return 0; 2949 out: 2950 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2951 release_firmware(adev->psp.toc_fw); 2952 adev->psp.toc_fw = NULL; 2953 return err; 2954 } 2955 2956 static int parse_sos_bin_descriptor(struct psp_context *psp, 2957 const struct psp_fw_bin_desc *desc, 2958 const struct psp_firmware_header_v2_0 *sos_hdr) 2959 { 2960 uint8_t *ucode_start_addr = NULL; 2961 2962 if (!psp || !desc || !sos_hdr) 2963 return -EINVAL; 2964 2965 ucode_start_addr = (uint8_t *)sos_hdr + 2966 le32_to_cpu(desc->offset_bytes) + 2967 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 2968 2969 switch (desc->fw_type) { 2970 case PSP_FW_TYPE_PSP_SOS: 2971 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 2972 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 2973 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 2974 psp->sos.start_addr = ucode_start_addr; 2975 break; 2976 case PSP_FW_TYPE_PSP_SYS_DRV: 2977 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 2978 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 2979 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 2980 psp->sys.start_addr = ucode_start_addr; 2981 break; 2982 case PSP_FW_TYPE_PSP_KDB: 2983 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 2984 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 2985 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 2986 psp->kdb.start_addr = ucode_start_addr; 2987 break; 2988 case PSP_FW_TYPE_PSP_TOC: 2989 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 2990 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 2991 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 2992 psp->toc.start_addr = ucode_start_addr; 2993 break; 2994 case PSP_FW_TYPE_PSP_SPL: 2995 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 2996 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 2997 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 2998 psp->spl.start_addr = ucode_start_addr; 2999 break; 3000 case PSP_FW_TYPE_PSP_RL: 3001 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3002 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3003 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3004 psp->rl.start_addr = ucode_start_addr; 3005 break; 3006 case PSP_FW_TYPE_PSP_SOC_DRV: 3007 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3008 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3009 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3010 psp->soc_drv.start_addr = ucode_start_addr; 3011 break; 3012 case PSP_FW_TYPE_PSP_INTF_DRV: 3013 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3014 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3015 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3016 psp->intf_drv.start_addr = ucode_start_addr; 3017 break; 3018 case PSP_FW_TYPE_PSP_DBG_DRV: 3019 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3020 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3021 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3022 psp->dbg_drv.start_addr = ucode_start_addr; 3023 break; 3024 default: 3025 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3026 break; 3027 } 3028 3029 return 0; 3030 } 3031 3032 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3033 { 3034 const struct psp_firmware_header_v1_0 *sos_hdr; 3035 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3036 uint8_t *ucode_array_start_addr; 3037 3038 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3039 ucode_array_start_addr = (uint8_t *)sos_hdr + 3040 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3041 3042 if (adev->gmc.xgmi.connected_to_cpu || 3043 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3044 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3045 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3046 3047 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3048 adev->psp.sys.start_addr = ucode_array_start_addr; 3049 3050 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3051 adev->psp.sos.start_addr = ucode_array_start_addr + 3052 le32_to_cpu(sos_hdr->sos.offset_bytes); 3053 } else { 3054 /* Load alternate PSP SOS FW */ 3055 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3056 3057 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3058 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3059 3060 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3061 adev->psp.sys.start_addr = ucode_array_start_addr + 3062 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3063 3064 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3065 adev->psp.sos.start_addr = ucode_array_start_addr + 3066 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3067 } 3068 3069 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3070 dev_warn(adev->dev, "PSP SOS FW not available"); 3071 return -EINVAL; 3072 } 3073 3074 return 0; 3075 } 3076 3077 int psp_init_sos_microcode(struct psp_context *psp, 3078 const char *chip_name) 3079 { 3080 struct amdgpu_device *adev = psp->adev; 3081 char fw_name[PSP_FW_NAME_LEN]; 3082 const struct psp_firmware_header_v1_0 *sos_hdr; 3083 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3084 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3085 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3086 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3087 int err = 0; 3088 uint8_t *ucode_array_start_addr; 3089 int fw_index = 0; 3090 3091 if (!chip_name) { 3092 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3093 return -EINVAL; 3094 } 3095 3096 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3097 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3098 if (err) 3099 goto out; 3100 3101 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3102 if (err) 3103 goto out; 3104 3105 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3106 ucode_array_start_addr = (uint8_t *)sos_hdr + 3107 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3108 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3109 3110 switch (sos_hdr->header.header_version_major) { 3111 case 1: 3112 err = psp_init_sos_base_fw(adev); 3113 if (err) 3114 goto out; 3115 3116 if (sos_hdr->header.header_version_minor == 1) { 3117 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3118 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3119 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3120 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3121 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3122 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3123 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3124 } 3125 if (sos_hdr->header.header_version_minor == 2) { 3126 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3127 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3128 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3129 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3130 } 3131 if (sos_hdr->header.header_version_minor == 3) { 3132 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3133 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3134 adev->psp.toc.start_addr = ucode_array_start_addr + 3135 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3136 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3137 adev->psp.kdb.start_addr = ucode_array_start_addr + 3138 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3139 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3140 adev->psp.spl.start_addr = ucode_array_start_addr + 3141 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3142 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3143 adev->psp.rl.start_addr = ucode_array_start_addr + 3144 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3145 } 3146 break; 3147 case 2: 3148 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3149 3150 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3151 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3152 err = -EINVAL; 3153 goto out; 3154 } 3155 3156 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3157 err = parse_sos_bin_descriptor(psp, 3158 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3159 sos_hdr_v2_0); 3160 if (err) 3161 goto out; 3162 } 3163 break; 3164 default: 3165 dev_err(adev->dev, 3166 "unsupported psp sos firmware\n"); 3167 err = -EINVAL; 3168 goto out; 3169 } 3170 3171 return 0; 3172 out: 3173 dev_err(adev->dev, 3174 "failed to init sos firmware\n"); 3175 release_firmware(adev->psp.sos_fw); 3176 adev->psp.sos_fw = NULL; 3177 3178 return err; 3179 } 3180 3181 static int parse_ta_bin_descriptor(struct psp_context *psp, 3182 const struct psp_fw_bin_desc *desc, 3183 const struct ta_firmware_header_v2_0 *ta_hdr) 3184 { 3185 uint8_t *ucode_start_addr = NULL; 3186 3187 if (!psp || !desc || !ta_hdr) 3188 return -EINVAL; 3189 3190 ucode_start_addr = (uint8_t *)ta_hdr + 3191 le32_to_cpu(desc->offset_bytes) + 3192 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3193 3194 switch (desc->fw_type) { 3195 case TA_FW_TYPE_PSP_ASD: 3196 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3197 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3198 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3199 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3200 break; 3201 case TA_FW_TYPE_PSP_XGMI: 3202 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3203 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3204 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3205 break; 3206 case TA_FW_TYPE_PSP_RAS: 3207 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3208 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3209 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3210 break; 3211 case TA_FW_TYPE_PSP_HDCP: 3212 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3213 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3214 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3215 break; 3216 case TA_FW_TYPE_PSP_DTM: 3217 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3218 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3219 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3220 break; 3221 case TA_FW_TYPE_PSP_RAP: 3222 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3223 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3224 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3225 break; 3226 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3227 psp->securedisplay_context.context.bin_desc.fw_version = 3228 le32_to_cpu(desc->fw_version); 3229 psp->securedisplay_context.context.bin_desc.size_bytes = 3230 le32_to_cpu(desc->size_bytes); 3231 psp->securedisplay_context.context.bin_desc.start_addr = 3232 ucode_start_addr; 3233 break; 3234 default: 3235 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3236 break; 3237 } 3238 3239 return 0; 3240 } 3241 3242 int psp_init_ta_microcode(struct psp_context *psp, 3243 const char *chip_name) 3244 { 3245 struct amdgpu_device *adev = psp->adev; 3246 char fw_name[PSP_FW_NAME_LEN]; 3247 const struct ta_firmware_header_v2_0 *ta_hdr; 3248 int err = 0; 3249 int ta_index = 0; 3250 3251 if (!chip_name) { 3252 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3253 return -EINVAL; 3254 } 3255 3256 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3257 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3258 if (err) 3259 goto out; 3260 3261 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3262 if (err) 3263 goto out; 3264 3265 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3266 3267 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3268 dev_err(adev->dev, "unsupported TA header version\n"); 3269 err = -EINVAL; 3270 goto out; 3271 } 3272 3273 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3274 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3275 err = -EINVAL; 3276 goto out; 3277 } 3278 3279 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3280 err = parse_ta_bin_descriptor(psp, 3281 &ta_hdr->ta_fw_bin[ta_index], 3282 ta_hdr); 3283 if (err) 3284 goto out; 3285 } 3286 3287 return 0; 3288 out: 3289 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3290 release_firmware(adev->psp.ta_fw); 3291 adev->psp.ta_fw = NULL; 3292 return err; 3293 } 3294 3295 int psp_init_cap_microcode(struct psp_context *psp, 3296 const char *chip_name) 3297 { 3298 struct amdgpu_device *adev = psp->adev; 3299 char fw_name[PSP_FW_NAME_LEN]; 3300 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3301 struct amdgpu_firmware_info *info = NULL; 3302 int err = 0; 3303 3304 if (!chip_name) { 3305 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3306 return -EINVAL; 3307 } 3308 3309 if (!amdgpu_sriov_vf(adev)) { 3310 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3311 return -EINVAL; 3312 } 3313 3314 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3315 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3316 if (err) { 3317 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3318 err = 0; 3319 goto out; 3320 } 3321 3322 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3323 if (err) { 3324 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3325 goto out; 3326 } 3327 3328 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3329 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3330 info->fw = adev->psp.cap_fw; 3331 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3332 adev->psp.cap_fw->data; 3333 adev->firmware.fw_size += ALIGN( 3334 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3335 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3336 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3337 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3338 3339 return 0; 3340 3341 out: 3342 release_firmware(adev->psp.cap_fw); 3343 adev->psp.cap_fw = NULL; 3344 return err; 3345 } 3346 3347 static int psp_set_clockgating_state(void *handle, 3348 enum amd_clockgating_state state) 3349 { 3350 return 0; 3351 } 3352 3353 static int psp_set_powergating_state(void *handle, 3354 enum amd_powergating_state state) 3355 { 3356 return 0; 3357 } 3358 3359 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3360 struct device_attribute *attr, 3361 char *buf) 3362 { 3363 struct drm_device *ddev = dev_get_drvdata(dev); 3364 struct amdgpu_device *adev = drm_to_adev(ddev); 3365 uint32_t fw_ver; 3366 int ret; 3367 3368 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3369 DRM_INFO("PSP block is not ready yet."); 3370 return -EBUSY; 3371 } 3372 3373 mutex_lock(&adev->psp.mutex); 3374 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3375 mutex_unlock(&adev->psp.mutex); 3376 3377 if (ret) { 3378 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3379 return ret; 3380 } 3381 3382 return sysfs_emit(buf, "%x\n", fw_ver); 3383 } 3384 3385 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3386 struct device_attribute *attr, 3387 const char *buf, 3388 size_t count) 3389 { 3390 struct drm_device *ddev = dev_get_drvdata(dev); 3391 struct amdgpu_device *adev = drm_to_adev(ddev); 3392 int ret, idx; 3393 char fw_name[100]; 3394 const struct firmware *usbc_pd_fw; 3395 struct amdgpu_bo *fw_buf_bo = NULL; 3396 uint64_t fw_pri_mc_addr; 3397 void *fw_pri_cpu_addr; 3398 3399 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3400 DRM_INFO("PSP block is not ready yet."); 3401 return -EBUSY; 3402 } 3403 3404 if (!drm_dev_enter(ddev, &idx)) 3405 return -ENODEV; 3406 3407 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3408 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3409 if (ret) 3410 goto fail; 3411 3412 /* LFB address which is aligned to 1MB boundary per PSP request */ 3413 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3414 AMDGPU_GEM_DOMAIN_VRAM, 3415 &fw_buf_bo, 3416 &fw_pri_mc_addr, 3417 &fw_pri_cpu_addr); 3418 if (ret) 3419 goto rel_buf; 3420 3421 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3422 3423 mutex_lock(&adev->psp.mutex); 3424 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3425 mutex_unlock(&adev->psp.mutex); 3426 3427 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3428 3429 rel_buf: 3430 release_firmware(usbc_pd_fw); 3431 fail: 3432 if (ret) { 3433 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3434 count = ret; 3435 } 3436 3437 drm_dev_exit(idx); 3438 return count; 3439 } 3440 3441 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3442 { 3443 int idx; 3444 3445 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3446 return; 3447 3448 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3449 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3450 3451 drm_dev_exit(idx); 3452 } 3453 3454 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3455 psp_usbc_pd_fw_sysfs_read, 3456 psp_usbc_pd_fw_sysfs_write); 3457 3458 int is_psp_fw_valid(struct psp_bin_desc bin) 3459 { 3460 return bin.size_bytes; 3461 } 3462 3463 const struct amd_ip_funcs psp_ip_funcs = { 3464 .name = "psp", 3465 .early_init = psp_early_init, 3466 .late_init = NULL, 3467 .sw_init = psp_sw_init, 3468 .sw_fini = psp_sw_fini, 3469 .hw_init = psp_hw_init, 3470 .hw_fini = psp_hw_fini, 3471 .suspend = psp_suspend, 3472 .resume = psp_resume, 3473 .is_idle = NULL, 3474 .check_soft_reset = NULL, 3475 .wait_for_idle = NULL, 3476 .soft_reset = NULL, 3477 .set_clockgating_state = psp_set_clockgating_state, 3478 .set_powergating_state = psp_set_powergating_state, 3479 }; 3480 3481 static int psp_sysfs_init(struct amdgpu_device *adev) 3482 { 3483 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3484 3485 if (ret) 3486 DRM_ERROR("Failed to create USBC PD FW control file!"); 3487 3488 return ret; 3489 } 3490 3491 static void psp_sysfs_fini(struct amdgpu_device *adev) 3492 { 3493 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3494 } 3495 3496 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3497 { 3498 .type = AMD_IP_BLOCK_TYPE_PSP, 3499 .major = 3, 3500 .minor = 1, 3501 .rev = 0, 3502 .funcs = &psp_ip_funcs, 3503 }; 3504 3505 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3506 { 3507 .type = AMD_IP_BLOCK_TYPE_PSP, 3508 .major = 10, 3509 .minor = 0, 3510 .rev = 0, 3511 .funcs = &psp_ip_funcs, 3512 }; 3513 3514 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3515 { 3516 .type = AMD_IP_BLOCK_TYPE_PSP, 3517 .major = 11, 3518 .minor = 0, 3519 .rev = 0, 3520 .funcs = &psp_ip_funcs, 3521 }; 3522 3523 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3524 .type = AMD_IP_BLOCK_TYPE_PSP, 3525 .major = 11, 3526 .minor = 0, 3527 .rev = 8, 3528 .funcs = &psp_ip_funcs, 3529 }; 3530 3531 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3532 { 3533 .type = AMD_IP_BLOCK_TYPE_PSP, 3534 .major = 12, 3535 .minor = 0, 3536 .rev = 0, 3537 .funcs = &psp_ip_funcs, 3538 }; 3539 3540 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3541 .type = AMD_IP_BLOCK_TYPE_PSP, 3542 .major = 13, 3543 .minor = 0, 3544 .rev = 0, 3545 .funcs = &psp_ip_funcs, 3546 }; 3547